diff mbox

[U-Boot,2/2] powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs

Message ID 1296852117-1500-2-git-send-email-galak@kernel.crashing.org
State Accepted
Delegated to: Kumar Gala
Headers show

Commit Message

Kumar Gala Feb. 4, 2011, 8:41 p.m. UTC
From: Haiying Wang <Haiying.Wang@freescale.com>

There are some differences between CoreNet (P2040, P3041, P5020, P4080)
and and non-CoreNet (P1017, P1023) based SoCs in what features exist and
the memory maps.

* Rename various immap defines to remove _CORENET_ if they are shared
* Added P1023/P1017 specific memory offsets
* Only setup LIODNs or LIODN related code on CORENET based SoCs
  (features doesn't exist on P1023/P1017)

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 arch/powerpc/cpu/mpc85xx/Makefile     |    2 +-
 arch/powerpc/cpu/mpc85xx/portals.c    |   32 +++++++++++++++++++++++---------
 arch/powerpc/cpu/mpc85xx/speed.c      |    7 +++++++
 arch/powerpc/include/asm/fsl_liodn.h  |   10 +++++-----
 arch/powerpc/include/asm/immap_85xx.h |   12 ++++++------
 include/configs/corenet_ds.h          |    1 +
 6 files changed, 43 insertions(+), 21 deletions(-)

Comments

Kumar Gala Feb. 10, 2011, 5:26 a.m. UTC | #1
On Feb 4, 2011, at 2:41 PM, Kumar Gala wrote:

> From: Haiying Wang <Haiying.Wang@freescale.com>
> 
> There are some differences between CoreNet (P2040, P3041, P5020, P4080)
> and and non-CoreNet (P1017, P1023) based SoCs in what features exist and
> the memory maps.
> 
> * Rename various immap defines to remove _CORENET_ if they are shared
> * Added P1023/P1017 specific memory offsets
> * Only setup LIODNs or LIODN related code on CORENET based SoCs
> (features doesn't exist on P1023/P1017)
> 
> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/cpu/mpc85xx/Makefile     |    2 +-
> arch/powerpc/cpu/mpc85xx/portals.c    |   32 +++++++++++++++++++++++---------
> arch/powerpc/cpu/mpc85xx/speed.c      |    7 +++++++
> arch/powerpc/include/asm/fsl_liodn.h  |   10 +++++-----
> arch/powerpc/include/asm/immap_85xx.h |   12 ++++++------
> include/configs/corenet_ds.h          |    1 +
> 6 files changed, 43 insertions(+), 21 deletions(-)

applied to 85xx next

- k
diff mbox

Patch

diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index cc16db3..5791be0 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -69,7 +69,7 @@  COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 COBJS-$(CONFIG_FSL_CORENET) += liodn.o
 COBJS-$(CONFIG_MP)	+= mp.o
 COBJS-$(CONFIG_PCI)	+= pci.o
-COBJS-$(CONFIG_FSL_CORENET) += portals.o
+COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
 
 # various SoC specific assignments
 COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c
index 01aec6e..e8d53bb 100644
--- a/arch/powerpc/cpu/mpc85xx/portals.c
+++ b/arch/powerpc/cpu/mpc85xx/portals.c
@@ -1,5 +1,5 @@ 
 /*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -30,18 +30,13 @@ 
 #include <asm/fsl_portals.h>
 #include <asm/fsl_liodn.h>
 
-static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_CORENET_QMAN_ADDR;
+static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
 
 void setup_portals(void)
 {
+#ifdef CONFIG_FSL_CORENET
 	int i;
 
-	/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
-#ifdef CONFIG_PHYS_64BIT
-	out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
-#endif
-	out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
-
 	for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
 		u8 sdest = qp_info[i].sdest;
 		u16 fliodn = qp_info[i].fliodn;
@@ -53,6 +48,13 @@  void setup_portals(void)
 		/* set frame liodn */
 		out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
 	}
+#endif
+
+	/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
+#ifdef CONFIG_PHYS_64BIT
+	out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
+#endif
+	out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
 }
 
 /* Update portal containter to match LAW setup of portal in phy map */
@@ -118,9 +120,12 @@  void fdt_portal(void *blob, const char *compat, const char *container,
 static int fdt_qportal(void *blob, int off, int id, char *name,
 		       enum fsl_dpaa_dev dev, int create)
 {
-	int childoff, dev_off, num, ret = 0;
+	int childoff, dev_off, ret = 0;
 	uint32_t dev_handle;
+#ifdef CONFIG_FSL_CORENET
+	int num;
 	u32 liodns[2];
+#endif
 
 	childoff = fdt_subnode_offset(blob, off, name);
 	if (create) {
@@ -154,9 +159,11 @@  static int fdt_qportal(void *blob, int off, int id, char *name,
 			if (ret < 0)
 				return ret;
 
+#ifdef CONFIG_FSL_CORENET
 			num = get_dpaa_liodn(dev, &liodns[0], id);
 			ret = fdt_setprop(blob, childoff, "fsl,liodn",
 					  &liodns[0], sizeof(u32) * num);
+#endif
 		} else {
 			return childoff;
 		}
@@ -184,7 +191,9 @@  void fdt_fixup_qportals(void *blob)
 
 	off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
 	while (off != -FDT_ERR_NOTFOUND) {
+#ifdef CONFIG_FSL_CORENET
 		u32 liodns[2];
+#endif
 		const int *ci = fdt_getprop(blob, off, "cell-index", NULL);
 		int j, i = *ci;
 
@@ -192,6 +201,7 @@  void fdt_fixup_qportals(void *blob)
 		if (err < 0)
 			goto err;
 
+#ifdef CONFIG_FSL_CORENET
 		liodns[0] = qp_info[i].dliodn;
 		liodns[1] = qp_info[i].fliodn;
 
@@ -199,6 +209,7 @@  void fdt_fixup_qportals(void *blob)
 				  &liodns, sizeof(u32) * 2);
 		if (err < 0)
 			goto err;
+#endif
 
 		i++;
 
@@ -207,6 +218,7 @@  void fdt_fixup_qportals(void *blob)
 		if (err < 0)
 			goto err;
 
+#ifdef CONFIG_FSL_CORENET
 #ifdef CONFIG_SYS_DPAA_PME
 		err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1);
 		if (err < 0)
@@ -214,6 +226,8 @@  void fdt_fixup_qportals(void *blob)
 #else
 		fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0);
 #endif
+#endif
+
 #ifdef CONFIG_SYS_DPAA_FMAN
 		for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
 			char name[] = "fman@0";
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index f2aa8d0..d440b6a 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -170,6 +170,13 @@  void get_sys_info (sys_info_t * sysInfo)
 	sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
 #endif
 
+#ifdef CONFIG_SYS_DPAA_FMAN
+		sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
+#if (CONFIG_SYS_NUM_FMAN) == 2
+		sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
+#endif
+#endif
+
 #if defined(CONFIG_FSL_LBC)
 #if defined(CONFIG_SYS_LBC_LCRR)
 	/* We will program LCRR to this value later */
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index 4c17fe2..f76676c 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -1,5 +1,5 @@ 
 /*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -85,13 +85,13 @@  extern void fdt_fixup_liodn(void *blob);
 
 #define SET_QMAN_LIODN(liodn) \
 	SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \
-		CONFIG_SYS_FSL_CORENET_QMAN_OFFSET, \
-		CONFIG_SYS_FSL_CORENET_QMAN_OFFSET)
+		CONFIG_SYS_FSL_QMAN_OFFSET, \
+		CONFIG_SYS_FSL_QMAN_OFFSET)
 
 #define SET_BMAN_LIODN(liodn) \
 	SET_LIODN_ENTRY_1("fsl,bman", liodn, offsetof(ccsr_bman_t, liodnr) + \
-		CONFIG_SYS_FSL_CORENET_BMAN_OFFSET, \
-		CONFIG_SYS_FSL_CORENET_BMAN_OFFSET)
+		CONFIG_SYS_FSL_BMAN_OFFSET, \
+		CONFIG_SYS_FSL_BMAN_OFFSET)
 
 #define SET_PME_LIODN(liodn) \
 	SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index ce27fec..d26d648 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2204,8 +2204,8 @@  typedef struct ccsr_pme {
 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET		0x221000
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x300000
 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET	0x316000
-#define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET	0x318000
-#define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET	0x31a000
+#define CONFIG_SYS_FSL_QMAN_OFFSET		0x318000
+#define CONFIG_SYS_FSL_BMAN_OFFSET		0x31a000
 #define CONFIG_SYS_FSL_FM1_OFFSET		0x400000
 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET	0x488000
 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET	0x489000
@@ -2268,10 +2268,10 @@  typedef struct ccsr_pme {
 
 #define CONFIG_SYS_FSL_CPC_ADDR	\
 	(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_QMAN_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET)
+#define CONFIG_SYS_FSL_QMAN_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
+#define CONFIG_SYS_FSL_BMAN_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_PME_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
 #define CONFIG_SYS_MPC85xx_GUTS_ADDR \
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index bff212e..7bafa05 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -357,6 +357,7 @@ 
 #define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
 
 /* Qman/Bman */
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	10
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #ifdef CONFIG_PHYS_64BIT