| Message ID | 1294817626-4727-1-git-send-email-b21989@freescale.com |
|---|---|
| State | Superseded |
| Headers | show |
Dear Shaohui Xie, In message <1294817626-4727-1-git-send-email-b21989@freescale.com> you wrote: > PBL(pre-boot loader): SPI flash used as RCW(Reset Configuration Word) and > PBI(pre-boot initialization) source, CPC(CoreNet Platform Cache) used as 1M SRAM > where PBL will copy whole U-BOOT image to, U-boot can boot from CPC after PBL > completes RCW and PBI phases. > > Signed-off-by: Chunhe Lan <b25806@freescale.com> > Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> > Signed-off-by: Shaohui Xie <b21989@freescale.com> > --- > Use CONFIG_RAMBOOT_PBL instead of CONFIG_PBL_BOOT_INDIRECT according to Kumar's comment. CONFIG_RAMBOOT_PBL needs to be documented in the README! > diff --git a/board/freescale/corenet_ds/config.mk b/board/freescale/corenet_ds/config.mk > index 15bbf20..918775d 100644 > --- a/board/freescale/corenet_ds/config.mk > +++ b/board/freescale/corenet_ds/config.mk > @@ -24,4 +24,10 @@ > # P4080DS board > # > > +ifeq ($(CONFIG_RAMBOOT_PBL), y) > +RESET_VECTOR_ADDRESS = 0xfffffffc > +endif > + > +ifndef RESET_VECTOR_ADDRESS > RESET_VECTOR_ADDRESS = 0xeffffffc > +endif Do we really need this? Can this not be moved into the board config file, so we gan delete the config.mk ? > /* TLB 1 */ > /* *I*** - Covers boot page */ > +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) > + /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the > + * SRAM is at 0xfff00000, it covered the 0xfffff000. > + * */ Incorrect multiline comment style. Please fix globally. > --- a/include/configs/corenet_ds.h > +++ b/include/configs/corenet_ds.h > @@ -28,6 +28,10 @@ > > #include "../board/freescale/common/ics307_clk.h" > > +#ifdef CONFIG_RAMBOOT_PBL > +#define CONFIG_RAMBOOT_TEXT_BASE 0xfff80000 > +#endif Why is this needed? You already set SYS_TEXT_BASE to that value. > @@ -62,11 +66,17 @@ > #ifdef CONFIG_SYS_NO_FLASH > #define CONFIG_ENV_IS_NOWHERE > #else > -#define CONFIG_ENV_IS_IN_FLASH Why remove the CONFIG_ENV_IS_IN_FLASH here, but leave the CONFIG_ENV_IS_NOWHERE above? > #define CONFIG_FLASH_CFI_DRIVER > #define CONFIG_SYS_FLASH_CFI > #endif > > +#if defined(CONFIG_RAMBOOT_PBL) > + #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ > +#else > + #define CONFIG_ENV_IS_IN_FLASH > + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) > +#endif See previous comment. This should be cleaned up. For example, move this block up, and set CONFIG_SYS_NO_FLASH instead. > +#define CONFIG_SYS_L3_SIZE (1024 << 10) > +#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) > + > + > +/* Drop one of the blank lines, please. Best regards, Wolfgang Denk
On Jan 12, 2011, at 2:10 AM, Wolfgang Denk wrote: >> diff --git a/board/freescale/corenet_ds/config.mk b/board/freescale/corenet_ds/config.mk >> index 15bbf20..918775d 100644 >> --- a/board/freescale/corenet_ds/config.mk >> +++ b/board/freescale/corenet_ds/config.mk >> @@ -24,4 +24,10 @@ >> # P4080DS board >> # >> >> +ifeq ($(CONFIG_RAMBOOT_PBL), y) >> +RESET_VECTOR_ADDRESS = 0xfffffffc >> +endif >> + >> +ifndef RESET_VECTOR_ADDRESS >> RESET_VECTOR_ADDRESS = 0xeffffffc >> +endif > > Do we really need this? Can this not be moved into the board config > file, so we gan delete the config.mk ? I'll post a cleanup patch that should handle this bit for us on all 85xx boards that need it. - k
>> --- >> Use CONFIG_RAMBOOT_PBL instead of CONFIG_PBL_BOOT_INDIRECT according to >Kumar's comment. > >CONFIG_RAMBOOT_PBL needs to be documented in the README! [Xie Shaohui] OK, I'll submit a patch of README. > > >> /* TLB 1 */ >> /* *I*** - Covers boot page */ >> +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) >> + /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the >> + * SRAM is at 0xfff00000, it covered the 0xfffff000. >> + * */ > >Incorrect multiline comment style. Please fix globally. [Xie Shaohui] OK. > >> --- a/include/configs/corenet_ds.h >> +++ b/include/configs/corenet_ds.h >> @@ -28,6 +28,10 @@ >> >> #include "../board/freescale/common/ics307_clk.h" >> >> +#ifdef CONFIG_RAMBOOT_PBL >> +#define CONFIG_RAMBOOT_TEXT_BASE 0xfff80000 >> +#endif > >Why is this needed? You already set SYS_TEXT_BASE to that value. [Xie Shaohui] You are right; this is not needed after boards.cfg is used. > >> @@ -62,11 +66,17 @@ >> #ifdef CONFIG_SYS_NO_FLASH >> #define CONFIG_ENV_IS_NOWHERE >> #else >> -#define CONFIG_ENV_IS_IN_FLASH > >Why remove the CONFIG_ENV_IS_IN_FLASH here, but leave the >CONFIG_ENV_IS_NOWHERE above? > >> #define CONFIG_FLASH_CFI_DRIVER >> #define CONFIG_SYS_FLASH_CFI >> #endif >> >> +#if defined(CONFIG_RAMBOOT_PBL) >> + #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ >> +#else >> + #define CONFIG_ENV_IS_IN_FLASH >> + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - >CONFIG_ENV_SECT_SIZE) >> +#endif > >See previous comment. This should be cleaned up. For example, move this >block up, and set CONFIG_SYS_NO_FLASH instead. [Xie Shaohui] OK, I'll clean up these codes. > >> +#define CONFIG_SYS_L3_SIZE (1024 << 10) >> +#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + >> +CONFIG_SYS_L3_SIZE) >> + >> + >> +/* > >Drop one of the blank lines, please. [Xie Shaohui] OK. Thanks. Best Regards, Shaohui Xie
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 4b8faa5..a58cd1a 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -139,6 +139,22 @@ static void enable_cpc(void) for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { u32 cpccfg0 = in_be32(&cpc->cpccfg0); size += CPC_CFG0_SZ_K(cpccfg0); +#ifdef CONFIG_RAMBOOT_PBL + if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { + /* find and disable LAW of SRAM */ + struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); + + if (law.index == -1) { + printf("\nFatal error happened\n"); + return; + } + disable_law(law.index); + + clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); + out_be32(&cpc->cpccsr0, 0); + out_be32(&cpc->cpcsrcr0, 0); + } +#endif out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); /* Read back to sync write */ @@ -155,6 +171,9 @@ void invalidate_cpc(void) cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + /* skip CPC when it used as all SRAM */ + if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) + continue; /* Flash invalidate the CPC and clear all the locks */ out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) diff --git a/board/freescale/corenet_ds/config.mk b/board/freescale/corenet_ds/config.mk index 15bbf20..918775d 100644 --- a/board/freescale/corenet_ds/config.mk +++ b/board/freescale/corenet_ds/config.mk @@ -24,4 +24,10 @@ # P4080DS board # +ifeq ($(CONFIG_RAMBOOT_PBL), y) +RESET_VECTOR_ADDRESS = 0xfffffffc +endif + +ifndef RESET_VECTOR_ADDRESS RESET_VECTOR_ADDRESS = 0xeffffffc +endif diff --git a/board/freescale/corenet_ds/tlb.c b/board/freescale/corenet_ds/tlb.c index 1ae0416..08f91a7 100644 --- a/board/freescale/corenet_ds/tlb.c +++ b/board/freescale/corenet_ds/tlb.c @@ -51,9 +51,18 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff00000, it covered the 0xfffff000. + * */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), +#endif /* *I*G* - CCSRBAR */ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, diff --git a/boards.cfg b/boards.cfg index 94b8745..2052efc 100644 --- a/boards.cfg +++ b/boards.cfg @@ -502,6 +502,7 @@ P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freesca P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,SDCARD P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,SPIFLASH P4080DS powerpc mpc85xx corenet_ds freescale +P4080DS_RAMBOOT_PBL powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF80000 stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 454a30a..663dff2 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -28,6 +28,10 @@ #include "../board/freescale/common/ics307_clk.h" +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE 0xfff80000 +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE #define CONFIG_E500 /* BOOKE e500 family */ @@ -62,11 +66,17 @@ #ifdef CONFIG_SYS_NO_FLASH #define CONFIG_ENV_IS_NOWHERE #else -#define CONFIG_ENV_IS_IN_FLASH #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #endif +#if defined(CONFIG_RAMBOOT_PBL) + #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ +#else + #define CONFIG_ENV_IS_IN_FLASH + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#endif + #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ /* @@ -96,6 +106,19 @@ #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) +#else +#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR +#endif +#define CONFIG_SYS_L3_SIZE (1024 << 10) +#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) + + +/* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ @@ -188,6 +211,10 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} @@ -459,7 +486,6 @@ /* * Environment */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */