From patchwork Tue Jan 11 08:10:36 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kumar Gala X-Patchwork-Id: 78295 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id A54EAB6F1E for ; Tue, 11 Jan 2011 19:12:15 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C606028227; Tue, 11 Jan 2011 09:11:36 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id UPJe5kOwDZ9j; Tue, 11 Jan 2011 09:11:36 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6D005281E9; Tue, 11 Jan 2011 09:11:06 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 95B5F2810E for ; Tue, 11 Jan 2011 09:11:04 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ioen7G3XnCvZ for ; Tue, 11 Jan 2011 09:11:02 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) by theia.denx.de (Postfix) with ESMTPS id EC56B280EF for ; Tue, 11 Jan 2011 09:10:48 +0100 (CET) Received: from localhost (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id p0B8Ag0a012291; Tue, 11 Jan 2011 02:10:42 -0600 From: Kumar Gala To: u-boot@lists.denx.de Date: Tue, 11 Jan 2011 02:10:36 -0600 Message-Id: <1294733436-10264-8-git-send-email-galak@kernel.crashing.org> X-Mailer: git-send-email 1.6.0.6 In-Reply-To: <1294733436-10264-7-git-send-email-galak@kernel.crashing.org> References: <1294607813-27723-1-git-send-email-galak@kernel.crashing.org> <1294733436-10264-1-git-send-email-galak@kernel.crashing.org> <1294733436-10264-2-git-send-email-galak@kernel.crashing.org> <1294733436-10264-3-git-send-email-galak@kernel.crashing.org> <1294733436-10264-4-git-send-email-galak@kernel.crashing.org> <1294733436-10264-5-git-send-email-galak@kernel.crashing.org> <1294733436-10264-6-git-send-email-galak@kernel.crashing.org> <1294733436-10264-7-git-send-email-galak@kernel.crashing.org> Cc: Li Yang Subject: [U-Boot] [PATCH v3 8/8] powerpc/85xx: Add SRIO support to P2020DS X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Li Yang The P2020 has 2 SRIO ports and they are useable on the P2020 DS board. Enable them using the common SRIO init code. Signed-off-by: Li Yang Signed-off-by: Kumar Gala --- * Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO include/configs/P2020DS.h | 24 +++++++++++++++++++++++- 1 files changed, 23 insertions(+), 1 deletions(-) diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 24f2498..c2636af 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2007-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -45,6 +45,10 @@ #define CONFIG_SYS_TEXT_BASE 0xeff80000 #endif +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ @@ -472,6 +476,24 @@ #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET #endif +/* SRIO1 uses the same window as PCIE2 mem window */ +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ + +/* SRIO2 uses the same window as PCIE1 mem window */ +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xc0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc40000000ull +#else +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc0000000 +#endif +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x20000000 /* 512M */ + #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */