Message ID | 1294608004-28304-2-git-send-email-galak@kernel.crashing.org |
---|---|
State | Accepted |
Commit | 3b4456ec391877a950dd5e98ee20df6560f0e1af |
Delegated to: | Kumar Gala |
Headers | show |
On Jan 9, 2011, at 3:20 PM, Kumar Gala wrote: > From: Roy Zang <tie-fei.zang@freescale.com> > > The default value of the SRS, VS18 and VS30 and ADMAS fields in the host > controller capabilities register (HOSTCAPBLT) are incorrect. The default > of these bits should be zero instead of one. > > Clear these bits out when we read HOSTCAPBLT. > > Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> > Signed-off-by: Kumar Gala <galak@kernel.crashing.org> > --- > arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ > drivers/mmc/fsl_esdhc.c | 5 +++++ > include/configs/P4080DS.h | 1 + > 3 files changed, 9 insertions(+), 0 deletions(-) applied - k
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 0c4820c..d5c34c8 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -53,6 +53,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111) puts("Work-around for Erratum ESDHC111 enabled\n"); #endif +#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135) + puts("Work-around for Erratum ESDHC135 enabled\n"); +#endif return 0; } diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index fe94164..d01c926 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -472,6 +472,11 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) voltage_caps = 0; caps = regs->hostcapblt; + +#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 + caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | + ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); +#endif if (caps & ESDHC_HOSTCAPBLT_VS18) voltage_caps |= MMC_VDD_165_195; if (caps & ESDHC_HOSTCAPBLT_VS30) diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 705b226..a15dd76 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -36,6 +36,7 @@ #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 #define CONFIG_SYS_P4080_ERRATUM_CPU22 #define CONFIG_SYS_P4080_ERRATUM_SERDES8