diff --git a/board/ti/beagle/beagle_nand_spl.c b/board/ti/beagle/beagle_nand_spl.c
new file mode 100644
index 0000000..4b4ebde
--- /dev/null
+++ b/board/ti/beagle/beagle_nand_spl.c
@@ -0,0 +1,250 @@
+/*
+ * (C) Copyright 2010
+ * Linaro <www.linaro.org>
+ * John Rigby <john.rigby@linaro.org>
+ *
+ * Adapted from x-loader omap3530beagle.c:
+ *   (C) Copyright 2006
+ *   Texas Instruments, <www.ti.com>
+ *   Jian Zhang <jzhang@ti.com>
+ *   Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include "beagle.h"
+
+void board_init_f(unsigned long bootflag)
+{
+	nand_boot();
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_BEAGLE();
+}
+
+/*
+ * beagle_identify
+ * Description: Detect if we are running on a Beagle revision Ax/Bx,
+ *		C1/2/3, C4 or D. This can be done by reading
+ *		the level of GPIO173, GPIO172 and GPIO171. This should
+ *		result in
+ *		GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
+ *		GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
+ *		GPIO173, GPIO172, GPIO171: 1 0 1 => C4
+ *		GPIO173, GPIO172, GPIO171: 0 0 0 => XM
+ *
+ */
+int beagle_revision(void)
+{
+	int rev;
+
+	omap_request_gpio(171);
+	omap_request_gpio(172);
+	omap_request_gpio(173);
+	omap_set_gpio_direction(171, 1);
+	omap_set_gpio_direction(172, 1);
+	omap_set_gpio_direction(173, 1);
+
+	rev = omap_get_gpio_datain(173) << 2 |
+		omap_get_gpio_datain(172) << 1 |
+		omap_get_gpio_datain(171);
+	omap_free_gpio(171);
+	omap_free_gpio(172);
+	omap_free_gpio(173);
+
+	return rev;
+}
+
+static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
+	M_NAND_GPMC_CONFIG1,
+	M_NAND_GPMC_CONFIG2,
+	M_NAND_GPMC_CONFIG3,
+	M_NAND_GPMC_CONFIG4,
+	M_NAND_GPMC_CONFIG5,
+	M_NAND_GPMC_CONFIG6, 0
+};
+
+static void gpmc_nand_init(void)
+{
+	gpmc_cfg = (struct gpmc *)GPMC_BASE;
+	const u32 *gpmc_config = NULL;
+	u32 base = 0;
+	u32 size = 0;
+	u32 config = 0;
+
+	/* global settings */
+	writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
+	writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
+
+	config = readl(&gpmc_cfg->config);
+	config &= (~0xf00);
+	writel(config, &gpmc_cfg->config);
+
+	/*
+	 * Disable the GPMC0 config set by ROM code
+	 * It conflicts with our MPDB (both at 0x08000000)
+	 */
+	writel(0, &gpmc_cfg->cs[0].config7);
+	sdelay(1000);
+
+	gpmc_config = gpmc_m_nand;
+
+	base = PISMO1_NAND_BASE;
+	size = PISMO1_NAND_SIZE;
+	enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
+}
+
+#define MICRON_DDR	0
+#define NUMONYX_MCP	1
+int identify_xm_ddr(void)
+{
+	int	mfr, id;
+
+	gpmc_nand_init();
+
+	sdelay(2000);
+
+	nand_boot_readid(&mfr, &id);
+	if (mfr == 0)
+		return MICRON_DDR;
+	if ((mfr == 0x20) && (id == 0xba))
+		return NUMONYX_MCP;
+	return MICRON_DDR;
+}
+
+void mem_init(void)
+{
+	struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
+	struct sdrc_actim *sdrc_actim_base0 =
+		(struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
+	struct sdrc_actim *sdrc_actim_base1 =
+		(struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
+
+	/* reset sdrc controller */
+	writel(SOFTRESET, &sdrc_base->sysconfig);
+	wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
+		      12000000);
+	writel(0, &sdrc_base->sysconfig);
+
+	/* setup sdrc to ball mux */
+	writel(SDRC_SHARING, &sdrc_base->sharing);
+
+	switch(beagle_revision()) {
+	case REVISION_C4:
+		if (identify_xm_ddr() == NUMONYX_MCP) {
+			writel(0x4, &sdrc_base->cs_cfg); /* 512MB/bank */
+			writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, &sdrc_base->cs[0].mcfg);
+			writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, &sdrc_base->cs[1].mcfg);
+			writel(NUMONYX_V_ACTIMA_165, &sdrc_actim_base0->ctrla);
+			writel(NUMONYX_V_ACTIMB_165, &sdrc_actim_base0->ctrlb);
+			writel(NUMONYX_V_ACTIMA_165, &sdrc_actim_base1->ctrla);
+			writel(NUMONYX_V_ACTIMB_165, &sdrc_actim_base1->ctrlb);
+			writel(SDP_3430_SDRC_RFR_CTRL_165MHz, &sdrc_base->cs[0].rfr_ctrl);
+			writel(SDP_3430_SDRC_RFR_CTRL_165MHz, &sdrc_base->cs[1].rfr_ctrl);
+		} else {
+			writel(0x1, &sdrc_base->cs_cfg); /* 128MB/bank */
+			writel(SDP_SDRC_MDCFG_0_DDR, &sdrc_base->cs[0].mcfg);
+			writel(SDP_SDRC_MDCFG_0_DDR, &sdrc_base->cs[1].mcfg);
+			writel(MICRON_V_ACTIMA_165, &sdrc_actim_base0->ctrla);
+			writel(MICRON_V_ACTIMB_165, &sdrc_actim_base0->ctrlb);
+			writel(MICRON_V_ACTIMA_165, &sdrc_actim_base1->ctrla);
+			writel(MICRON_V_ACTIMB_165, &sdrc_actim_base1->ctrlb);
+			writel(SDP_3430_SDRC_RFR_CTRL_165MHz, &sdrc_base->cs[0].rfr_ctrl);
+			writel(SDP_3430_SDRC_RFR_CTRL_165MHz, &sdrc_base->cs[1].rfr_ctrl);
+		}
+		break;
+	case REVISION_XM:
+		if (identify_xm_ddr() == MICRON_DDR) {
+			writel(0x2, &sdrc_base->cs_cfg); /* 256MB/bank */
+			writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, &sdrc_base->cs[0].mcfg);
+			writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, &sdrc_base->cs[1].mcfg);
+			writel(MICRON_V_ACTIMA_200, &sdrc_actim_base0->ctrla);
+			writel(MICRON_V_ACTIMB_200, &sdrc_actim_base0->ctrlb);
+			writel(MICRON_V_ACTIMA_200, &sdrc_actim_base1->ctrla);
+			writel(MICRON_V_ACTIMB_200, &sdrc_actim_base1->ctrlb);
+			writel(SDP_3430_SDRC_RFR_CTRL_200MHz, &sdrc_base->cs[0].rfr_ctrl);
+			writel(SDP_3430_SDRC_RFR_CTRL_200MHz, &sdrc_base->cs[1].rfr_ctrl);
+		} else {
+			writel(0x4, &sdrc_base->cs_cfg); /* 512MB/bank */
+			writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, &sdrc_base->cs[0].mcfg);
+			writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, &sdrc_base->cs[1].mcfg);
+			writel(NUMONYX_V_ACTIMA_165, &sdrc_actim_base0->ctrla);
+			writel(NUMONYX_V_ACTIMB_165, &sdrc_actim_base0->ctrlb);
+			writel(NUMONYX_V_ACTIMA_165, &sdrc_actim_base1->ctrla);
+			writel(NUMONYX_V_ACTIMB_165, &sdrc_actim_base1->ctrlb);
+			writel(SDP_3430_SDRC_RFR_CTRL_165MHz, &sdrc_base->cs[0].rfr_ctrl);
+			writel(SDP_3430_SDRC_RFR_CTRL_165MHz, &sdrc_base->cs[1].rfr_ctrl);
+		}
+		break;
+	default:
+		writel(0x1, &sdrc_base->cs_cfg); /* 128MB/bank */
+		writel(SDP_SDRC_MDCFG_0_DDR, &sdrc_base->cs[0].mcfg);
+		writel(SDP_SDRC_MDCFG_0_DDR, &sdrc_base->cs[1].mcfg);
+		writel(MICRON_V_ACTIMA_165, &sdrc_actim_base0->ctrla);
+		writel(MICRON_V_ACTIMB_165, &sdrc_actim_base0->ctrlb);
+		writel(MICRON_V_ACTIMA_165, &sdrc_actim_base1->ctrla);
+		writel(MICRON_V_ACTIMB_165, &sdrc_actim_base1->ctrlb);
+		writel(SDP_3430_SDRC_RFR_CTRL_165MHz, &sdrc_base->cs[0].rfr_ctrl);
+		writel(SDP_3430_SDRC_RFR_CTRL_165MHz, &sdrc_base->cs[1].rfr_ctrl);
+	}
+
+	writel(SDP_SDRC_POWER_POP, &sdrc_base->power);
+
+	/* init sequence for mDDR/mSDR using manual commands (DDR is different) */
+	writel(CMD_NOP, &sdrc_base->cs[0].manual);
+	writel(CMD_NOP, &sdrc_base->cs[1].manual);
+
+	sdelay(5000);
+
+	writel(CMD_PRECHARGE, &sdrc_base->cs[0].manual);
+	writel(CMD_PRECHARGE, &sdrc_base->cs[1].manual);
+
+	writel(CMD_AUTOREFRESH, &sdrc_base->cs[0].manual);
+	writel(CMD_AUTOREFRESH, &sdrc_base->cs[1].manual);
+
+	writel(CMD_AUTOREFRESH, &sdrc_base->cs[0].manual);
+	writel(CMD_AUTOREFRESH, &sdrc_base->cs[1].manual);
+
+	/* set mr0 */
+	writel(SDP_SDRC_MR_0_DDR, &sdrc_base->cs[0].mr);
+	writel(SDP_SDRC_MR_0_DDR, &sdrc_base->cs[1].mr);
+
+	/* set up dll */
+	writel(SDP_SDRC_DLLAB_CTRL, &sdrc_base->dlla_ctrl);
+	sdelay(0x2000);	/* give time to lock */
+
+	return;
+}
diff --git a/boards.cfg b/boards.cfg
index 94b8745..5f2b613 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -115,6 +115,7 @@ am3517_evm                   arm         armv7       am3517evm           logicpd
 omap3_zoom1                  arm         armv7       zoom1               logicpd        omap3
 omap3_zoom2                  arm         armv7       zoom2               logicpd        omap3
 omap3_beagle                 arm         armv7       beagle              ti             omap3
+omap3_beagle_nand            arm         armv7       beagle              ti             omap3       omap3_beagle:NAND_U_BOOT           
 omap3_evm                    arm         armv7       evm                 ti             omap3
 omap3_sdp3430                arm         armv7       sdp3430             ti             omap3
 devkit8000                   arm         armv7       devkit8000          timll          omap3
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index f73d133..fd8389d 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -41,14 +41,23 @@
 
 #define CONFIG_SDRC	/* The chip has SDRC controller */
 
+/* The 343x-SDRC incoming address convention is row bank column */
+#define SDRC_R_B_C		1
+
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>
 
+#define CONFIG_SYS_NAND_SPL_TEXT_BASE 0x40200800
+#define CONFIG_SYS_NAND_SPL_PAD_TO 0x40204800
+#define CONFIG_SYS_TEXT_BASE 0x80008000
+
+#ifndef CONFIG_NAND_SPL
 /*
  * Display CPU and Board information
  */
 #define CONFIG_DISPLAY_CPUINFO		1
 #define CONFIG_DISPLAY_BOARDINFO	1
+#endif
 
 /* Clock Defines */
 #define V_OSCK			26000000	/* Clock output from T2 */
@@ -79,6 +88,10 @@
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
 						/* initial data */
 
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
 /*
  * Hardware drivers
  */
@@ -92,6 +105,9 @@
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
 #define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
 
 /*
  * select serial console configuration
@@ -177,6 +193,29 @@
 
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
 							/* devices */
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_BUSWIDTH_16     1
+#define CONFIG_SYS_NAND_BOOT_READID	16
+#define CONFIG_SYS_NAND_PAGE_SIZE	(2 << 10)
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE	1
+#define CONFIG_SYS_NAND_ECCPOS		{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12}
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
+#define CONFIG_SYS_NAND_ECCSIZE         512
+#define CONFIG_SYS_NAND_ECCBYTES        3
+#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE /	 \
+					 CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES *	\
+					CONFIG_SYS_NAND_ECCSTEPS)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS     0x0080000 /* Leaving first 4 blocks for SPL */
+#define CONFIG_SYS_NAND_U_BOOT_SIZE     (0x0160000-CONFIG_SYS_NAND_U_BOOT_OFFS)
+/* offset from beginning of sdram of a safe scratch */
+#define CONFIG_SYS_NAND_BOOT_ECC_SCRATCH (1 << 20)
+#endif
 #define CONFIG_JFFS2_NAND
 /* nand device jffs2 lives on */
 #define CONFIG_JFFS2_DEV		"nand0"
diff --git a/nand_spl/board/ti/beagle/Makefile b/nand_spl/board/ti/beagle/Makefile
new file mode 100644
index 0000000..6bc0ac7
--- /dev/null
+++ b/nand_spl/board/ti/beagle/Makefile
@@ -0,0 +1,138 @@
+#
+# (C) Copyright 2006-2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_NAND_SPL	= y
+
+include $(TOPDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS	= -Bstatic -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_NAND_SPL_TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS	+= -DCONFIG_PRELOADER -DCONFIG_NAND_SPL
+CFLAGS	+= -DCONFIG_PRELOADER -DCONFIG_NAND_SPL
+
+SOBJS	= start.o lowlevel_init.o
+COBJS	= board.o clock.o gpio.o mem.o omap_gpmc.o ns16550.o \
+	beagle_nand_spl.o nand_boot.o syslib.o sys_info.o
+
+SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS	:= $(SOBJS) $(COBJS)
+LNDIR	:= $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj	:= $(OBJTREE)/nand_spl/
+
+ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin \
+	$(nandobj)u-boot-spl-16k.bin
+
+all:	$(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_NAND_SPL_PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl:	$(OBJS) $(nandobj)u-boot.lds
+	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
+		-Map $(nandobj)u-boot-spl.map \
+		-o $(nandobj)u-boot-spl
+
+$(nandobj)u-boot.lds: $(LDSCRIPT)
+	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+
+# create symbolic links for common files
+
+# from drivers/mtd/nand directory
+$(obj)omap_gpmc.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/drivers/mtd/nand/omap_gpmc.c $@
+
+# from nand_spl directory
+$(obj)nand_boot.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/nand_spl/nand_boot.c $@
+
+# from drivers/serial directory
+$(obj)ns16550.c:
+	@rm -f $@
+	@ln -sf $(TOPDIR)/drivers/serial/ns16550.c $@
+
+# from cpu directory
+$(obj)start.S:
+	@rm -f $@
+	ln -s $(TOPDIR)/arch/arm/cpu/armv7/start.S $@
+
+$(obj)board.c:
+	@rm -f $@
+	ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap3/board.c $@
+
+$(obj)clock.c:
+	@rm -f $@
+	ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap3/clock.c $@
+
+$(obj)gpio.c:
+	@rm -f $@
+	ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap3/gpio.c $@
+
+$(obj)lowlevel_init.S:
+	@rm -f $@
+	ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap3/lowlevel_init.S $@
+
+$(obj)mem.c:
+	@rm -f $@
+	ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap3/mem.c $@
+
+$(obj)syslib.c:
+	@rm -f $@
+	ln -s $(TOPDIR)/arch/arm/cpu/armv7/syslib.c $@
+
+$(obj)sys_info.c:
+	@rm -f $@
+	ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap3/sys_info.c $@
+
+# from board directory
+$(obj)beagle.h:
+	@rm -f $(obj)beagle.h
+	ln -s $(TOPDIR)/board/ti/beagle/beagle.h $@
+
+$(obj)beagle_nand_spl.c: $(obj)beagle.h
+	@rm -f $@
+	ln -s $(TOPDIR)/board/ti/beagle/beagle_nand_spl.c $@
+
+#########################################################################
+
+$(obj)%.o:	$(obj)%.S
+	$(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o:	$(obj)%.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/nand_spl/board/ti/beagle/u-boot.lds b/nand_spl/board/ti/beagle/u-boot.lds
new file mode 100644
index 0000000..bff721b
--- /dev/null
+++ b/nand_spl/board/ti/beagle/u-boot.lds
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  start.o	(.text)
+	  nand_boot.o	(.text)
+
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data)
+	__datarel_start = .;
+		*(.data.rel)
+	__datarelrolocal_start = .;
+		*(.data.rel.ro.local)
+	__datarellocal_start = .;
+		*(.data.rel.local)
+	__datarelro_start = .;
+		*(.data.rel.ro)
+	}
+
+	. = ALIGN(4);
+	__rel_dyn_start = .;
+	__rel_dyn_end = .;
+	__dynsym_start = .;
+
+	__got_start = .;
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__got_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
