From patchwork Wed Dec 1 00:36:25 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timur Tabi X-Patchwork-Id: 73689 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 97EEBB70DF for ; Wed, 1 Dec 2010 11:36:38 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4956D280B7; Wed, 1 Dec 2010 01:36:36 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 73yhd-7WHS-Z; Wed, 1 Dec 2010 01:36:36 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4B92028096; Wed, 1 Dec 2010 01:36:35 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1F8C728096 for ; Wed, 1 Dec 2010 01:36:34 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id H3urj7QY+oCa for ; Wed, 1 Dec 2010 01:36:32 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from AM1EHSOBE004.bigfish.com (am1ehsobe004.messaging.microsoft.com [213.199.154.207]) by theia.denx.de (Postfix) with ESMTPS id 110102808A for ; Wed, 1 Dec 2010 01:36:30 +0100 (CET) Received: from mail51-am1-R.bigfish.com (10.3.201.251) by AM1EHSOBE004.bigfish.com (10.3.204.24) with Microsoft SMTP Server id 14.1.225.8; Wed, 1 Dec 2010 00:36:29 +0000 Received: from mail51-am1 (localhost.localdomain [127.0.0.1]) by mail51-am1-R.bigfish.com (Postfix) with ESMTP id BC76B640468 for ; Wed, 1 Dec 2010 00:36:29 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h691h668h67dh61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: KIP:(null); UIP:(null); IPVD:NLI; H:de01egw02.freescale.net; RD:de01egw02.freescale.net; EFVD:NLI Received: from mail51-am1 (localhost.localdomain [127.0.0.1]) by mail51-am1 (MessageSwitch) id 1291163789383569_535; Wed, 1 Dec 2010 00:36:29 +0000 (UTC) Received: from AM1EHSMHS007.bigfish.com (unknown [10.3.201.243]) by mail51-am1.bigfish.com (Postfix) with ESMTP id 4E9461C5804E for ; Wed, 1 Dec 2010 00:36:29 +0000 (UTC) Received: from de01egw02.freescale.net (192.88.165.103) by AM1EHSMHS007.bigfish.com (10.3.207.107) with Microsoft SMTP Server (TLS) id 14.1.225.8; Wed, 1 Dec 2010 00:36:28 +0000 Received: from az33smr01.freescale.net (az33smr01.freescale.net [10.64.34.199]) by de01egw02.freescale.net (8.14.3/8.14.3) with ESMTP id oB10aQQr003568 for ; Tue, 30 Nov 2010 17:36:27 -0700 (MST) Received: from efes.am.freescale.net (efes.am.freescale.net [10.82.123.3]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id oB10aPKd015878; Tue, 30 Nov 2010 18:36:26 -0600 (CST) From: Timur Tabi To: , Date: Tue, 30 Nov 2010 18:36:25 -0600 Message-ID: <1291163785-24443-1-git-send-email-timur@freescale.com> X-Mailer: git-send-email 1.7.2.3 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Subject: [U-Boot] [PATCH] p1022ds: fix switching of DIU/LBC signals X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de On the P1022, the pins which drive the video display (DIU) are muxed with the local bus controller (LBC), so if the DIU is active, the pins need to be temporarily muxed to LBC whenever accessing NOR flash. The code which handled this transition is checking and changing the wrong bits in PMUXCR. Also add a follow-up read after a write to NOR flash if we're going to mux back to DIU after the write, as described in the P1022 RM. Signed-off-by: Timur Tabi --- I have no idea how this ever worked before. It's a complete mystery to me. board/freescale/p1022ds/diu.c | 45 +++++++++++++++++++++++++++++++++------- 1 files changed, 37 insertions(+), 8 deletions(-) diff --git a/board/freescale/p1022ds/diu.c b/board/freescale/p1022ds/diu.c index 12b40a0..2259384 100644 --- a/board/freescale/p1022ds/diu.c +++ b/board/freescale/p1022ds/diu.c @@ -32,6 +32,7 @@ #define PMUXCR_ELBCDIU_MASK 0xc0000000 #define PMUXCR_ELBCDIU_NOR16 0x80000000 +#define PMUXCR_ELBCDIU_DIU 0x40000000 /* * DIU Area Descriptor @@ -131,9 +132,8 @@ int platform_diu_init(unsigned int *xres, unsigned int *yres) px_brdcfg0 = in_8(lbc_lcs1_ba); out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU); - /* Setting PMUXCR to switch to DVI from ELBC */ - clrsetbits_be32(&gur->pmuxcr, - PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_NOR16); + /* Set PMUXCR to switch the muxed pins from the LBC to the DIU */ + clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU); pmuxcr = in_be32(&gur->pmuxcr); return fsl_diu_init(*xres, pixel_format, 0); @@ -161,7 +161,7 @@ static int set_mux_to_lbc(void) ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; /* Switch the muxes only if they're currently set to DIU mode */ - if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) == + if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) != PMUXCR_ELBCDIU_NOR16) { /* * In DIU mode, the PIXIS can only be accessed indirectly @@ -216,8 +216,16 @@ void flash_write8(u8 value, void *addr) int sw = set_mux_to_lbc(); __raw_writeb(value, addr); - if (sw) + + if (sw) { + /* + * To ensure the post-write is completed to eLBC, software must + * perform a dummy read from one valid address from eLBC space + * before changing the eLBC_DIU from NOR mode to DIU mode. + */ + __raw_readb(addr); set_mux_to_diu(); + } } void flash_write16(u16 value, void *addr) @@ -225,8 +233,15 @@ void flash_write16(u16 value, void *addr) int sw = set_mux_to_lbc(); __raw_writew(value, addr); - if (sw) + if (sw) { + /* + * To ensure the post-write is completed to eLBC, software must + * perform a dummy read from one valid address from eLBC space + * before changing the eLBC_DIU from NOR mode to DIU mode. + */ + __raw_readb(addr); set_mux_to_diu(); + } } void flash_write32(u32 value, void *addr) @@ -234,8 +249,15 @@ void flash_write32(u32 value, void *addr) int sw = set_mux_to_lbc(); __raw_writel(value, addr); - if (sw) + if (sw) { + /* + * To ensure the post-write is completed to eLBC, software must + * perform a dummy read from one valid address from eLBC space + * before changing the eLBC_DIU from NOR mode to DIU mode. + */ + __raw_readb(addr); set_mux_to_diu(); + } } void flash_write64(u64 value, void *addr) @@ -244,8 +266,15 @@ void flash_write64(u64 value, void *addr) /* There is no __raw_writeq(), so do the write manually */ *(volatile u64 *)addr = value; - if (sw) + if (sw) { + /* + * To ensure the post-write is completed to eLBC, software must + * perform a dummy read from one valid address from eLBC space + * before changing the eLBC_DIU from NOR mode to DIU mode. + */ + __raw_readb(addr); set_mux_to_diu(); + } } u8 flash_read8(void *addr)