From patchwork Mon Apr 19 07:56:59 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefano Babic X-Patchwork-Id: 71767 Return-Path: X-Original-To: wd@gemini.denx.de Delivered-To: wd@gemini.denx.de Received: from diddl.denx.de (diddl.denx.de [10.0.0.6]) by gemini.denx.de (Postfix) with ESMTP id B941DE22ADC for ; Mon, 19 Apr 2010 10:00:09 +0200 (CEST) Received: from diddl.denx.de (localhost.localdomain [127.0.0.1]) by diddl.denx.de (Postfix) with ESMTP id AD21AC912DD7 for ; Mon, 19 Apr 2010 10:00:09 +0200 (CEST) Received: from pop.mnet-online.de by diddl.denx.de with POP3 (fetchmail-6.3.9) for (single-drop); Mon, 19 Apr 2010 10:00:09 +0200 (CEST) Received: from murder (svr19.m-online.net [192.168.3.147]) by backend2 (Cyrus v2.2.12) with LMTPA; Mon, 19 Apr 2010 09:58:23 +0200 X-Sieve: CMU Sieve 2.2 Received: from mail.m-online.net (localhost [127.0.0.1]) by frontend3.pop.m-online.net (Cyrus v2.2.13) with LMTPA; Mon, 19 Apr 2010 09:58:23 +0200 Received: from scanner-2.m-online.net (unknown [192.168.8.166]) by mail.m-online.net (Postfix) with ESMTP id 59AB0200134; Mon, 19 Apr 2010 09:58:23 +0200 (CEST) Received: from mxin-3.m-online.net ([192.168.6.165]) by scanner-2.m-online.net (scanner-2.m-online.net [192.168.8.166]) (amavisd-new, port 10026) with ESMTP id 22196-01-2; Mon, 19 Apr 2010 09:58:21 +0200 (CEST) Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by mxin-3.m-online.net (Postfix) with ESMTP id EC3FD47A4E2; Mon, 19 Apr 2010 09:58:20 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DE0BE280A1; Mon, 19 Apr 2010 09:57:54 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id O5DiCphzfU7Q; Mon, 19 Apr 2010 09:57:54 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 227F7280A8; Mon, 19 Apr 2010 09:57:49 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0AF1B28080 for ; Mon, 19 Apr 2010 09:57:47 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id oCpNlw2kbc1V for ; Mon, 19 Apr 2010 09:57:45 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from smtpout24.attiva.biz (smtpout24.attiva.biz [85.37.16.25]) by theia.denx.de (Postfix) with ESMTP id 09CC6280A4 for ; Mon, 19 Apr 2010 09:57:35 +0200 (CEST) Received: from fbcmfe02b11.fbc.local ([192.168.30.92]) by smtpout24.attiva.biz with Microsoft SMTPSVC(6.0.3790.3959); Mon, 19 Apr 2010 09:57:35 +0200 Received: from superpapero.babic.homelinux.org ([81.74.56.14]) by fbcmfe02b11.fbc.local with Microsoft SMTPSVC(6.0.3790.3959); Mon, 19 Apr 2010 09:57:33 +0200 Received: from localhost.localdomain (unknown [192.168.2.236]) by superpapero.babic.homelinux.org (Postfix) with ESMTP id 7BD8816E0002; Mon, 19 Apr 2010 09:57:32 +0200 (CEST) From: Stefano Babic To: u-boot@lists.denx.de Date: Mon, 19 Apr 2010 09:56:59 +0200 Message-Id: <1271663820-7358-5-git-send-email-sbabic@denx.de> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1271663820-7358-4-git-send-email-sbabic@denx.de> References: <1268756287-2030-1-git-send-email-sbabic@denx.de> <1271663820-7358-1-git-send-email-sbabic@denx.de> <1271663820-7358-2-git-send-email-sbabic@denx.de> <1271663820-7358-3-git-send-email-sbabic@denx.de> <1271663820-7358-4-git-send-email-sbabic@denx.de> X-OriginalArrivalTime: 19 Apr 2010 07:57:33.0543 (UTC) FILETIME=[F7E2AF70:01CADF95] Subject: [U-Boot] [PATCH 5/6] MX: Added definition file for MC13892 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de X-Virus-Scanned: by amavisd-new at m-online.net The MC13892 is a Power Controller used with processors of the family MX.51. The file adds definitions to be used to setup the internal registers via SPI. Signed-off-by: Stefano Babic --- include/mc13892.h | 160 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 160 insertions(+), 0 deletions(-) create mode 100644 include/mc13892.h diff --git a/include/mc13892.h b/include/mc13892.h new file mode 100644 index 0000000..b291757 --- /dev/null +++ b/include/mc13892.h @@ -0,0 +1,160 @@ +/* + * (C) Copyright 2010 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef __MC13892_H__ +#define __MC13892_H__ + +/* REG_CHARGE */ + +#define VCHRG0 0 +#define VCHRG1 (1 << 1) +#define VCHRG2 (1 << 2) +#define ICHRG0 (1 << 3) +#define ICHRG1 (1 << 4) +#define ICHRG2 (1 << 5) +#define ICHRG3 (1 << 6) +#define ICHRGTR0 (1 << 7) +#define ICHRGTR1 (1 << 8) +#define ICHRGTR2 (1 << 9) +#define FETOVRD (1 << 10) +#define FETCTRL (1 << 11) +#define RVRSMODE (1 << 13) +#define OVCTRL0 (1 << 15) +#define OVCTRL1 (1 << 16) +#define UCHEN (1 << 17) +#define CHRGLEDEN (1 << 18) +#define CHRGRAWPDEN (1 << 19) +#define CHGRESTART (1 << 20) +#define CHGAUTOB (1 << 21) +#define CYCLB (1 << 22) +#define CHGAUTOVIB (1 << 23) + +/* REG_SETTING_0/1 */ +#define VO_1_20V 0 +#define VO_1_30V 1 +#define VO_1_50V 2 +#define VO_1_80V 3 +#define VO_1_10V 4 +#define VO_2_00V 5 +#define VO_2_77V 6 +#define VO_2_40V 7 + +#define VIOL 2 +#define VDIG 4 +#define VGEN 6 + +/* SWxMode for Normal/Standby Mode */ +#define SWMODE_OFF_OFF 0 +#define SWMODE_PWM_OFF 1 +#define SWMODE_PWMPS_OFF 2 +#define SWMODE_PFM_OFF 3 +#define SWMODE_AUTO_OFF 4 +#define SWMODE_PWM_PWM 5 +#define SWMODE_PWM_AUTO 6 +#define SWMODE_AUTO_AUTO 8 +#define SWMODE_PWM_PWMPS 9 +#define SWMODE_PWMS_PWMPS 10 +#define SWMODE_PWMS_AUTO 11 +#define SWMODE_AUTO_PFM 12 +#define SWMODE_PWM_PFM 13 +#define SWMODE_PWMS_PFM 14 +#define SWMODE_PFM_PFM 15 +#define SWMODE_MASK 0x0F + +#define SWMODE1_SHIFT 0 +#define SWMODE2_SHIFT 10 +#define SWMODE3_SHIFT 0 +#define SWMODE4_SHIFT 8 + +/* Fields in REG_SETTING_1 */ +#define VVIDEO_2_7 (0 << 2) +#define VVIDEO_2_775 (1 << 2) +#define VVIDEO_2_5 (2 << 2) +#define VVIDEO_2_6 (3 << 2) +#define VVIDEO_MASK (3 << 2) +#define VAUDIO_2_3 (0 << 4) +#define VAUDIO_2_5 (1 << 4) +#define VAUDIO_2_775 (2 << 4) +#define VAUDIO_3_0 (3 << 4) +#define VAUDIO_MASK (3 << 4) +#define VSD_1_8 (0 << 6) +#define VSD_2_0 (1 << 6) +#define VSD_2_6 (2 << 6) +#define VSD_2_7 (3 << 6) +#define VSD_2_8 (4 << 6) +#define VSD_2_9 (5 << 6) +#define VSD_3_0 (6 << 6) +#define VSD_3_15 (7 << 6) +#define VSD_MASK (7 << 6) +#define VGEN1_1_2 0 +#define VGEN1_1_5 1 +#define VGEN1_2_775 2 +#define VGEN1_3_15 3 +#define VGEN1_MASK 3 +#define VGEN2_1_2 (0 << 6) +#define VGEN2_1_5 (1 << 6) +#define VGEN2_1_6 (2 << 6) +#define VGEN2_1_8 (3 << 6) +#define VGEN2_2_7 (4 << 6) +#define VGEN2_2_8 (5 << 6) +#define VGEN2_3_0 (6 << 6) +#define VGEN2_3_15 (7 << 6) +#define VGEN2_MASK (7 << 6) + +/* Fields in REG_SETTING_1 */ +#define VGEN3_1_8 (0 << 14) +#define VGEN3_2_9 (1 << 14) +#define VGEN3_MASK (1 << 14) +#define VDIG_1_05 (0 << 4) +#define VDIG_1_25 (1 << 4) +#define VDIG_1_65 (2 << 4) +#define VDIG_1_8 (3 << 4) +#define VDIG_MASK (3 << 4) +#define VCAM_2_5 (0 << 16) +#define VCAM_2_6 (1 << 16) +#define VCAM_2_75 (2 << 16) +#define VCAM_3_0 (3 << 16) +#define VCAM_MASK (3 << 16) + +/* Reg Mode 1 */ +#define VGEN3EN (1 << 0) +#define VGEN3STBY (1 << 1) +#define VGEN3MODE (1 << 2) +#define VGEN3CONFIG (1 << 3) +#define VCAMEN (1 << 6) +#define VCAMSTBY (1 << 7) +#define VCAMMODE (1 << 8) +#define VCAMCONFIG (1 << 9) +#define VVIDEOEN (1 << 12) +#define VIDEOSTBY (1 << 13) +#define VVIDEOMODE (1 << 14) +#define VAUDIOEN (1 << 15) +#define VAUDIOSTBY (1 << 16) +#define VSDEN (1 << 18) +#define VSDSTBY (1 << 19) +#define VSDMODE (1 << 20) + +#endif