From patchwork Fri Sep 9 11:59:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?V2VpamllIEdhbyAo6auY5oOf5p2wKQ==?= X-Patchwork-Id: 1675990 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256 header.s=dk header.b=JsXsGjvQ; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4MPF0n63sfz1yj1 for ; Fri, 9 Sep 2022 21:59:53 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5852C84B75; Fri, 9 Sep 2022 13:59:30 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.b="JsXsGjvQ"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 1941A84B73; Fri, 9 Sep 2022 13:59:28 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,RDNS_NONE, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.2 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C427084B5F for ; Fri, 9 Sep 2022 13:59:22 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=weijie.gao@mediatek.com X-UUID: e9074b26b8ed45c8b414d478b0397934-20220909 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=jL7a397mw3NEcDHIsDMzaxJkil9JZeOgeQPU63MUZfw=; b=JsXsGjvQfMnWZYFsGyGJuLmrPLrIGO0G34J9vFqJHhWk/T6mdZaMKGsJKVmiV+R5aANFyklnafUCGBxy4rjv+98IOK4WgPMFWW4u2AP4YgvuMeYi6nXMh4XN/NgrhnblPJ5ZRQ2EErLtqq1XBhFPLR5hH6Hf74latDtq45nO3hM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.10, REQID:2af32577-f432-46ec-8308-9155df013a81, OB:0, L OB:0,IP:0,URL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Releas e_Ham,ACTION:release,TS:-25 X-CID-META: VersionHash:84eae18, CLOUDID:9eed205d-5ed4-4e28-8b00-66ed9f042fbd, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: e9074b26b8ed45c8b414d478b0397934-20220909 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 979646017; Fri, 09 Sep 2022 19:59:15 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 9 Sep 2022 19:59:13 +0800 Received: from mcddlt001.gcn.mediatek.inc (10.19.240.15) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 9 Sep 2022 19:59:12 +0800 From: Weijie Gao To: CC: GSS_MTK_Uboot_upstream , Daniel Golle , Weijie Gao Subject: [PATCH v3 02/32] arm: mediatek: add support for MediaTek MT7981 SoC Date: Fri, 9 Sep 2022 19:59:11 +0800 Message-ID: <0a146eb2c9b60f38cbe2b955148408a5b64903a8.1662722729.git.weijie.gao@mediatek.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: References: MIME-Version: 1.0 X-MTK: N X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean This patch adds basic support for MediaTek MT7981 SoC. This include the file that will initialize the SoC after boot and its device tree. Reviewed-by: Simon Glass Signed-off-by: Weijie Gao --- v3 changes: Add syscon to hwver node Add reference of hwver to cpu nodes v2 changes: Sort include lines Add reference link for armv8_el2_to_aarch32 in lowlevel_init.S Remove print_cpuinfo and use cpu driver instead --- arch/arm/dts/mt7981.dtsi | 295 ++++++++++++++++++ arch/arm/mach-mediatek/Kconfig | 13 +- arch/arm/mach-mediatek/Makefile | 1 + arch/arm/mach-mediatek/mt7981/Makefile | 4 + arch/arm/mach-mediatek/mt7981/init.c | 45 +++ arch/arm/mach-mediatek/mt7981/lowlevel_init.S | 32 ++ 6 files changed, 389 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/mt7981.dtsi create mode 100644 arch/arm/mach-mediatek/mt7981/Makefile create mode 100644 arch/arm/mach-mediatek/mt7981/init.c create mode 100644 arch/arm/mach-mediatek/mt7981/lowlevel_init.S diff --git a/arch/arm/dts/mt7981.dtsi b/arch/arm/dts/mt7981.dtsi new file mode 100644 index 0000000000..3089371805 --- /dev/null +++ b/arch/arm/dts/mt7981.dtsi @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Sam Shih + */ + +#include +#include +#include +#include +#include + +/ { + compatible = "mediatek,mt7981"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + mediatek,hwver = <&hwver>; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + mediatek,hwver = <&hwver>; + }; + }; + + gpt_clk: gpt_dummy20m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + u-boot,dm-pre-reloc; + }; + + hwver: hwver { + compatible = "mediatek,hwver", "syscon"; + reg = <0x8000000 0x1000>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + clock-frequency = <13000000>; + interrupts = , + , + , + ; + arm,cpu-registers-not-fw-configured; + }; + + timer0: timer@10008000 { + compatible = "mediatek,mt7986-timer"; + reg = <0x10008000 0x1000>; + interrupts = ; + clocks = <&gpt_clk>; + clock-names = "gpt-clk"; + u-boot,dm-pre-reloc; + }; + + watchdog: watchdog@1001c000 { + compatible = "mediatek,mt7986-wdt"; + reg = <0x1001c000 0x1000>; + interrupts = ; + #reset-cells = <1>; + status = "disabled"; + }; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0x0c000000 0x40000>, /* GICD */ + <0x0c080000 0x200000>; /* GICR */ + + interrupts = ; + }; + + fixed_plls: apmixedsys@1001e000 { + compatible = "mediatek,mt7981-fixed-plls"; + reg = <0x1001e000 0x1000>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + topckgen: topckgen@1001b000 { + compatible = "mediatek,mt7981-topckgen"; + reg = <0x1001b000 0x1000>; + clock-parent = <&fixed_plls>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + infracfg_ao: infracfg_ao@10001000 { + compatible = "mediatek,mt7981-infracfg_ao"; + reg = <0x10001000 0x80>; + clock-parent = <&infracfg>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + infracfg: infracfg@10001000 { + compatible = "mediatek,mt7981-infracfg"; + reg = <0x10001000 0x30>; + clock-parent = <&topckgen>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + pinctrl: pinctrl@11d00000 { + compatible = "mediatek,mt7981-pinctrl"; + reg = <0x11d00000 0x1000>, + <0x11c00000 0x1000>, + <0x11c10000 0x1000>, + <0x11d20000 0x1000>, + <0x11e00000 0x1000>, + <0x11e20000 0x1000>, + <0x11f00000 0x1000>, + <0x11f10000 0x1000>, + <0x1000b000 0x1000>; + reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rm_base", + "iocfg_rb_base", "iocfg_lb_base", "iocfg_bl_base", + "iocfg_tm_base", "iocfg_tl_base", "eint"; + gpio: gpio-controller { + gpio-controller; + #gpio-cells = <2>; + }; + }; + + pwm: pwm@10048000 { + compatible = "mediatek,mt7981-pwm"; + reg = <0x10048000 0x1000>; + #clock-cells = <1>; + #pwm-cells = <2>; + interrupts = ; + clocks = <&infracfg CK_INFRA_PWM>, + <&infracfg_ao CK_INFRA_PWM_BSEL>, + <&infracfg_ao CK_INFRA_PWM1_CK>, + <&infracfg_ao CK_INFRA_PWM2_CK>, + /* FIXME */ + <&infracfg_ao CK_INFRA_PWM2_CK>; + assigned-clocks = <&topckgen CK_TOP_PWM_SEL>; + assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; + status = "disabled"; + }; + + uart0: serial@11002000 { + compatible = "mediatek,hsuart"; + reg = <0x11002000 0x400>; + interrupts = ; + clocks = <&infracfg_ao CK_INFRA_UART0_CK>; + assigned-clocks = <&topckgen CK_TOP_UART_SEL>, + <&infracfg_ao CK_INFRA_UART0_SEL>; + assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, + <&infracfg CK_INFRA_UART>; + mediatek,force-highspeed; + status = "disabled"; + u-boot,dm-pre-reloc; + }; + + uart1: serial@11003000 { + compatible = "mediatek,hsuart"; + reg = <0x11003000 0x400>; + interrupts = ; + clocks = <&infracfg_ao CK_INFRA_UART1_CK>; + assigned-clocks = <&topckgen CK_TOP_UART_SEL>, + <&infracfg_ao CK_INFRA_UART1_SEL>; + assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, + <&infracfg CK_INFRA_UART>; + mediatek,force-highspeed; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,hsuart"; + reg = <0x11004000 0x400>; + interrupts = ; + clocks = <&infracfg_ao CK_INFRA_UART2_CK>; + assigned-clocks = <&topckgen CK_TOP_UART_SEL>, + <&infracfg_ao CK_INFRA_UART2_SEL>; + assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, + <&infracfg CK_INFRA_UART>; + mediatek,force-highspeed; + status = "disabled"; + }; + + snand: snand@11005000 { + compatible = "mediatek,mt7986-snand"; + reg = <0x11005000 0x1000>, + <0x11006000 0x1000>; + reg-names = "nfi", "ecc"; + clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>, + <&infracfg_ao CK_INFRA_NFI1_CK>, + <&infracfg_ao CK_INFRA_NFI_HCK_CK>; + clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; + assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>, + <&topckgen CK_TOP_NFI1X_SEL>; + assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>, + <&topckgen CK_TOP_CB_M_D8>; + status = "disabled"; + }; + + ethsys: syscon@15000000 { + compatible = "mediatek,mt7981-ethsys", "syscon"; + reg = <0x15000000 0x1000>; + clock-parent = <&topckgen>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + eth: ethernet@15100000 { + compatible = "mediatek,mt7981-eth", "syscon"; + reg = <0x15100000 0x20000>; + resets = <ðsys ETHSYS_FE_RST>; + reset-names = "fe"; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sgmiisys0: syscon@10060000 { + compatible = "mediatek,mt7986-sgmiisys", "syscon"; + reg = <0x10060000 0x1000>; + pn_swap; + #clock-cells = <1>; + }; + + sgmiisys1: syscon@10070000 { + compatible = "mediatek,mt7986-sgmiisys", "syscon"; + reg = <0x10070000 0x1000>; + #clock-cells = <1>; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,ipm-spi"; + reg = <0x1100a000 0x100>; + clocks = <&infracfg_ao CK_INFRA_SPI0_CK>, + <&topckgen CK_TOP_SPI_SEL>; + assigned-clocks = <&topckgen CK_TOP_SPI_SEL>, + <&infracfg CK_INFRA_SPI0_SEL>; + assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>, + <&topckgen CK_INFRA_ISPI0>; + clock-names = "sel-clk", "spi-clk"; + interrupts = ; + status = "disabled"; + }; + + spi1: spi@1100b000 { + compatible = "mediatek,ipm-spi"; + reg = <0x1100b000 0x100>; + interrupts = ; + status = "disabled"; + }; + + spi2: spi@11009000 { + compatible = "mediatek,ipm-spi"; + reg = <0x11009000 0x100>; + clocks = <&infracfg_ao CK_INFRA_SPI0_CK>, + <&topckgen CK_TOP_SPI_SEL>; + assigned-clocks = <&topckgen CK_TOP_SPI_SEL>, + <&infracfg CK_INFRA_SPI0_SEL>; + assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>, + <&topckgen CK_INFRA_ISPI0>; + clock-names = "sel-clk", "spi-clk"; + interrupts = ; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt7981-mmc"; + reg = <0x11230000 0x1000>, + <0x11C20000 0x1000>; + interrupts = ; + clocks = <&topckgen CK_TOP_EMMC_400M>, + <&topckgen CK_TOP_EMMC_208M>, + <&infracfg_ao CK_INFRA_MSDC_CK>; + assigned-clocks = <&topckgen CK_TOP_EMMC_400M_SEL>, + <&topckgen CK_TOP_EMMC_208M_SEL>; + assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_D2>, + <&topckgen CK_TOP_CB_M_D2>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + +}; diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 82fadeba8a..04aa2fd97f 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -40,6 +40,15 @@ config TARGET_MT7629 including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet, switch, USB3.0, PCIe, UART, SPI, I2C and PWM. +config TARGET_MT7981 + bool "MediaTek MT7981 SoC" + select ARM64 + select CPU + help + The MediaTek MT7981 is a ARM64-based SoC with a dual-core Cortex-A53. + including UART, SPI, USB, NAND, SNFI, PWM, Gigabit Ethernet, I2C, + built-in Wi-Fi, and PCIe. + config TARGET_MT7986 bool "MediaTek MT7986 SoC" select ARM64 @@ -93,6 +102,7 @@ config SYS_BOARD default "mt7622" if TARGET_MT7622 default "mt7623" if TARGET_MT7623 default "mt7629" if TARGET_MT7629 + default "mt7981" if TARGET_MT7981 default "mt7986" if TARGET_MT7986 default "mt8183" if TARGET_MT8183 default "mt8512" if TARGET_MT8512 @@ -109,6 +119,7 @@ config SYS_CONFIG_NAME default "mt7622" if TARGET_MT7622 default "mt7623" if TARGET_MT7623 default "mt7629" if TARGET_MT7629 + default "mt7981" if TARGET_MT7981 default "mt7986" if TARGET_MT7986 default "mt8183" if TARGET_MT8183 default "mt8512" if TARGET_MT8512 @@ -124,7 +135,7 @@ config MTK_BROM_HEADER_INFO string default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622 default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 - default "media=snand;nandinfo=2k+64" if TARGET_MT7986 + default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 default "lk=1" if TARGET_MT7623 endif diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile index fe5c3a837c..fc85293f71 100644 --- a/arch/arm/mach-mediatek/Makefile +++ b/arch/arm/mach-mediatek/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_MT8512) += mt8512/ obj-$(CONFIG_TARGET_MT7622) += mt7622/ obj-$(CONFIG_TARGET_MT7623) += mt7623/ obj-$(CONFIG_TARGET_MT7629) += mt7629/ +obj-$(CONFIG_TARGET_MT7981) += mt7981/ obj-$(CONFIG_TARGET_MT7986) += mt7986/ obj-$(CONFIG_TARGET_MT8183) += mt8183/ obj-$(CONFIG_TARGET_MT8516) += mt8516/ diff --git a/arch/arm/mach-mediatek/mt7981/Makefile b/arch/arm/mach-mediatek/mt7981/Makefile new file mode 100644 index 0000000000..007eb4a367 --- /dev/null +++ b/arch/arm/mach-mediatek/mt7981/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o +obj-y += lowlevel_init.o diff --git a/arch/arm/mach-mediatek/mt7981/init.c b/arch/arm/mach-mediatek/mt7981/init.c new file mode 100644 index 0000000000..4f77a3defb --- /dev/null +++ b/arch/arm/mach-mediatek/mt7981/init.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam Shih + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G); + + return 0; +} + +void reset_cpu(ulong addr) +{ + psci_system_reset(); +} + +static struct mm_region mt7981_mem_map[] = { + { + /* DDR */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, + }, { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + 0, + } +}; + +struct mm_region *mem_map = mt7981_mem_map; diff --git a/arch/arm/mach-mediatek/mt7981/lowlevel_init.S b/arch/arm/mach-mediatek/mt7981/lowlevel_init.S new file mode 100644 index 0000000000..85a1cea359 --- /dev/null +++ b/arch/arm/mach-mediatek/mt7981/lowlevel_init.S @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam Shih + */ + +/* + * Switch from AArch64 EL2 to AArch32 EL2 + * @param inputs: + * x0: argument, zero + * x1: machine nr + * x2: fdt address + * x3: input argument + * x4: kernel entry point + * @param outputs for secure firmware: + * x0: function id + * x1: kernel entry point + * x2: machine nr + * x3: fdt address + * + * [1] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/mediatek/common/mtk_sip_svc.c +*/ + +.global armv8_el2_to_aarch32 +armv8_el2_to_aarch32: + mov x3, x2 + mov x2, x1 + mov x1, x4 + mov x4, #0 + ldr x0, =0x82000200 /* MTK_SIP_KERNEL_BOOT_AARCH32 */ + SMC #0 + ret