From patchwork Fri Apr 20 13:51:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 901936 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=xilinx.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=monstr-eu.20150623.gappssmtp.com header.i=@monstr-eu.20150623.gappssmtp.com header.b="oL1/jPuN"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40SHMt2rHZz9s19 for ; Fri, 20 Apr 2018 23:51:54 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 064D6C21E12; Fri, 20 Apr 2018 13:51:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 94672C21C57; Fri, 20 Apr 2018 13:51:45 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id DEAF7C21C29; Fri, 20 Apr 2018 13:51:43 +0000 (UTC) Received: from mail-wr0-f193.google.com (mail-wr0-f193.google.com [209.85.128.193]) by lists.denx.de (Postfix) with ESMTPS id 7E7CAC21C27 for ; Fri, 20 Apr 2018 13:51:43 +0000 (UTC) Received: by mail-wr0-f193.google.com with SMTP id q3-v6so13206101wrj.6 for ; Fri, 20 Apr 2018 06:51:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monstr-eu.20150623.gappssmtp.com; s=20150623; h=sender:from:to:cc:subject:date:message-id; bh=ZtOo31tFUjOUr1N791W9I7nurVj/IVv8Rq6+zw5c6+M=; b=oL1/jPuNk6tSlKMQM0xNDzzeP8tQIFuvS3tTOCv1fnkEy4kPS3gnZiOFfmPYfQMVTD mnEUN+III7spJj4wVcfmyFxqe7E0hQSH6w+y4Zrfpw/PMtWK5zgXFTZso9LSTAsGpNbT LLTlZK7xCgI27LD4ddY6JLG+Oo90GY1xqmTKiU6zR5Dz8YBC236dyuQljU5ax3vZ18Aa EcKUMh/OssvREWqf05ll3OybGWmXJykPzZtbRxSg3774rK+StRzPai1AzyHefRBrT3Yh gFYZ7cQeM6HN4QbTYoQ7gXBA9jqS/F+dHSK91cDnCGSHVU9pFBIzQ12zAQH4vKJbpwpK 1Vzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=ZtOo31tFUjOUr1N791W9I7nurVj/IVv8Rq6+zw5c6+M=; b=CQ2JECubiYlUT2GFuPaW0eRBh8WTMMnCVtTylRO4RYrY1qpjpK+j/dWuJ4DTVV2QXd lfuw58JpH22lPcyWrwH4YjMuJ7TCAZcdyzxTxFvxfJSkUfSgrJ6D+kRduSuDi/rzlGRa lL2Gv/2i1AkOg8gjpgDtqDVIvjknFVOu4xHZIVGEDKVN6NWUcOYxGuNl9bHZ9sXCLVRi h/BlE1Ns7pZalKl6fsdpcFbgUTDHyE8x81tW6RxyU/8xNm5OWrQDcld2d1O8smpaRWc7 QJdyyZjMM2f5xmoO+hyqGp0VJP8C3iUDB7sKnVVhm+DH2XddezDHe5YVZKSt94HW+g3b WniA== X-Gm-Message-State: ALQs6tCQq0VRSlJkRL978sA9rgPAz4Ydt2JTB24Xga7nBH70A9amJHKG eIqg6jwiGU6cHp08iS304auHRYFt X-Google-Smtp-Source: AIpwx48+b5o8QkwppHckCv1RrklxCHVmPTHGAx6Z2BGVDLWYJ30Z/ZDBTBGwHzPbkbdTpQQfinz0Mg== X-Received: by 2002:adf:8861:: with SMTP id e30-v6mr7873652wre.252.1524232302861; Fri, 20 Apr 2018 06:51:42 -0700 (PDT) Received: from localhost (nat-35.starnet.cz. [178.255.168.35]) by smtp.gmail.com with ESMTPSA id g75sm2822087wmc.47.2018.04.20.06.51.42 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 20 Apr 2018 06:51:42 -0700 (PDT) From: Michal Simek To: u-boot@lists.denx.de, agraf@suse.de Date: Fri, 20 Apr 2018 15:51:40 +0200 Message-Id: <0662f83f37aa9e9fe96cb1b940ea9bac947512a9.1524232297.git.michal.simek@xilinx.com> X-Mailer: git-send-email 2.17.0 Subject: [U-Boot] [PATCH 1/2] arm: Add minimal support for Cortex-R5 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This minimal support will be used by Xilinx ZynqMP R5 cpu. Signed-off-by: Michal Simek --- arch/arm/Kconfig | 6 ++++++ arch/arm/cpu/armv7r/Makefile | 4 ++++ arch/arm/cpu/armv7r/config.mk | 3 +++ arch/arm/cpu/armv7r/cpu.c | 24 ++++++++++++++++++++++++ arch/arm/cpu/armv7r/start.S | 17 +++++++++++++++++ 5 files changed, 54 insertions(+) create mode 100644 arch/arm/cpu/armv7r/Makefile create mode 100644 arch/arm/cpu/armv7r/config.mk create mode 100644 arch/arm/cpu/armv7r/cpu.c create mode 100644 arch/arm/cpu/armv7r/start.S diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b5fbce03667d..b10804f55224 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -192,6 +192,10 @@ config CPU_V7M select THUMB2_KERNEL select SYS_CACHE_SHIFT_5 +config CPU_V7R + bool + select SYS_CACHE_SHIFT_6 + config CPU_PXA bool select SYS_CACHE_SHIFT_5 @@ -209,6 +213,7 @@ config SYS_CPU default "arm1176" if CPU_ARM1176 default "armv7" if CPU_V7 default "armv7m" if CPU_V7M + default "armv7r" if CPU_V7R default "pxa" if CPU_PXA default "sa1100" if CPU_SA1100 default "armv8" if ARM64 @@ -223,6 +228,7 @@ config SYS_ARM_ARCH default 6 if CPU_ARM1176 default 7 if CPU_V7 default 7 if CPU_V7M + default 7 if CPU_V7R default 5 if CPU_PXA default 4 if CPU_SA1100 default 8 if ARM64 diff --git a/arch/arm/cpu/armv7r/Makefile b/arch/arm/cpu/armv7r/Makefile new file mode 100644 index 000000000000..3c66976dfa62 --- /dev/null +++ b/arch/arm/cpu/armv7r/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +extra-y := start.o +obj-y += cpu.o diff --git a/arch/arm/cpu/armv7r/config.mk b/arch/arm/cpu/armv7r/config.mk new file mode 100644 index 000000000000..224d191ff846 --- /dev/null +++ b/arch/arm/cpu/armv7r/config.mk @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +PLATFORM_CPPFLAGS += -mcpu=cortex-r5 -DARMR5 diff --git a/arch/arm/cpu/armv7r/cpu.c b/arch/arm/cpu/armv7r/cpu.c new file mode 100644 index 000000000000..e384a530c5e0 --- /dev/null +++ b/arch/arm/cpu/armv7r/cpu.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2018 Xilinx, Inc. (Michal Simek) + */ + +#include + +/* + * This is called right before passing control to + * the Linux kernel point. + */ +int cleanup_before_linux(void) +{ + return 0; +} + +/* + * Perform the low-level reset. + */ +void reset_cpu(ulong addr) +{ + while (1) + ; +} diff --git a/arch/arm/cpu/armv7r/start.S b/arch/arm/cpu/armv7r/start.S new file mode 100644 index 000000000000..d6e8eecf54b7 --- /dev/null +++ b/arch/arm/cpu/armv7r/start.S @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 + * Kamil Lulko, + * + */ + +#include + +.globl reset +.type reset, %function +reset: + W(b) _main + +.globl c_runtime_cpu_setup +c_runtime_cpu_setup: + mov pc, lr