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[v4,12/23] reset: mtmips: add reset controller support for MediaTek MT7620 SoC

Message ID 06473c793f8f45918c23eefa7d10d28dab41eae2.1605169080.git.weijie.gao@mediatek.com
State Awaiting Upstream
Delegated to: Daniel Schwierzeck
Headers show
Series Add support for MediaTek MT7620 SoC - v4 | expand

Commit Message

Weijie Gao Nov. 12, 2020, 8:36 a.m. UTC
This patch adds reset controller bits definition header file for MediaTek
MT7620 SoC

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
v4 changes: none
v3 changes: none
v2 changes: none
---
 include/dt-bindings/reset/mt7620-reset.h | 35 ++++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 include/dt-bindings/reset/mt7620-reset.h
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Patch

diff --git a/include/dt-bindings/reset/mt7620-reset.h b/include/dt-bindings/reset/mt7620-reset.h
new file mode 100644
index 0000000000..3096b29cdb
--- /dev/null
+++ b/include/dt-bindings/reset/mt7620-reset.h
@@ -0,0 +1,35 @@ 
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author:  Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_MT7620_RESET_H_
+#define _DT_BINDINGS_MT7620_RESET_H_
+
+#define PPE_RST			31
+#define SDHC_RST		30
+#define MIPS_CNT_RST		28
+#define PCIE_RST		26
+#define UHST_RST		25
+#define EPHY_RST		24
+#define ESW_RST			23
+#define UDEV_RST		22
+#define FE_RST			21
+#define WLAN_RST		20
+#define UARTL_RST		19
+#define SPI_RST			18
+#define I2S_RST			17
+#define I2C_RST			16
+#define NAND_RST		15
+#define DMA_RST			14
+#define PIO_RST			13
+#define UARTF_RST		12
+#define PCM_RST			11
+#define MC_RST			10
+#define INTC_RST		9
+#define TIMER_RST		8
+#define SYS_RST			0
+
+#endif /* _DT_BINDINGS_MT7620_RESET_H_ */