From patchwork Mon Oct 15 07:59:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Lahoudere X-Patchwork-Id: 984095 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=collabora.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42YbTM6BmPz9s5c for ; Mon, 15 Oct 2018 22:15:35 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 5E025C21DD7; Mon, 15 Oct 2018 11:13:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_PASS, UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 43FC0C21DD9; Mon, 15 Oct 2018 11:13:00 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 6E327C21C2C; Mon, 15 Oct 2018 07:59:54 +0000 (UTC) Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lists.denx.de (Postfix) with ESMTPS id 0C033C21BE5 for ; Mon, 15 Oct 2018 07:59:54 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: aragua) with ESMTPSA id DC8B327DF19 From: Fabien Lahoudere To: u-boot@lists.denx.de Date: Mon, 15 Oct 2018 09:59:44 +0200 Message-Id: <057fe479c0fb8a9583f49d9193fd0f04a4713e8a.1539333733.git.fabien.lahoudere@collabora.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: References: In-Reply-To: References: X-Mailman-Approved-At: Mon, 15 Oct 2018 11:12:56 +0000 Cc: ian.ray@ge.com, Fabien Lahoudere Subject: [U-Boot] [PATCH 1/2] board: ge: bx50v3: correct LDB clock X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Ian Ray Use Video PLL to provide 65MHz for all displays. Signed-off-by: Ian Ray Signed-off-by: Fabien Lahoudere --- board/ge/bx50v3/bx50v3.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index b2d065c..f07141b 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -426,14 +426,22 @@ static void enable_videopll(void) setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); - /* set video pll to 910MHz (24MHz * (37+11/12)) - * video pll post div to 910/4 = 227.5MHz - */ + /* PLL_VIDEO 455MHz (24MHz * (37+11/12) / 2) + * | + * PLL5 + * | + * CS2CDR[LDB_DI0_CLK_SEL] + * | + * +----> LDB_DI0_SERIAL_CLK_ROOT + * | + * +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU 455 / 7 = 65 MHz + */ + clrsetbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_DIV_SELECT | BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT, BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) | - BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0)); + BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1)); writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); @@ -459,8 +467,8 @@ static void setup_display_b850v3(void) enable_videopll(); - /* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */ - clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); + /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */ + setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); imx_setup_hdmi(); @@ -507,7 +515,7 @@ static void setup_display_bx50v3(void) */ mdelay(200); - /* IPU1 DI0 clock is 480/7 = 68.5 MHz */ + /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */ setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); /* Set LDB_DI0 as clock source for IPU_DI0 */ @@ -683,12 +691,8 @@ int board_early_init_f(void) setup_iomux_uart(); #if defined(CONFIG_VIDEO_IPUV3) - if (is_b850v3()) - /* Set LDB clock to Video PLL */ - select_ldb_di_clock_source(MXC_PLL5_CLK); - else - /* Set LDB clock to USB PLL */ - select_ldb_di_clock_source(MXC_PLL3_SW_CLK); + /* Set LDB clock to Video PLL */ + select_ldb_di_clock_source(MXC_PLL5_CLK); #endif return 0; }