@@ -279,10 +279,14 @@
&zynqmp_dpdma {
clocks = <&zynqmp_clk DPDMA_REF>;
+ assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */
};
&zynqmp_dpsub {
clocks = <&zynqmp_clk TOPSW_LSBUS>,
<&zynqmp_clk DP_AUDIO_REF>,
<&zynqmp_clk DP_VIDEO_REF>;
+ assigned-clocks = <&zynqmp_clk DP_STC_REF>,
+ <&zynqmp_clk DP_AUDIO_REF>,
+ <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */
};
@@ -115,10 +115,12 @@
status = "disabled";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
+ assigned-clock-rates = <27000000>, <25000000>, <300000000>;
};
&zynqmp_dpdma {
status = "okay";
+ assigned-clock-rates = <600000000>;
};
&usb0 {
@@ -95,10 +95,12 @@
status = "disabled";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
+ assigned-clock-rates = <27000000>, <25000000>, <300000000>;
};
&zynqmp_dpdma {
status = "okay";
+ assigned-clock-rates = <600000000>;
};
&usb0 {
Clocks are coming from shared HW design where these frequencies should be aligned with PLL setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com> --- arch/arm/dts/zynqmp-clk-ccf.dtsi | 4 ++++ arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 2 ++ arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 2 ++ 3 files changed, 8 insertions(+)