diff --git a/.travis.yml b/.travis.yml
index fe9148fc75..c4d96a0338 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -194,12 +194,6 @@ matrix:
         - BUILDMAN="mips"
           TOOLCHAIN="mips"
     - env:
-        - BUILDMAN="mpc512x"
-    - env:
-        - BUILDMAN="mpc5xx"
-    - env:
-        - BUILDMAN="mpc5xxx"
-    - env:
         - BUILDMAN="mpc83xx"
     - env:
         - BUILDMAN="mpc85xx -x freescale"
diff --git a/MAINTAINERS b/MAINTAINERS
index 0cadc51321..7f8526272e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -321,12 +321,6 @@ M:	Wolfgang Denk <wd@denx.de>
 S:	Maintained
 F:	arch/powerpc/
 
-POWERPC MPC5XXX
-M:	Wolfgang Denk <wd@denx.de>
-S:	Maintained
-T:	git git://git.denx.de/u-boot-mpc5xxx.git
-F:	arch/powerpc/cpu/mpc5*/
-
 POWERPC MPC8XX
 M:	Wolfgang Denk <wd@denx.de>
 S:	Maintained
diff --git a/README b/README
index 260a44973f..eb370a1cdf 100644
--- a/README
+++ b/README
@@ -636,10 +636,6 @@ The following options need to be configured:
 		 * Adds the "fdt" command
 		 * The bootm command automatically updates the fdt
 
-		OF_CPU - The proper name of the cpus node (only required for
-			MPC512X and MPC5xxx based boards).
-		OF_SOC - The proper name of the soc node (only required for
-			MPC512X and MPC5xxx based boards).
 		OF_TBCLK - The timebase frequency.
 		OF_STDOUT_PATH - The path to the console device
 
@@ -1282,7 +1278,7 @@ The following options need to be configured:
 
 - USB Support:
 		At the moment only the UHCI host controller is
-		supported (PIP405, MIP405, MPC5200); define
+		supported (PIP405, MIP405); define
 		CONFIG_USB_UHCI to enable it.
 		define CONFIG_USB_KEYBOARD to enable the USB Keyboard
 		and define CONFIG_USB_STORAGE to enable the USB
@@ -1290,19 +1286,6 @@ The following options need to be configured:
 		Note:
 		Supported are USB Keyboards and USB Floppy drives
 		(TEAC FD-05PUB).
-		MPC5200 USB requires additional defines:
-			CONFIG_USB_CLOCK
-				for 528 MHz Clock: 0x0001bbbb
-			CONFIG_PSC3_USB
-				for USB on PSC3
-			CONFIG_USB_CONFIG
-				for differential drivers: 0x00001000
-				for single ended drivers: 0x00005000
-				for differential drivers on PSC3: 0x00000100
-				for single ended drivers on PSC3: 0x00004100
-			CONFIG_SYS_USB_EVENT_POLL
-				May be defined to allow interrupt polling
-				instead of using asynchronous interrupts
 
 		CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
 		txfilltuning field in the EHCI controller on reset.
diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c
index f6a93cad45..fcfa2ad8ff 100644
--- a/api/api_platform-powerpc.c
+++ b/api/api_platform-powerpc.c
@@ -33,8 +33,6 @@ int platform_sys_info(struct sys_info *si)
 #if defined(CONFIG_8xx) || \
     defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 #define bi_bar	bi_immr_base
-#elif defined(CONFIG_MPC5xxx)
-#define bi_bar	bi_mbar_base
 #elif defined(CONFIG_MPC83xx)
 #define bi_bar	bi_immrbar
 #endif
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 7d206b30b9..8cab8508ac 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -8,12 +8,6 @@ choice
 	prompt "CPU select"
 	optional
 
-config MPC512X
-	bool "MPC512X"
-
-config MPC5xxx
-	bool "MPC5xxx"
-
 config MPC83xx
 	bool "MPC83xx"
 	select CREATE_ARCH_SYMLINK
@@ -45,8 +39,6 @@ config 4xx
 
 endchoice
 
-source "arch/powerpc/cpu/mpc512x/Kconfig"
-source "arch/powerpc/cpu/mpc5xxx/Kconfig"
 source "arch/powerpc/cpu/mpc83xx/Kconfig"
 source "arch/powerpc/cpu/mpc85xx/Kconfig"
 source "arch/powerpc/cpu/mpc86xx/Kconfig"
diff --git a/arch/powerpc/cpu/mpc512x/Kconfig b/arch/powerpc/cpu/mpc512x/Kconfig
deleted file mode 100644
index 53450aeaba..0000000000
--- a/arch/powerpc/cpu/mpc512x/Kconfig
+++ /dev/null
@@ -1,34 +0,0 @@
-menu "mpc512x CPU"
-	depends on MPC512X
-
-config SYS_CPU
-	default "mpc512x"
-
-choice
-	prompt "Target select"
-	optional
-
-config TARGET_PDM360NG
-	bool "Support pdm360ng"
-
-config TARGET_ARIA
-	bool "Support aria"
-
-config TARGET_MECP5123
-	bool "Support mecp5123"
-
-config TARGET_MPC5121ADS
-	bool "Support mpc5121ads"
-
-config TARGET_AC14XX
-	bool "Support ac14xx"
-
-endchoice
-
-source "board/davedenx/aria/Kconfig"
-source "board/esd/mecp5123/Kconfig"
-source "board/freescale/mpc5121ads/Kconfig"
-source "board/ifm/ac14xx/Kconfig"
-source "board/pdm360ng/Kconfig"
-
-endmenu
diff --git a/arch/powerpc/cpu/mpc512x/Makefile b/arch/powerpc/cpu/mpc512x/Makefile
deleted file mode 100644
index 933deebdae..0000000000
--- a/arch/powerpc/cpu/mpc512x/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# (C) Copyright 2007-2009 DENX Software Engineering
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-extra-y	= start.o
-obj-y	:= cpu.o
-obj-y	+= traps.o
-obj-y += cpu_init.o
-obj-y += fixed_sdram.o
-obj-y += interrupts.o
-obj-y += iopin.o
-obj-y += serial.o
-obj-y += speed.o
-obj-$(CONFIG_FSL_DIU_FB) += diu.o
-obj-$(CONFIG_CMD_IDE) += ide.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/powerpc/cpu/mpc512x/asm-offsets.h b/arch/powerpc/cpu/mpc512x/asm-offsets.h
deleted file mode 100644
index 957d4be2d2..0000000000
--- a/arch/powerpc/cpu/mpc512x/asm-offsets.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * needed for arch/powerpc/cpu/mpc512x/start.S
- *
- * These should be auto-generated
- */
-#define LPCS0AW			0x0024
-#define SRAMBAR			0x00C4
-#define SWCRR			0x0904
-#define LPC_OFFSET		0x10000
-#define CS0_CONFIG		0x00000
-#define CS_CTRL			0x00020
-#define CS_CTRL_ME		0x01000000	/* CS Master Enable bit */
-
-#define EXC_OFF_SYS_RESET	0x0100
-#define	_START_OFFSET		EXC_OFF_SYS_RESET
diff --git a/arch/powerpc/cpu/mpc512x/config.mk b/arch/powerpc/cpu/mpc512x/config.mk
deleted file mode 100644
index 5bf1b2a3b9..0000000000
--- a/arch/powerpc/cpu/mpc512x/config.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2007-2010 DENX Software Engineering
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_E300 -msoft-float -mcpu=603e
diff --git a/arch/powerpc/cpu/mpc512x/cpu.c b/arch/powerpc/cpu/mpc512x/cpu.c
deleted file mode 100644
index ce524fcdc7..0000000000
--- a/arch/powerpc/cpu/mpc512x/cpu.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * (C) Copyright 2007-2010 DENX Software Engineering
- * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * CPU specific code for the MPC512x family.
- *
- * Derived from the MPC83xx code.
- */
-
-#include <common.h>
-#include <command.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-#if defined(CONFIG_OF_LIBFDT)
-#include <fdt_support.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkcpu (void)
-{
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-	ulong clock = gd->cpu_clk;
-	u32 pvr = get_pvr ();
-	u32 spridr = in_be32(&immr->sysconf.spridr);
-	char buf1[32], buf2[32];
-
-	puts ("CPU:   ");
-
-	switch (spridr & 0xffff0000) {
-	case SPR_5121E:
-		puts ("MPC5121e ");
-		break;
-	default:
-		printf ("Unknown part ID %08x ", spridr & 0xffff0000);
-	}
-	printf ("rev. %d.%d, Core ", SVR_MJREV (spridr), SVR_MNREV (spridr));
-
-	switch (pvr & 0xffff0000) {
-	case PVR_E300C4:
-		puts ("e300c4 ");
-		break;
-	default:
-		puts ("unknown ");
-	}
-	printf ("at %s MHz, CSB at %s MHz (RSR=0x%04lx)\n",
-		strmhz(buf1, clock),
-		strmhz(buf2, gd->arch.csb_clk),
-		gd->arch.reset_status & 0xffff);
-	return 0;
-}
-
-
-int
-do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
-	ulong msr;
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
-	/* Interrupts and MMU off */
-	__asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
-
-	msr &= ~( MSR_EE | MSR_IR | MSR_DR);
-	__asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
-
-	/*
-	 * Enable Reset Control Reg - "RSTE" is the magic word that let us go
-	 */
-	out_be32(&immap->reset.rpr, 0x52535445);
-
-	/* Verify Reset Control Reg is enabled */
-	while (!(in_be32(&immap->reset.rcer) & RCER_CRE))
-		;
-
-	printf ("Resetting the board.\n");
-	udelay(200);
-
-	/* Perform reset */
-	out_be32(&immap->reset.rcr, RCR_SWHR);
-
-	/* Unreached... */
-	return 1;
-}
-
-
-/*
- * Get timebase clock frequency (like cpu_clk in Hz)
- */
-unsigned long get_tbclk (void)
-{
-	return (gd->bus_clk + 3L) / 4L;
-}
-
-
-#if defined(CONFIG_WATCHDOG)
-void watchdog_reset (void)
-{
-	int re_enable = disable_interrupts ();
-
-	/* Reset watchdog */
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-	out_be32(&immr->wdt.swsrr, 0x556c);
-	out_be32(&immr->wdt.swsrr, 0xaa39);
-
-	if (re_enable)
-		enable_interrupts ();
-}
-#endif
-
-#ifdef CONFIG_OF_LIBFDT
-
-#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
-/*
- * fdt setup for old device trees
- * fix up
- * 	cpu clocks
- * 	soc clocks
- * 	ethernet addresses
- */
-static void old_ft_cpu_setup(void *blob, bd_t *bd)
-{
-	/*
-	 * avoid fixing up by path because that
-	 * produces scary error messages
-	 */
-	uchar enetaddr[6];
-
-	/*
-	 * old device trees have ethernet nodes with
-	 * device_type = "network"
-	 */
-	eth_getenv_enetaddr("ethaddr", enetaddr);
-	do_fixup_by_prop(blob, "device_type", "network", 8,
-		"local-mac-address", enetaddr, 6, 0);
-	do_fixup_by_prop(blob, "device_type", "network", 8,
-		"address", enetaddr, 6, 0);
-	/*
-	 * old device trees have soc nodes with
-	 * device_type = "soc"
-	 */
-	do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
-		"bus-frequency", bd->bi_ipsfreq, 0);
-}
-#endif
-
-static void ft_clock_setup(void *blob, bd_t *bd)
-{
-	char *cpu_path = "/cpus/" OF_CPU;
-
-	/*
-	 * fixup cpu clocks using path
-	 */
-	do_fixup_by_path_u32(blob, cpu_path,
-		"timebase-frequency", OF_TBCLK, 1);
-	do_fixup_by_path_u32(blob, cpu_path,
-		"bus-frequency", bd->bi_busfreq, 1);
-	do_fixup_by_path_u32(blob, cpu_path,
-		"clock-frequency", bd->bi_intfreq, 1);
-	/*
-	 * fixup soc clocks using compatible
-	 */
-	do_fixup_by_compat_u32(blob, OF_SOC_COMPAT,
-		"bus-frequency", bd->bi_ipsfreq, 1);
-}
-
-void ft_cpu_setup(void *blob, bd_t *bd)
-{
-#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
-	old_ft_cpu_setup(blob, bd);
-#endif
-	ft_clock_setup(blob, bd);
-	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
-}
-#endif
-
-#ifdef CONFIG_MPC512x_FEC
-/* Default initializations for FEC controllers.  To override,
- * create a board-specific function called:
- * 	int board_eth_init(bd_t *bis)
- */
-
-int cpu_eth_init(bd_t *bis)
-{
-	return mpc512x_fec_initialize(bis);
-}
-#endif
diff --git a/arch/powerpc/cpu/mpc512x/cpu_init.c b/arch/powerpc/cpu/mpc512x/cpu_init.c
deleted file mode 100644
index 48a5e4f8b2..0000000000
--- a/arch/powerpc/cpu/mpc512x/cpu_init.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
- * Copyright (C) 2007-2009 DENX Software Engineering
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Derived from the MPC83xx code.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/mpc512x.h>
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Set up the memory map, initialize registers,
- */
-void cpu_init_f (volatile immap_t * im)
-{
-	u32 ips_div;
-
-	/* Pointer is writable since we allocated a register for it */
-	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
-
-	/* Clear initial global data */
-	memset ((void *) gd, 0, sizeof (gd_t));
-
-	/* Local Window and chip select configuration */
-#if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE)
-	out_be32(&im->sysconf.lpcs0aw,
-		CSAW_START(CONFIG_SYS_CS0_START) |
-		CSAW_STOP(CONFIG_SYS_CS0_START, CONFIG_SYS_CS0_SIZE));
-	sync_law(&im->sysconf.lpcs0aw);
-#endif
-#if defined(CONFIG_SYS_CS0_CFG)
-	out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
-#endif
-
-#if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE)
-	out_be32(&im->sysconf.lpcs1aw,
-		CSAW_START(CONFIG_SYS_CS1_START) |
-		CSAW_STOP(CONFIG_SYS_CS1_START, CONFIG_SYS_CS1_SIZE));
-	sync_law(&im->sysconf.lpcs1aw);
-#endif
-#if defined(CONFIG_SYS_CS1_CFG)
-	out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
-#endif
-
-#if defined(CONFIG_SYS_CS2_START) && (defined CONFIG_SYS_CS2_SIZE)
-	out_be32(&im->sysconf.lpcs2aw,
-		CSAW_START(CONFIG_SYS_CS2_START) |
-		CSAW_STOP(CONFIG_SYS_CS2_START, CONFIG_SYS_CS2_SIZE));
-	sync_law(&im->sysconf.lpcs2aw);
-#endif
-#if defined(CONFIG_SYS_CS2_CFG)
-	out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
-#endif
-
-#if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE)
-	out_be32(&im->sysconf.lpcs3aw,
-		CSAW_START(CONFIG_SYS_CS3_START) |
-		CSAW_STOP(CONFIG_SYS_CS3_START, CONFIG_SYS_CS3_SIZE));
-	sync_law(&im->sysconf.lpcs3aw);
-#endif
-#if defined(CONFIG_SYS_CS3_CFG)
-	out_be32(&im->lpc.cs_cfg[3], CONFIG_SYS_CS3_CFG);
-#endif
-
-#if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE)
-	out_be32(&im->sysconf.lpcs4aw,
-		CSAW_START(CONFIG_SYS_CS4_START) |
-		CSAW_STOP(CONFIG_SYS_CS4_START, CONFIG_SYS_CS4_SIZE));
-	sync_law(&im->sysconf.lpcs4aw);
-#endif
-#if defined(CONFIG_SYS_CS4_CFG)
-	out_be32(&im->lpc.cs_cfg[4], CONFIG_SYS_CS4_CFG);
-#endif
-
-#if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE)
-	out_be32(&im->sysconf.lpcs5aw,
-		CSAW_START(CONFIG_SYS_CS5_START) |
-		CSAW_STOP(CONFIG_SYS_CS5_START, CONFIG_SYS_CS5_SIZE));
-	sync_law(&im->sysconf.lpcs5aw);
-#endif
-#if defined(CONFIG_SYS_CS5_CFG)
-	out_be32(&im->lpc.cs_cfg[5], CONFIG_SYS_CS5_CFG);
-#endif
-
-#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
-	out_be32(&im->sysconf.lpcs6aw,
-		CSAW_START(CONFIG_SYS_CS6_START) |
-		CSAW_STOP(CONFIG_SYS_CS6_START, CONFIG_SYS_CS6_SIZE));
-	sync_law(&im->sysconf.lpcs6aw);
-#endif
-#if defined(CONFIG_SYS_CS6_CFG)
-	out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG);
-#endif
-
-#if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE)
-	out_be32(&im->sysconf.lpcs7aw,
-		CSAW_START(CONFIG_SYS_CS7_START) |
-		CSAW_STOP(CONFIG_SYS_CS7_START, CONFIG_SYS_CS7_SIZE));
-	sync_law(&im->sysconf.lpcs7aw);
-#endif
-#if defined(CONFIG_SYS_CS7_CFG)
-	out_be32(&im->lpc.cs_cfg[7], CONFIG_SYS_CS7_CFG);
-#endif
-
-#if defined CONFIG_SYS_CS_ALETIMING
-	if (SVR_MJREV(in_be32(&im->sysconf.spridr)) >= 2)
-		out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
-#endif
-#if defined CONFIG_SYS_CS_BURST
-	out_be32(&im->lpc.cs_bcr, CONFIG_SYS_CS_BURST);
-#endif
-#if defined CONFIG_SYS_CS_DEADCYCLE
-	out_be32(&im->lpc.cs_dccr, CONFIG_SYS_CS_DEADCYCLE);
-#endif
-#if defined CONFIG_SYS_CS_HOLDCYCLE
-	out_be32(&im->lpc.cs_hccr, CONFIG_SYS_CS_HOLDCYCLE);
-#endif
-
-	/* system performance tweaking */
-
-#ifdef CONFIG_SYS_ACR_PIPE_DEP
-	/* Arbiter pipeline depth */
-	out_be32(&im->arbiter.acr,
-		(im->arbiter.acr & ~ACR_PIPE_DEP) |
-		(CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT)
-	);
-#endif
-
-#ifdef CONFIG_SYS_ACR_RPTCNT
-	/* Arbiter repeat count */
-	out_be32(im->arbiter.acr,
-		(im->arbiter.acr & ~(ACR_RPTCNT)) |
-		(CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT)
-	);
-#endif
-
-	/* RSR - Reset Status Register - clear all status */
-	gd->arch.reset_status = im->reset.rsr;
-	out_be32(&im->reset.rsr, ~RSR_RES);
-
-	/*
-	 * RMR - Reset Mode Register - enable checkstop reset
-	 */
-	out_be32(&im->reset.rmr, RMR_CSRE & (1 << RMR_CSRE_SHIFT));
-
-	/* Set IPS-CSB divider: IPS = 1/2 CSB */
-	ips_div = in_be32(&im->clk.scfr[0]);
-	ips_div &= ~(SCFR1_IPS_DIV_MASK);
-	ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT;
-	out_be32(&im->clk.scfr[0], ips_div);
-
-#ifdef SCFR1_LPC_DIV
-	clrsetbits_be32(&im->clk.scfr[0], SCFR1_LPC_DIV_MASK,
-			SCFR1_LPC_DIV << SCFR1_LPC_DIV_SHIFT);
-#endif
-
-#ifdef SCFR1_NFC_DIV
-	clrsetbits_be32(&im->clk.scfr[0], SCFR1_NFC_DIV_MASK,
-			SCFR1_NFC_DIV << SCFR1_NFC_DIV_SHIFT);
-#endif
-
-#ifdef SCFR1_DIU_DIV
-	clrsetbits_be32(&im->clk.scfr[0], SCFR1_DIU_DIV_MASK,
-			SCFR1_DIU_DIV << SCFR1_DIU_DIV_SHIFT);
-#endif
-
-	/*
-	 * Enable Time Base/Decrementer
-	 *
-	 * NOTICE: TB needs to be enabled as early as possible in order to
-	 * have udelay() working; if not enabled, usually leads to a hang, like
-	 * during FLASH chip identification etc.
-	 */
-	setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
-
-	/*
-	 * Enable clocks
-	 */
-	out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
-	out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
-#if defined(CONFIG_FSL_IIM) || defined(CONFIG_CMD_FUSE)
-	setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
-#endif
-}
-
-int cpu_init_r (void)
-{
-	return 0;
-}
diff --git a/arch/powerpc/cpu/mpc512x/diu.c b/arch/powerpc/cpu/mpc512x/diu.c
deleted file mode 100644
index 36e1f9cffd..0000000000
--- a/arch/powerpc/cpu/mpc512x/diu.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- * York Sun <yorksun@freescale.com>
- *
- * FSL DIU Framebuffer driver
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-
-#include <fsl_diu_fb.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void diu_set_pixel_clock(unsigned int pixclock)
-{
-	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile clk512x_t *clk = &immap->clk;
-	volatile unsigned int *clkdvdr = &clk->scfr[0];
-	unsigned long speed_ccb, temp, pixval;
-
-	speed_ccb = get_bus_freq(0) * 4;
-	temp = 1000000000/pixclock;
-	temp *= 1000;
-	pixval = speed_ccb / temp;
-	debug("DIU pixval = %lu\n", pixval);
-
-	/* Modify PXCLK in GUTS CLKDVDR */
-	debug("DIU: Current value of CLKDVDR = 0x%08x\n", in_be32(clkdvdr));
-	temp = in_be32(clkdvdr) & 0xFFFFFF00;
-	out_be32(clkdvdr, temp | (pixval & 0xFF));
-	debug("DIU: Modified value of CLKDVDR = 0x%08x\n", in_be32(clkdvdr));
-}
-
-int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
-{
-	unsigned int pixel_format = 0x88883316;
-
-	debug("mpc5121_diu_init\n");
-	return fsl_diu_init(xres, yres, pixel_format, 0);
-}
diff --git a/arch/powerpc/cpu/mpc512x/fixed_sdram.c b/arch/powerpc/cpu/mpc512x/fixed_sdram.c
deleted file mode 100644
index 68c5f8a27b..0000000000
--- a/arch/powerpc/cpu/mpc512x/fixed_sdram.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * (C) Copyright 2007-2009 DENX Software Engineering
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/mpc512x.h>
-
-/*
- * MDDRC Config Runtime Settings
- */
-ddr512x_config_t default_mddrc_config = {
-	.ddr_sys_config   = CONFIG_SYS_MDDRC_SYS_CFG,
-	.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
-	.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1,
-	.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2,
-};
-
-u32 default_init_seq[] = {
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_PCHG_ALL,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_RFSH,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_RFSH,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_MICRON_INIT_DEV_OP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_EM2,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_PCHG_ALL,
-	CONFIG_SYS_DDRCMD_EM2,
-	CONFIG_SYS_DDRCMD_EM3,
-	CONFIG_SYS_DDRCMD_EN_DLL,
-	CONFIG_SYS_MICRON_INIT_DEV_OP,
-	CONFIG_SYS_DDRCMD_PCHG_ALL,
-	CONFIG_SYS_DDRCMD_RFSH,
-	CONFIG_SYS_MICRON_INIT_DEV_OP,
-	CONFIG_SYS_DDRCMD_OCD_DEFAULT,
-	CONFIG_SYS_DDRCMD_PCHG_ALL,
-	CONFIG_SYS_DDRCMD_NOP
-};
-
-/*
- * fixed sdram init:
- * The board doesn't use memory modules that have serial presence
- * detect or similar mechanism for discovery of the DRAM settings
- */
-long int fixed_sdram(ddr512x_config_t *mddrc_config,
-			u32 *dram_init_seq, int seq_sz)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 msize = CONFIG_SYS_MAX_RAM_SIZE;
-	u32 msize_log2 = __ilog2(msize);
-	u32 i;
-
-	/* take default settings and init sequence if necessary */
-	if (mddrc_config == NULL)
-		mddrc_config = &default_mddrc_config;
-	if (dram_init_seq == NULL) {
-		dram_init_seq = default_init_seq;
-		seq_sz = ARRAY_SIZE(default_init_seq);
-	}
-
-	/* Initialize IO Control */
-	out_be32(&im->io_ctrl.io_control_mem, CONFIG_SYS_IOCTRL_MUX_DDR);
-
-	/* Initialize DDR Local Window */
-	out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
-	out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
-	sync_law(&im->sysconf.ddrlaw.ar);
-
-	/* DDR Enable */
-	/*
-	 * the "enable" combination: DRAM controller out of reset,
-	 * clock enabled, command mode -- BUT leave CKE low for now
-	 */
-	i = MDDRC_SYS_CFG_EN & ~MDDRC_SYS_CFG_CKE_MASK;
-	out_be32(&im->mddrc.ddr_sys_config, i);
-	/* maintain 200 microseconds of stable power and clock */
-	udelay(200);
-	/* apply a NOP, it shouldn't harm */
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_DDRCMD_NOP);
-	/* now assert CKE (high) */
-	i |= MDDRC_SYS_CFG_CKE_MASK;
-	out_be32(&im->mddrc.ddr_sys_config, i);
-
-	/* Initialize DDR Priority Manager */
-	out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
-	out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
-	out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
-	out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
-	out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
-	out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
-	out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
-	out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
-	out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
-	out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
-	out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
-	out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
-	out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
-	out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
-	out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
-	out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
-	out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
-	out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
-	out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
-	out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
-	out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
-	out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
-	out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
-
-	/*
-	 * Initialize MDDRC
-	 *  put MDDRC in CMD mode and
-	 *  set the max time between refreshes to 0 during init process
-	 */
-	out_be32(&im->mddrc.ddr_sys_config,
-		mddrc_config->ddr_sys_config | MDDRC_SYS_CFG_CMD_MASK);
-	out_be32(&im->mddrc.ddr_time_config0,
-		mddrc_config->ddr_time_config0 & MDDRC_REFRESH_ZERO_MASK);
-	out_be32(&im->mddrc.ddr_time_config1,
-		mddrc_config->ddr_time_config1);
-	out_be32(&im->mddrc.ddr_time_config2,
-		mddrc_config->ddr_time_config2);
-
-	/* Initialize DDR with either default or supplied init sequence */
-	for (i = 0; i < seq_sz; i++)
-		out_be32(&im->mddrc.ddr_command, dram_init_seq[i]);
-
-	/* Start MDDRC */
-	out_be32(&im->mddrc.ddr_time_config0, mddrc_config->ddr_time_config0);
-	out_be32(&im->mddrc.ddr_sys_config, mddrc_config->ddr_sys_config);
-
-	/* Allow for the DLL to startup before accessing data */
-	udelay(10);
-
-	msize = get_ram_size(CONFIG_SYS_DDR_BASE, CONFIG_SYS_MAX_RAM_SIZE);
-	/* Fix DDR Local Window for new size */
-	out_be32(&im->sysconf.ddrlaw.ar, __ilog2(msize) - 1);
-	sync_law(&im->sysconf.ddrlaw.ar);
-
-	return msize;
-}
diff --git a/arch/powerpc/cpu/mpc512x/ide.c b/arch/powerpc/cpu/mpc512x/ide.c
deleted file mode 100644
index dd1130694d..0000000000
--- a/arch/powerpc/cpu/mpc512x/ide.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * (C) Copyright 2007-2009 DENX Software Engineering
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_IDE_RESET)
-
-void ide_set_reset (int idereset)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	debug ("ide_set_reset(%d)\n", idereset);
-
-	if (idereset) {
-		out_be32(&im->pata.pata_ata_control, 0);
-	} else {
-		out_be32(&im->pata.pata_ata_control, FSL_ATA_CTRL_ATA_RST_B);
-	}
-	udelay(100);
-}
-
-void init_ide_reset (void)
-{
-	debug ("init_ide_reset\n");
-
-	/*
-	 * Clear the reset bit to reset the interface
-	 * cf. RefMan MPC5121EE: 28.4.1 Resetting the ATA Bus
-	 */
-	ide_set_reset(1);
-
-	/* Assert the reset bit to enable the interface */
-	ide_set_reset(0);
-
-}
-
-#define CALC_TIMING(t) (t + period - 1) / period
-
-int ide_preinit (void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	long t;
-	const struct {
-		short t0;
-		short t1;
-		short t2_8;
-		short t2_16;
-		short t2i;
-		short t4;
-		short t9;
-		short tA;
-	} pio_specs = {
-		.t0    = 600,
-		.t1    =  70,
-		.t2_8  = 290,
-		.t2_16 = 165,
-		.t2i   =   0,
-		.t4    =  30,
-		.t9    =  20,
-		.tA    =  50,
-	};
-	union {
-		u32 config;
-		struct {
-			u8 field1;
-			u8 field2;
-			u8 field3;
-			u8 field4;
-		}bytes;
-	} cfg;
-
-	debug ("IDE preinit using PATA peripheral at IMMR-ADDR %08x\n",
-		(u32)&im->pata);
-
-	/* Set the reset bit to 1 to enable the interface */
-	ide_set_reset(0);
-
-	/* Init timings : we use PIO mode 0 timings */
-	t = 1000000000 / gd->arch.ips_clk;	/* period in ns */
-	cfg.bytes.field1 = 3;
-	cfg.bytes.field2 = 3;
-	cfg.bytes.field3 = (pio_specs.t1 + t) / t;
-	cfg.bytes.field4 = (pio_specs.t2_8 + t) / t;
-
-	out_be32(&im->pata.pata_time1, cfg.config);
-
-	cfg.bytes.field1 = (pio_specs.t2_8 + t) / t;
-	cfg.bytes.field2 = (pio_specs.tA + t) / t + 2;
-	cfg.bytes.field3 = 1;
-	cfg.bytes.field4 = (pio_specs.t4 + t) / t;
-
-	out_be32(&im->pata.pata_time2, cfg.config);
-
-	cfg.config = in_be32(&im->pata.pata_time3);
-	cfg.bytes.field1 = (pio_specs.t9 + t) / t;
-
-	out_be32(&im->pata.pata_time3, cfg.config);
-
-	debug ("PATA preinit complete.\n");
-
-	return 0;
-}
-
-#endif /* defined(CONFIG_IDE_RESET) */
diff --git a/arch/powerpc/cpu/mpc512x/interrupts.c b/arch/powerpc/cpu/mpc512x/interrupts.c
deleted file mode 100644
index 3385aed1cc..0000000000
--- a/arch/powerpc/cpu/mpc512x/interrupts.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * (C) Copyright 2000-2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright 2004 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Derived from the MPC83xx code.
- */
-
-#include <common.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct irq_action {
-	interrupt_handler_t *handler;
-	void *arg;
-	ulong count;
-};
-
-int interrupt_init_cpu (unsigned *decrementer_count)
-{
-	*decrementer_count = get_tbclk () / CONFIG_SYS_HZ;
-
-	return 0;
-}
-
-/*
- * Install and free an interrupt handler.
- */
-void
-irq_install_handler (int irq, interrupt_handler_t * handler, void *arg)
-{
-}
-
-void irq_free_handler (int irq)
-{
-}
-
-void timer_interrupt_cpu (struct pt_regs *regs)
-{
-	/* nothing to do here */
-	return;
-}
diff --git a/arch/powerpc/cpu/mpc512x/iopin.c b/arch/powerpc/cpu/mpc512x/iopin.c
deleted file mode 100644
index 0b53c7b98e..0000000000
--- a/arch/powerpc/cpu/mpc512x/iopin.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * (C) Copyright 2008
- * Martha J Marx, Silicon Turnkey Express, mmarx@silicontkx.com
- * mpc512x I/O pin/pad initialization for the ADS5121 board
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/types.h>
-#include <asm/io.h>
-
-void iopin_initialize(iopin_t *ioregs_init, int len)
-{
-	short i, j, p;
-	u32 *reg;
-	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
-	reg = (u32 *)&(im->io_ctrl);
-
-	if (sizeof(ioregs_init) == 0)
-		return;
-
-	for (i = 0; i < len; i++) {
-		for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
-			p < ioregs_init[i].nr_pins; p++, j++) {
-			if (ioregs_init[i].bit_or)
-				setbits_be32(reg + j, ioregs_init[i].val);
-			else
-				out_be32 (reg + j, ioregs_init[i].val);
-		}
-	}
-	return;
-}
-
-void iopin_initialize_bits(iopin_t *ioregs_init, int len)
-{
-	short i, j, p;
-	u32 *reg, mask;
-	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
-	reg = (u32 *)&(im->io_ctrl);
-
-	/* iterate over table entries */
-	for (i = 0; i < len; i++) {
-		/* iterate over pins within a table entry */
-		for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
-			p < ioregs_init[i].nr_pins; p++, j++) {
-			if (ioregs_init[i].bit_or & IO_PIN_OVER_EACH) {
-				/* replace all settings at once */
-				out_be32(reg + j, ioregs_init[i].val);
-			} else {
-				/*
-				 * only replace individual parts, but
-				 * REPLACE them instead of just ORing
-				 * them in and "inheriting" previously
-				 * set bits which we don't want
-				 */
-				mask = 0;
-				if (ioregs_init[i].bit_or & IO_PIN_OVER_FMUX)
-					mask |= IO_PIN_FMUX(3);
-
-				if (ioregs_init[i].bit_or & IO_PIN_OVER_HOLD)
-					mask |= IO_PIN_HOLD(3);
-
-				if (ioregs_init[i].bit_or & IO_PIN_OVER_PULL)
-					mask |= IO_PIN_PUD(1) | IO_PIN_PUE(1);
-
-				if (ioregs_init[i].bit_or & IO_PIN_OVER_STRIG)
-					mask |= IO_PIN_ST(1);
-
-				if (ioregs_init[i].bit_or & IO_PIN_OVER_DRVSTR)
-					mask |= IO_PIN_DS(3);
-				/*
-				 * DON'T do the "mask, then insert"
-				 * in place on the register, it may
-				 * break access to external hardware
-				 * (like boot ROMs) when configuring
-				 * LPB related pins, while the code to
-				 * configure the pin is read from this
-				 * very address region
-				 */
-				clrsetbits_be32(reg + j, mask,
-						ioregs_init[i].val & mask);
-			}
-		}
-	}
-}
diff --git a/arch/powerpc/cpu/mpc512x/pci.c b/arch/powerpc/cpu/mpc512x/pci.c
deleted file mode 100644
index 7ea5df2960..0000000000
--- a/arch/powerpc/cpu/mpc512x/pci.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- * Copyright (C) 2009-2010 DENX Software Engineering <wd@denx.de>
- * Copyright (C) Freescale Semiconductor, Inc. 2006, 2007.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <asm/global_data.h>
-#include <pci.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
-
-static struct pci_controller pci_hose;
-
-
-/**************************************************************************
- * pci_init_board()
- *
- */
-void
-pci_init_board(void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile law512x_t *pci_law;
-	volatile pot512x_t *pci_pot;
-	volatile pcictrl512x_t *pci_ctrl;
-	u16 reg16;
-	u32 reg32;
-	u32 dev;
-	int i;
-	struct pci_controller *hose;
-
-	/* Set PCI divider for 33MHz */
-	reg32 = in_be32(&im->clk.scfr[0]);
-	reg32 &= ~(SCFR1_PCI_DIV_MASK);
-	reg32 |= SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT;
-	out_be32(&im->clk.scfr[0], reg32);
-
-	clrsetbits_be32(&im->clk.scfr[0],
-			SCFR1_PCI_DIV_MASK,
-			SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT
-	);
-
-	pci_law = im->sysconf.pcilaw;
-	pci_pot = im->ios.pot;
-	pci_ctrl = &im->pci_ctrl;
-
-	hose = &pci_hose;
-
-	/*
-	 * Release PCI RST Output signal
-	 */
-	out_be32(&pci_ctrl->gcr, 0);
-	udelay(2000);
-	out_be32(&pci_ctrl->gcr, 1);
-
-	/* We need to wait at least a 1sec based on PCI specs */
-	for (i = 0; i < 1000; i++)
-		udelay(1000);
-
-	/*
-	 * Configure PCI Local Access Windows
-	 */
-	out_be32(&pci_law[0].bar, CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR);
-	out_be32(&pci_law[0].ar, LAWAR_EN | LAWAR_SIZE_512M);
-
-	out_be32(&pci_law[1].bar, CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR);
-	out_be32(&pci_law[1].ar, LAWAR_EN | LAWAR_SIZE_16M);
-
-	/*
-	 * Configure PCI Outbound Translation Windows
-	 */
-
-	/* PCI mem space - prefetch */
-	out_be32(&pci_pot[0].potar,
-		(CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK);
-	out_be32(&pci_pot[0].pobar,
-		(CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK);
-	out_be32(&pci_pot[0].pocmr,
-		POCMR_EN | POCMR_PRE | POCMR_CM_256M);
-
-	/* PCI IO space */
-	out_be32(&pci_pot[1].potar,
-		(CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK);
-	out_be32(&pci_pot[1].pobar,
-		(CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK);
-	out_be32(&pci_pot[1].pocmr,
-		POCMR_EN | POCMR_IO | POCMR_CM_16M);
-
-	/* PCI mmio - non-prefetch mem space */
-	out_be32(&pci_pot[2].potar,
-		(CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK);
-	out_be32(&pci_pot[2].pobar,
-		(CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK);
-	out_be32(&pci_pot[2].pocmr,
-		POCMR_EN | POCMR_CM_256M);
-
-	/*
-	 * Configure PCI Inbound Translation Windows
-	 */
-
-	/* we need RAM mapped to PCI space for the devices to
-	 * access main memory */
-	out_be32(&pci_ctrl[0].pitar1, 0x0);
-	out_be32(&pci_ctrl[0].pibar1, 0x0);
-	out_be32(&pci_ctrl[0].piebar1, 0x0);
-	out_be32(&pci_ctrl[0].piwar1,
-		PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
-		PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1));
-
-	hose->first_busno = 0;
-	hose->last_busno = 0xff;
-
-	/* PCI memory prefetch space */
-	pci_set_region(hose->regions + 0,
-		       CONFIG_SYS_PCI_MEM_BASE,
-		       CONFIG_SYS_PCI_MEM_PHYS,
-		       CONFIG_SYS_PCI_MEM_SIZE,
-		       PCI_REGION_MEM|PCI_REGION_PREFETCH);
-
-	/* PCI memory space */
-	pci_set_region(hose->regions + 1,
-		       CONFIG_SYS_PCI_MMIO_BASE,
-		       CONFIG_SYS_PCI_MMIO_PHYS,
-		       CONFIG_SYS_PCI_MMIO_SIZE,
-		       PCI_REGION_MEM);
-
-	/* PCI IO space */
-	pci_set_region(hose->regions + 2,
-		       CONFIG_SYS_PCI_IO_BASE,
-		       CONFIG_SYS_PCI_IO_PHYS,
-		       CONFIG_SYS_PCI_IO_SIZE,
-		       PCI_REGION_IO);
-
-	/* System memory space */
-	pci_set_region(hose->regions + 3,
-		       CONFIG_PCI_SYS_MEM_BUS,
-		       CONFIG_PCI_SYS_MEM_PHYS,
-		       gd->ram_size,
-		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
-	hose->region_count = 4;
-
-	pci_setup_indirect(hose,
-			   (CONFIG_SYS_IMMR + 0x8300),
-			   (CONFIG_SYS_IMMR + 0x8304));
-
-	pci_register_hose(hose);
-
-	/*
-	 * Write to Command register
-	 */
-	reg16 = 0xff;
-	dev = PCI_BDF(hose->first_busno, 0, 0);
-	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
-	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
-
-	/*
-	 * Clear non-reserved bits in status register.
-	 */
-	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
-	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
-	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
-
-#ifdef CONFIG_PCI_SCAN_SHOW
-	printf("PCI:   Bus Dev VenId DevId Class Int\n");
-#endif
-	/*
-	 * Hose scan.
-	 */
-	hose->last_busno = pci_hose_scan(hose);
-}
-
-#if defined(CONFIG_OF_LIBFDT)
-void ft_pci_setup(void *blob, bd_t *bd)
-{
-	int nodeoffset;
-	int tmp[2];
-	const char *path;
-
-	nodeoffset = fdt_path_offset(blob, "/aliases");
-	if (nodeoffset >= 0) {
-		path = fdt_getprop(blob, nodeoffset, "pci", NULL);
-		if (path) {
-			tmp[0] = cpu_to_be32(pci_hose.first_busno);
-			tmp[1] = cpu_to_be32(pci_hose.last_busno);
-			do_fixup_by_path(blob, path, "bus-range",
-				&tmp, sizeof(tmp), 1);
-
-			tmp[0] = cpu_to_be32(gd->pci_clk);
-			do_fixup_by_path(blob, path, "clock-frequency",
-				&tmp, sizeof(tmp[0]), 1);
-		}
-	}
-}
-#endif /* CONFIG_OF_LIBFDT */
diff --git a/arch/powerpc/cpu/mpc512x/serial.c b/arch/powerpc/cpu/mpc512x/serial.c
deleted file mode 100644
index ac77ddcf4d..0000000000
--- a/arch/powerpc/cpu/mpc512x/serial.c
+++ /dev/null
@@ -1,431 +0,0 @@
-/*
- * (C) Copyright 2000 - 2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Based ont the MPC5200 PSC driver.
- * Adapted for MPC512x by Jan Wrobel <wrr@semihalf.com>
- */
-
-/*
- * Minimal serial functions needed to use one of the PSC ports
- * as serial console interface.
- */
-
-#include <common.h>
-#include <linux/compiler.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <serial.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_PSC_CONSOLE)
-
-static void fifo_init (volatile psc512x_t *psc)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 tfsize, rfsize;
-
-	/* reset Rx & Tx fifo slice */
-	out_be32(&psc->rfcmd, PSC_FIFO_RESET_SLICE);
-	out_be32(&psc->tfcmd, PSC_FIFO_RESET_SLICE);
-
-	/* disable Tx & Rx FIFO interrupts */
-	out_be32(&psc->rfintmask, 0);
-	out_be32(&psc->tfintmask, 0);
-
-	switch (((u32)psc & 0xf00) >> 8) {
-	case 0:
-		tfsize = FIFOC_PSC0_TX_SIZE | (FIFOC_PSC0_TX_ADDR << 16);
-		rfsize = FIFOC_PSC0_RX_SIZE | (FIFOC_PSC0_RX_ADDR << 16);
-		break;
-	case 1:
-		tfsize = FIFOC_PSC1_TX_SIZE | (FIFOC_PSC1_TX_ADDR << 16);
-		rfsize = FIFOC_PSC1_RX_SIZE | (FIFOC_PSC1_RX_ADDR << 16);
-		break;
-	case 2:
-		tfsize = FIFOC_PSC2_TX_SIZE | (FIFOC_PSC2_TX_ADDR << 16);
-		rfsize = FIFOC_PSC2_RX_SIZE | (FIFOC_PSC2_RX_ADDR << 16);
-		break;
-	case 3:
-		tfsize = FIFOC_PSC3_TX_SIZE | (FIFOC_PSC3_TX_ADDR << 16);
-		rfsize = FIFOC_PSC3_RX_SIZE | (FIFOC_PSC3_RX_ADDR << 16);
-		break;
-	case 4:
-		tfsize = FIFOC_PSC4_TX_SIZE | (FIFOC_PSC4_TX_ADDR << 16);
-		rfsize = FIFOC_PSC4_RX_SIZE | (FIFOC_PSC4_RX_ADDR << 16);
-		break;
-	case 5:
-		tfsize = FIFOC_PSC5_TX_SIZE | (FIFOC_PSC5_TX_ADDR << 16);
-		rfsize = FIFOC_PSC5_RX_SIZE | (FIFOC_PSC5_RX_ADDR << 16);
-		break;
-	case 6:
-		tfsize = FIFOC_PSC6_TX_SIZE | (FIFOC_PSC6_TX_ADDR << 16);
-		rfsize = FIFOC_PSC6_RX_SIZE | (FIFOC_PSC6_RX_ADDR << 16);
-		break;
-	case 7:
-		tfsize = FIFOC_PSC7_TX_SIZE | (FIFOC_PSC7_TX_ADDR << 16);
-		rfsize = FIFOC_PSC7_RX_SIZE | (FIFOC_PSC7_RX_ADDR << 16);
-		break;
-	case 8:
-		tfsize = FIFOC_PSC8_TX_SIZE | (FIFOC_PSC8_TX_ADDR << 16);
-		rfsize = FIFOC_PSC8_RX_SIZE | (FIFOC_PSC8_RX_ADDR << 16);
-		break;
-	case 9:
-		tfsize = FIFOC_PSC9_TX_SIZE | (FIFOC_PSC9_TX_ADDR << 16);
-		rfsize = FIFOC_PSC9_RX_SIZE | (FIFOC_PSC9_RX_ADDR << 16);
-		break;
-	case 10:
-		tfsize = FIFOC_PSC10_TX_SIZE | (FIFOC_PSC10_TX_ADDR << 16);
-		rfsize = FIFOC_PSC10_RX_SIZE | (FIFOC_PSC10_RX_ADDR << 16);
-		break;
-	case 11:
-		tfsize = FIFOC_PSC11_TX_SIZE | (FIFOC_PSC11_TX_ADDR << 16);
-		rfsize = FIFOC_PSC11_RX_SIZE | (FIFOC_PSC11_RX_ADDR << 16);
-		break;
-	default:
-		return;
-	}
-
-	out_be32(&psc->tfsize, tfsize);
-	out_be32(&psc->rfsize, rfsize);
-
-	/* enable Tx & Rx FIFO slice */
-	out_be32(&psc->rfcmd, PSC_FIFO_ENABLE_SLICE);
-	out_be32(&psc->tfcmd, PSC_FIFO_ENABLE_SLICE);
-
-	out_be32(&im->fifoc.fifoc_cmd, FIFOC_DISABLE_CLOCK_GATE);
-	__asm__ volatile ("sync");
-}
-
-void serial_setbrg_dev(unsigned int idx)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
-	unsigned long baseclk, div;
-	unsigned long baudrate;
-	char buf[16];
-	char *br_env;
-
-	baudrate = gd->baudrate;
-	if (idx != CONFIG_PSC_CONSOLE) {
-		/* Allows setting baudrate for other serial devices
-		 * on PSCx using environment. If not specified, use
-		 * the same baudrate as for console.
-		 */
-		sprintf(buf, "psc%d_baudrate", idx);
-		br_env = getenv(buf);
-		if (br_env)
-			baudrate = simple_strtoul(br_env, NULL, 10);
-
-		debug("%s: idx %d, baudrate %ld\n", __func__, idx, baudrate);
-	}
-
-	/* calculate divisor for setting PSC CTUR and CTLR registers */
-	baseclk = (gd->arch.ips_clk + 8) / 16;
-	div = (baseclk + (baudrate / 2)) / baudrate;
-
-	out_8(&psc->ctur, (div >> 8) & 0xff);
-	out_8(&psc->ctlr,  div & 0xff); /* set baudrate */
-}
-
-int serial_init_dev(unsigned int idx)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
-	u32 reg;
-
-	reg = in_be32(&im->clk.sccr[0]);
-	out_be32(&im->clk.sccr[0], reg | CLOCK_SCCR1_PSC_EN(idx));
-
-	fifo_init (psc);
-
-	/* set MR register to point to MR1 */
-	out_8(&psc->command, PSC_SEL_MODE_REG_1);
-
-	/* disable Tx/Rx */
-	out_8(&psc->command, PSC_TX_DISABLE | PSC_RX_DISABLE);
-
-	/* choose the prescaler	by 16 for the Tx/Rx clock generation */
-	out_be16(&psc->psc_clock_select, 0xdd00);
-
-	/* switch to UART mode */
-	out_be32(&psc->sicr, 0);
-
-	/* mode register points to mr1 */
-	/* configure parity, bit length and so on in mode register 1*/
-	out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE);
-	/* now, mode register points to mr2 */
-	out_8(&psc->mode, PSC_MODE_1_STOPBIT);
-
-	/* set baudrate */
-	serial_setbrg_dev(idx);
-
-	/* disable all interrupts */
-	out_be16(&psc->psc_imr, 0);
-
-	/* reset and enable Rx/Tx */
-	out_8(&psc->command, PSC_RST_RX);
-	out_8(&psc->command, PSC_RST_TX);
-	out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE);
-
-	return 0;
-}
-
-int serial_uninit_dev(unsigned int idx)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
-	u32 reg;
-
-	out_8(&psc->command, PSC_RX_DISABLE | PSC_TX_DISABLE);
-	reg = in_be32(&im->clk.sccr[0]);
-	reg &= ~CLOCK_SCCR1_PSC_EN(idx);
-	out_be32(&im->clk.sccr[0], reg);
-
-	return 0;
-}
-
-void serial_putc_dev(unsigned int idx, const char c)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
-
-	if (c == '\n')
-		serial_putc_dev(idx, '\r');
-
-	/* Wait for last character to go. */
-	while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
-		;
-
-	out_8(&psc->tfdata_8, c);
-}
-
-void serial_puts_dev(unsigned int idx, const char *s)
-{
-	while (*s)
-		serial_putc_dev(idx, *s++);
-}
-
-int serial_getc_dev(unsigned int idx)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
-
-	/* Wait for a character to arrive. */
-	while (in_be32(&psc->rfstat) & PSC_FIFO_EMPTY)
-		;
-
-	return in_8(&psc->rfdata_8);
-}
-
-int serial_tstc_dev(unsigned int idx)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
-
-	return !(in_be32(&psc->rfstat) & PSC_FIFO_EMPTY);
-}
-
-void serial_setrts_dev(unsigned int idx, int s)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
-
-	if (s) {
-		/* Assert RTS (become LOW) */
-		out_8(&psc->op1, 0x1);
-	}
-	else {
-		/* Negate RTS (become HIGH) */
-		out_8(&psc->op0, 0x1);
-	}
-}
-
-int serial_getcts_dev(unsigned int idx)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
-
-	return (in_8(&psc->ip) & 0x1) ? 0 : 1;
-}
-#endif /* CONFIG_PSC_CONSOLE */
-
-#define DECLARE_PSC_SERIAL_FUNCTIONS(port) \
-	int serial##port##_init(void) \
-	{ \
-		return serial_init_dev(port); \
-	} \
-	int serial##port##_uninit(void) \
-	{ \
-		return serial_uninit_dev(port); \
-	} \
-	void serial##port##_setbrg(void) \
-	{ \
-		serial_setbrg_dev(port); \
-	} \
-	int serial##port##_getc(void) \
-	{ \
-		return serial_getc_dev(port); \
-	} \
-	int serial##port##_tstc(void) \
-	{ \
-		return serial_tstc_dev(port); \
-	} \
-	void serial##port##_putc(const char c) \
-	{ \
-		serial_putc_dev(port, c); \
-	} \
-	void serial##port##_puts(const char *s) \
-	{ \
-		serial_puts_dev(port, s); \
-	}
-
-#define INIT_PSC_SERIAL_STRUCTURE(port, __name) {	\
-	.name	= __name,				\
-	.start	= serial##port##_init,			\
-	.stop	= serial##port##_uninit,		\
-	.setbrg	= serial##port##_setbrg,		\
-	.getc	= serial##port##_getc,			\
-	.tstc	= serial##port##_tstc,			\
-	.putc	= serial##port##_putc,			\
-	.puts	= serial##port##_puts,			\
-}
-
-#if defined(CONFIG_SYS_PSC1)
-DECLARE_PSC_SERIAL_FUNCTIONS(1);
-struct serial_device serial1_device =
-INIT_PSC_SERIAL_STRUCTURE(1, "psc1");
-#endif
-
-#if defined(CONFIG_SYS_PSC3)
-DECLARE_PSC_SERIAL_FUNCTIONS(3);
-struct serial_device serial3_device =
-INIT_PSC_SERIAL_STRUCTURE(3, "psc3");
-#endif
-
-#if defined(CONFIG_SYS_PSC4)
-DECLARE_PSC_SERIAL_FUNCTIONS(4);
-struct serial_device serial4_device =
-INIT_PSC_SERIAL_STRUCTURE(4, "psc4");
-#endif
-
-#if defined(CONFIG_SYS_PSC6)
-DECLARE_PSC_SERIAL_FUNCTIONS(6);
-struct serial_device serial6_device =
-INIT_PSC_SERIAL_STRUCTURE(6, "psc6");
-#endif
-
-__weak struct serial_device *default_serial_console(void)
-{
-#if (CONFIG_PSC_CONSOLE == 3)
-	return &serial3_device;
-#elif (CONFIG_PSC_CONSOLE == 6)
-	return &serial6_device;
-#else
-#error "invalid CONFIG_PSC_CONSOLE"
-#endif
-}
-
-void mpc512x_serial_initialize(void)
-{
-#if defined(CONFIG_SYS_PSC1)
-	serial_register(&serial1_device);
-#endif
-#if defined(CONFIG_SYS_PSC3)
-	serial_register(&serial3_device);
-#endif
-#if defined(CONFIG_SYS_PSC4)
-	serial_register(&serial4_device);
-#endif
-#if defined(CONFIG_SYS_PSC6)
-	serial_register(&serial6_device);
-#endif
-}
-
-#include <stdio_dev.h>
-/*
- * Routines for communication with serial devices over PSC
- */
-/* Bitfield for initialized PSCs */
-static unsigned int initialized;
-
-struct stdio_dev *open_port(int num, int baudrate)
-{
-	struct stdio_dev *port;
-	char env_var[16];
-	char env_val[10];
-	char name[7];
-
-	if (num < 0 || num > 11)
-		return NULL;
-
-	sprintf(name, "psc%d", num);
-	port = stdio_get_by_name(name);
-	if (!port)
-		return NULL;
-
-	if (!test_bit(num, &initialized)) {
-		sprintf(env_var, "psc%d_baudrate", num);
-		sprintf(env_val, "%d", baudrate);
-		setenv(env_var, env_val);
-
-		if (port->start(port))
-			return NULL;
-
-		set_bit(num, &initialized);
-	}
-
-	return port;
-}
-
-int close_port(int num)
-{
-	struct stdio_dev *port;
-	int ret;
-	char name[7];
-
-	if (num < 0 || num > 11)
-		return -1;
-
-	sprintf(name, "psc%d", num);
-	port = stdio_get_by_name(name);
-	if (!port)
-		return -1;
-
-	ret = port->stop(port);
-	clear_bit(num, &initialized);
-
-	return ret;
-}
-
-int write_port(struct stdio_dev *port, char *buf)
-{
-	if (!port || !buf)
-		return -1;
-
-	port->puts(port, buf);
-
-	return 0;
-}
-
-int read_port(struct stdio_dev *port, char *buf, int size)
-{
-	int cnt = 0;
-
-	if (!port || !buf)
-		return -1;
-
-	if (!size)
-		return 0;
-
-	while (port->tstc(port)) {
-		buf[cnt++] = port->getc(port);
-		if (cnt > size)
-			break;
-	}
-
-	return cnt;
-}
diff --git a/arch/powerpc/cpu/mpc512x/speed.c b/arch/powerpc/cpu/mpc512x/speed.c
deleted file mode 100644
index 95069cad84..0000000000
--- a/arch/powerpc/cpu/mpc512x/speed.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * (C) Copyright 2000-2009
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Based on the MPC83xx code.
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int spmf_mult[] = {
-	68, 1, 12, 16,
-	20, 24, 28, 32,
-	36, 40, 44, 48,
-	52, 56, 60, 64
-};
-
-static int cpmf_mult[][2] = {
-	{0, 1}, {0, 1}, /* 0 and 1 are not valid */
-	{1, 1}, {3, 2},
-	{2, 1}, {5, 2},
-	{3, 1}, {7, 2},
-	{0, 1}, {0, 1}, /* and all above 7 are not valid too */
-	{0, 1}, {0, 1},
-	{0, 1}, {0, 1},
-	{0, 1}, {0, 1}
-};
-
-static int sys_dividors[][2] = {
-	{2, 1}, {5, 2}, {3, 1}, {7, 2}, {4, 1},
-	{9, 2}, {5, 1}, {7, 1}, {6, 1}, {8, 1},
-	{9, 1}, {11, 1}, {10, 1}, {12, 1}, {13, 1},
-	{15, 1}, {14, 1}, {16, 1}, {17, 1}, {19, 1},
-	{18, 1}, {20, 1}, {21, 1}, {23, 1}, {22, 1},
-	{24, 1}, {25, 1}, {27, 1}, {26, 1}, {28, 1},
-	{29, 1}, {31, 1}, {30, 1}, {32, 1}, {33, 1}
-};
-
-int get_clocks (void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u8 spmf;
-	u8 cpmf;
-	u8 sys_div;
-	u8 ips_div;
-	u8 pci_div;
-	u32 ref_clk = CONFIG_SYS_MPC512X_CLKIN;
-	u32 spll;
-	u32 sys_clk;
-	u32 core_clk;
-	u32 csb_clk;
-	u32 ips_clk;
-	u32 pci_clk;
-	u32 reg;
-
-	reg = in_be32(&im->sysconf.immrbar);
-	if ((reg & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
-
-	reg = in_be32(&im->clk.spmr);
-	spmf = (reg & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
-	spll = ref_clk * spmf_mult[spmf];
-
-	reg = in_be32(&im->clk.scfr[1]);
-	sys_div = (reg & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT;
-	sys_clk = (spll * sys_dividors[sys_div][1]) / sys_dividors[sys_div][0];
-
-	csb_clk = sys_clk / 2;
-
-	reg = in_be32(&im->clk.spmr);
-	cpmf = (reg & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
-	core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1];
-
-	reg = in_be32(&im->clk.scfr[0]);
-	ips_div = (reg & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT;
-	if (ips_div != 0) {
-		ips_clk = csb_clk / ips_div;
-	} else {
-		/* in case we cannot get a sane IPS divisor, fail gracefully */
-		ips_clk = 0;
-	}
-
-	reg = in_be32(&im->clk.scfr[0]);
-	pci_div = (reg & SCFR1_PCI_DIV_MASK) >> SCFR1_PCI_DIV_SHIFT;
-	if (pci_div != 0) {
-		pci_clk = csb_clk / pci_div;
-	} else {
-		/* in case we cannot get a sane IPS divisor, fail gracefully */
-		pci_clk = 333333;
-	}
-
-	gd->arch.ips_clk = ips_clk;
-	gd->pci_clk = pci_clk;
-	gd->arch.csb_clk = csb_clk;
-	gd->cpu_clk = core_clk;
-	gd->bus_clk = csb_clk;
-	return 0;
-
-}
-
-/********************************************
- * get_bus_freq
- * return system bus freq in Hz
- *********************************************/
-ulong get_bus_freq (ulong dummy)
-{
-	return gd->arch.csb_clk;
-}
-
-int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
-	char buf[32];
-
-	printf("Clock configuration:\n");
-	printf("  CPU:                 %-4s MHz\n", strmhz(buf, gd->cpu_clk));
-	printf("  Coherent System Bus: %-4s MHz\n",
-	       strmhz(buf, gd->arch.csb_clk));
-	printf("  IPS Bus:             %-4s MHz\n",
-	       strmhz(buf, gd->arch.ips_clk));
-	printf("  PCI:                 %-4s MHz\n", strmhz(buf, gd->pci_clk));
-	printf("  DDR:                 %-4s MHz\n",
-	       strmhz(buf, 2 * gd->arch.csb_clk));
-	return 0;
-}
-
-U_BOOT_CMD(clocks, 1, 0, do_clocks,
-	"print clock configuration",
-	"    clocks"
-);
diff --git a/arch/powerpc/cpu/mpc512x/start.S b/arch/powerpc/cpu/mpc512x/start.S
deleted file mode 100644
index dd3066ec4c..0000000000
--- a/arch/powerpc/cpu/mpc512x/start.S
+++ /dev/null
@@ -1,694 +0,0 @@
-/*
- * Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
- * Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
- * Copyright (C) 2000-2009 Wolfgang Denk <wd@denx.de>
- * Copyright Freescale Semiconductor, Inc. 2004, 2006.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Based on the MPC83xx code.
- */
-
-/*
- *  U-Boot - Startup Code for MPC512x based Embedded Boards
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-
-#define CONFIG_521X	1		/* needed for Linux kernel header files*/
-
-#include <asm/immap_512x.h>
-#include "asm-offsets.h"
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <asm/u-boot.h>
-
-/*
- * Floating Point enable, Machine Check and Recoverable Interr.
- */
-#undef	MSR_KERNEL
-#ifdef DEBUG
-#define MSR_KERNEL (MSR_FP|MSR_RI)
-#else
-#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
-#endif
-
-/* Macros for manipulating CSx_START/STOP */
-#define START_REG(start)	((start) >> 16)
-#define STOP_REG(start, size)	(((start) + (size) - 1) >> 16)
-
-/*
- * Set up GOT: Global Offset Table
- *
- * Use r12 to access the GOT
- */
-	START_GOT
-	GOT_ENTRY(_GOT2_TABLE_)
-	GOT_ENTRY(_FIXUP_TABLE_)
-
-	GOT_ENTRY(_start)
-	GOT_ENTRY(_start_of_vectors)
-	GOT_ENTRY(_end_of_vectors)
-	GOT_ENTRY(transfer_to_handler)
-
-	GOT_ENTRY(__init_end)
-	GOT_ENTRY(__bss_end)
-	GOT_ENTRY(__bss_start)
-	END_GOT
-
-/*
- * Magic number and version string
- */
-	.long	0x27051956		/* U-Boot Magic Number */
-	.globl	version_string
-version_string:
-	.ascii U_BOOT_VERSION_STRING, "\0"
-
-/*
- * Vector Table
- */
-	.text
-	. = EXC_OFF_SYS_RESET
-
-	.globl	_start
-	/* Start from here after reset/power on */
-_start:
-	b	boot_cold
-
-	.globl	_start_of_vectors
-_start_of_vectors:
-
-/* Machine check */
-	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
-
-/* Data Storage exception. */
-	STD_EXCEPTION(0x300, DataStorage, UnknownException)
-
-/* Instruction Storage exception. */
-	STD_EXCEPTION(0x400, InstStorage, UnknownException)
-
-/* External Interrupt exception. */
-	STD_EXCEPTION(0x500, ExtInterrupt, UnknownException)
-
-/* Alignment exception. */
-	. = 0x600
-Alignment:
-	EXCEPTION_PROLOG(SRR0, SRR1)
-	mfspr	r4,DAR
-	stw	r4,_DAR(r21)
-	mfspr	r5,DSISR
-	stw	r5,_DSISR(r21)
-	addi	r3,r1,STACK_FRAME_OVERHEAD
-	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
-
-/* Program check exception */
-	. = 0x700
-ProgramCheck:
-	EXCEPTION_PROLOG(SRR0, SRR1)
-	addi	r3,r1,STACK_FRAME_OVERHEAD
-	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
-		MSR_KERNEL, COPY_EE)
-
-/* Floating Point Unit unavailable exception */
-	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
-
-/* Decrementer */
-	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
-
-/* Critical interrupt */
-	STD_EXCEPTION(0xa00, Critical, UnknownException)
-
-/* System Call */
-	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
-
-/* Trace interrupt */
-	STD_EXCEPTION(0xd00, Trace, UnknownException)
-
-/* Performance Monitor interrupt */
-	STD_EXCEPTION(0xf00, PerfMon, UnknownException)
-
-/* Intruction Translation Miss */
-	STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
-
-/* Data Load Translation Miss */
-	STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
-
-/* Data Store Translation Miss */
-	STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
-
-/* Instruction Address Breakpoint */
-	STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException)
-
-/* System Management interrupt */
-	STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException)
-
-	.globl	_end_of_vectors
-_end_of_vectors:
-
-	. = 0x3000
-boot_cold:
-	/* Save msr contents */
-	mfmsr	r5
-
-	/* Set IMMR area to our preferred location */
-	lis	r4, CONFIG_DEFAULT_IMMR@h
-	lis	r3, CONFIG_SYS_IMMR@h
-	ori	r3, r3, CONFIG_SYS_IMMR@l
-	stw	r3, IMMRBAR(r4)
-	mtspr	MBAR, r3		/* IMMRBAR is mirrored into the MBAR SPR (311) */
-
-	/* Initialise the machine */
-	bl	cpu_early_init
-
-	/*
-	 * Set up Local Access Windows:
-	 *
-	 * 1) Boot/CS0 (boot FLASH)
-	 * 2) On-chip SRAM (initial stack purposes)
-	 */
-
-	/* Boot CS/CS0 window range */
-	lis     r3, CONFIG_SYS_IMMR@h
-	ori     r3, r3, CONFIG_SYS_IMMR@l
-
-	lis	r4, START_REG(CONFIG_SYS_FLASH_BASE)
-	ori	r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)
-	stw	r4, LPCS0AW(r3)
-
-	/*
-	 * The SRAM window has a fixed size (256K), so only the start address
-	 * is necessary
-	 */
-	lis	r4, START_REG(CONFIG_SYS_SRAM_BASE) & 0xff00
-	stw	r4, SRAMBAR(r3)
-
-	/*
-	 * According to MPC5121e RM, configuring local access windows should
-	 * be followed by a dummy read of the config register that was
-	 * modified last and an isync
-	 */
-	lwz	r4, SRAMBAR(r3)
-	isync
-
-	/*
-	 * Set configuration of the Boot/CS0, the SRAM window does not have a
-	 * config register so no params can be set for it
-	 */
-	lis     r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h
-	ori     r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l
-
-	lis     r4, CONFIG_SYS_CS0_CFG@h
-	ori     r4, r4, CONFIG_SYS_CS0_CFG@l
-	stw     r4, CS0_CONFIG(r3)
-
-	/* Master enable all CS's */
-	lis	r4, CS_CTRL_ME@h
-	ori	r4, r4, CS_CTRL_ME@l
-	stw	r4, CS_CTRL(r3)
-
-	lis	r4, (CONFIG_SYS_MONITOR_BASE)@h
-	ori	r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
-	addi	r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
-	mtlr	r5
-	blr
-
-in_flash:
-	lis	r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
-	ori	r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
-
-	li	r0, 0		/* Make room for stack frame header and	*/
-	stwu	r0, -4(r1)	/* clear final stack frame so that	*/
-	stwu	r0, -4(r1)	/* stack backtraces terminate cleanly	*/
-
-	/* let the C-code set up the rest			*/
-	/*							*/
-	/* Be careful to keep code relocatable & stack humble	*/
-	/*------------------------------------------------------*/
-
-	GET_GOT			/* initialize GOT access	*/
-
-	/* r3: IMMR */
-	lis	r3, CONFIG_SYS_IMMR@h
-	/* run low-level CPU init code (in Flash) */
-	bl	cpu_init_f
-
-	/* run 1st part of board init code (in Flash) */
-	bl	board_init_f
-
-	/* NOTREACHED - board_init_f() does not return */
-
-/*
- * This code finishes saving the registers to the exception frame
- * and jumps to the appropriate handler for the exception.
- * Register r21 is pointer into trap frame, r1 has new stack pointer.
- */
-	.globl	transfer_to_handler
-transfer_to_handler:
-	stw	r22,_NIP(r21)
-	lis	r22,MSR_POW@h
-	andc	r23,r23,r22
-	stw	r23,_MSR(r21)
-	SAVE_GPR(7, r21)
-	SAVE_4GPRS(8, r21)
-	SAVE_8GPRS(12, r21)
-	SAVE_8GPRS(24, r21)
-	mflr	r23
-	andi.	r24,r23,0x3f00		/* get vector offset */
-	stw	r24,TRAP(r21)
-	li	r22,0
-	stw	r22,RESULT(r21)
-	lwz	r24,0(r23)		/* virtual address of handler */
-	lwz	r23,4(r23)		/* where to go when done */
-	mtspr	SRR0,r24
-	mtspr	SRR1,r20
-	mtlr	r23
-	SYNC
-	rfi				/* jump to handler, enable MMU */
-
-int_return:
-	mfmsr	r28		/* Disable interrupts */
-	li	r4,0
-	ori	r4,r4,MSR_EE
-	andc	r28,r28,r4
-	SYNC			/* Some chip revs need this... */
-	mtmsr	r28
-	SYNC
-	lwz	r2,_CTR(r1)
-	lwz	r0,_LINK(r1)
-	mtctr	r2
-	mtlr	r0
-	lwz	r2,_XER(r1)
-	lwz	r0,_CCR(r1)
-	mtspr	XER,r2
-	mtcrf	0xFF,r0
-	REST_10GPRS(3, r1)
-	REST_10GPRS(13, r1)
-	REST_8GPRS(23, r1)
-	REST_GPR(31, r1)
-	lwz	r2,_NIP(r1)	/* Restore environment */
-	lwz	r0,_MSR(r1)
-	mtspr	SRR0,r2
-	mtspr	SRR1,r0
-	lwz	r0,GPR0(r1)
-	lwz	r2,GPR2(r1)
-	lwz	r1,GPR1(r1)
-	SYNC
-	rfi
-
-/*
- * This code initialises the machine, it expects original MSR contents to be in r5.
- */
-cpu_early_init:
-	/* Initialize machine status; enable machine check interrupt */
-	/*-----------------------------------------------------------*/
-
-	li	r3, MSR_KERNEL			/* Set ME and RI flags */
-	rlwimi	r3, r5, 0, 25, 25		/* preserve IP bit */
-#ifdef DEBUG
-	rlwimi	r3, r5, 0, 21, 22		/* debugger might set SE, BE bits */
-#endif
-	mtmsr	r3
-	SYNC
-	mtspr	SRR1, r3			/* Mirror current MSR state in SRR1 */
-
-	lis	r3, CONFIG_SYS_IMMR@h
-
-#if defined(CONFIG_WATCHDOG)
-	/* Initialise the watchdog and reset it */
-	/*--------------------------------------*/
-	lis r4, CONFIG_SYS_WATCHDOG_VALUE
-	ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
-	stw r4, SWCRR(r3)
-
-	/* reset */
-	li	r4, 0x556C
-	sth	r4, SWSRR@l(r3)
-	li	r4, 0x0
-	ori	r4, r4, 0xAA39
-	sth	r4, SWSRR@l(r3)
-#else
-	/* Disable the watchdog */
-	/*----------------------*/
-	lwz r4, SWCRR(r3)
-	/*
-	 * Check to see if it's enabled for disabling: once disabled by s/w
-	 * it's not possible to re-enable it
-	 */
-	andi. r4, r4, 0x4
-	beq 1f
-	xor r4, r4, r4
-	stw r4, SWCRR(r3)
-1:
-#endif /* CONFIG_WATCHDOG */
-
-	/* Initialize the Hardware Implementation-dependent Registers */
-	/* HID0 also contains cache control			*/
-	/*------------------------------------------------------*/
-	lis	r3, CONFIG_SYS_HID0_INIT@h
-	ori	r3, r3, CONFIG_SYS_HID0_INIT@l
-	SYNC
-	mtspr	HID0, r3
-
-	lis	r3, CONFIG_SYS_HID0_FINAL@h
-	ori	r3, r3, CONFIG_SYS_HID0_FINAL@l
-	SYNC
-	mtspr	HID0, r3
-
-	lis	r3, CONFIG_SYS_HID2@h
-	ori	r3, r3, CONFIG_SYS_HID2@l
-	SYNC
-	mtspr	HID2, r3
-	sync
-	blr
-
-
-/* Cache functions.
- *
- * Note: requires that all cache bits in
- * HID0 are in the low half word.
- */
-	.globl	icache_enable
-icache_enable:
-	mfspr	r3, HID0
-	ori	r3, r3, HID0_ICE
-	lis	r4, 0
-	ori	r4, r4, HID0_ILOCK
-	andc	r3, r3, r4
-	ori	r4, r3, HID0_ICFI
-	isync
-	mtspr	HID0, r4    /* sets enable and invalidate, clears lock */
-	isync
-	mtspr	HID0, r3	/* clears invalidate */
-	blr
-
-	.globl	icache_disable
-icache_disable:
-	mfspr	r3, HID0
-	lis	r4, 0
-	ori	r4, r4, HID0_ICE|HID0_ILOCK
-	andc	r3, r3, r4
-	ori	r4, r3, HID0_ICFI
-	isync
-	mtspr	HID0, r4     /* sets invalidate, clears enable and lock*/
-	isync
-	mtspr	HID0, r3	/* clears invalidate */
-	blr
-
-	.globl	icache_status
-icache_status:
-	mfspr	r3, HID0
-	rlwinm	r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
-	blr
-
-	.globl	dcache_enable
-dcache_enable:
-	mfspr	r3, HID0
-	li	r5, HID0_DCFI|HID0_DLOCK
-	andc	r3, r3, r5
-	mtspr	HID0, r3		/* no invalidate, unlock */
-	ori	r3, r3, HID0_DCE
-	ori	r5, r3, HID0_DCFI
-	mtspr	HID0, r5		/* enable + invalidate */
-	mtspr	HID0, r3		/* enable */
-	sync
-	blr
-
-	.globl	dcache_disable
-dcache_disable:
-	mfspr	r3, HID0
-	lis	r4, 0
-	ori	r4, r4, HID0_DCE|HID0_DLOCK
-	andc	r3, r3, r4
-	ori	r4, r3, HID0_DCI
-	sync
-	mtspr	HID0, r4	/* sets invalidate, clears enable and lock */
-	sync
-	mtspr	HID0, r3	/* clears invalidate */
-	blr
-
-	.globl	dcache_status
-dcache_status:
-	mfspr	r3, HID0
-	rlwinm	r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
-	blr
-
-	.globl get_pvr
-get_pvr:
-	mfspr	r3, PVR
-	blr
-
-	.globl get_svr
-get_svr:
-	mfspr	r3, SVR
-	blr
-
-/*-------------------------------------------------------------------*/
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- * r3 = dest
- * r4 = src
- * r5 = length in bytes
- * r6 = cachelinesize
- */
-	.globl	relocate_code
-relocate_code:
-	mr	r1,  r3		/* Set new stack pointer	*/
-	mr	r9,  r4		/* Save copy of Global Data pointer */
-	mr	r10, r5		/* Save copy of Destination Address */
-
-	GET_GOT
-	mr	r3,  r5				/* Destination Address */
-	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address */
-	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
-	lwz	r5, GOT(__init_end)
-	sub	r5, r5, r4
-	li	r6, CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size */
-
-	/*
-	 * Fix GOT pointer:
-	 *
-	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
-	 *		+ Destination Address
-	 *
-	 * Offset:
-	 */
-	sub	r15, r10, r4
-
-	/* First our own GOT */
-	add	r12, r12, r15
-	/* then the one used by the C code */
-	add	r30, r30, r15
-
-	/*
-	 * Now relocate code
-	 */
-	cmplw	cr1,r3,r4
-	addi	r0,r5,3
-	srwi.	r0,r0,2
-	beq	cr1,4f		/* In place copy is not necessary */
-	beq	7f		/* Protect against 0 count	  */
-	mtctr	r0
-	bge	cr1,2f
-	la	r8,-4(r4)
-	la	r7,-4(r3)
-
-	/* copy */
-1:	lwzu	r0,4(r8)
-	stwu	r0,4(r7)
-	bdnz	1b
-
-	addi	r0,r5,3
-	srwi.	r0,r0,2
-	mtctr	r0
-	la	r8,-4(r4)
-	la	r7,-4(r3)
-
-	/* and compare */
-20:	lwzu	r20,4(r8)
-	lwzu	r21,4(r7)
-	xor. r22, r20, r21
-	bne  30f
-	bdnz	20b
-	b 4f
-
-	/* compare failed */
-30:	li r3, 0
-	blr
-
-2:	slwi	r0,r0,2 /* re copy in reverse order ... y do we needed it? */
-	add	r8,r4,r0
-	add	r7,r3,r0
-3:	lwzu	r0,-4(r8)
-	stwu	r0,-4(r7)
-	bdnz	3b
-
-/*
- * Now flush the cache: note that we must start from a cache aligned
- * address. Otherwise we might miss one cache line.
- */
-4:	cmpwi	r6,0
-	add	r5,r3,r5
-	beq	7f		/* Always flush prefetch queue in any case */
-	subi	r0,r6,1
-	andc	r3,r3,r0
-	mr	r4,r3
-5:	dcbst	0,r4
-	add	r4,r4,r6
-	cmplw	r4,r5
-	blt	5b
-	sync			/* Wait for all dcbst to complete on bus */
-	mr	r4,r3
-6:	icbi	0,r4
-	add	r4,r4,r6
-	cmplw	r4,r5
-	blt	6b
-7:	sync			/* Wait for all icbi to complete on bus	*/
-	isync
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
-	mtlr	r0
-	blr
-
-in_ram:
-	/*
-	 * Relocation Function, r12 point to got2+0x8000
-	 *
-	 * Adjust got2 pointers, no need to check for 0, this code
-	 * already puts a few entries in the table.
-	 */
-	li	r0,__got2_entries@sectoff@l
-	la	r3,GOT(_GOT2_TABLE_)
-	lwz	r11,GOT(_GOT2_TABLE_)
-	mtctr	r0
-	sub	r11,r3,r11
-	addi	r3,r3,-4
-1:	lwzu	r0,4(r3)
-	cmpwi	r0,0
-	beq-	2f
-	add	r0,r0,r11
-	stw	r0,0(r3)
-2:	bdnz	1b
-
-	/*
-	 * Now adjust the fixups and the pointers to the fixups
-	 * in case we need to move ourselves again.
-	 */
-	li	r0,__fixup_entries@sectoff@l
-	lwz	r3,GOT(_FIXUP_TABLE_)
-	cmpwi	r0,0
-	mtctr	r0
-	addi	r3,r3,-4
-	beq	4f
-3:	lwzu	r4,4(r3)
-	lwzux	r0,r4,r11
-	cmpwi	r0,0
-	add	r0,r0,r11
-	stw	r4,0(r3)
-	beq-	5f
-	stw	r0,0(r4)
-5:	bdnz	3b
-4:
-clear_bss:
-	/*
-	 * Now clear BSS segment
-	 */
-	lwz	r3,GOT(__bss_start)
-	lwz	r4,GOT(__bss_end)
-
-	cmplw	0, r3, r4
-	beq	6f
-
-	li	r0, 0
-5:
-	stw	r0, 0(r3)
-	addi	r3, r3, 4
-	cmplw	0, r3, r4
-	bne	5b
-6:
-	mr	r3, r9		/* Global Data pointer		*/
-	mr	r4, r10		/* Destination Address		*/
-	bl	board_init_r
-
-	/*
-	 * Copy exception vector code to low memory
-	 *
-	 * r3: dest_addr
-	 * r7: source address, r8: end address, r9: target address
-	 */
-	.globl	trap_init
-trap_init:
-	mflr	r4		/* save link register */
-	GET_GOT
-	lwz	r7, GOT(_start)
-	lwz	r8, GOT(_end_of_vectors)
-
-	li	r9, 0x100	/* reset vector at 0x100 */
-
-	cmplw	0, r7, r8
-	bgelr			/* return if r7>=r8 - just in case */
-1:
-	lwz	r0, 0(r7)
-	stw	r0, 0(r9)
-	addi	r7, r7, 4
-	addi	r9, r9, 4
-	cmplw	0, r7, r8
-	bne	1b
-
-	/*
-	 * relocate `hdlr' and `int_return' entries
-	 */
-	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
-	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
-2:
-	bl	trap_reloc
-	addi	r7, r7, 0x100		/* next exception vector */
-	cmplw	0, r7, r8
-	blt	2b
-
-	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
-	bl	trap_reloc
-
-	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
-	bl	trap_reloc
-
-	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
-	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
-3:
-	bl	trap_reloc
-	addi	r7, r7, 0x100		/* next exception vector */
-	cmplw	0, r7, r8
-	blt	3b
-
-	li	r7, .L_Trace - _start + EXC_OFF_SYS_RESET
-	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
-4:
-	bl	trap_reloc
-	addi	r7, r7, 0x100		/* next exception vector */
-	cmplw	0, r7, r8
-	blt	4b
-
-	mfmsr	r3			/* now that the vectors have */
-	lis	r7, MSR_IP@h		/* relocated into low memory */
-	ori	r7, r7, MSR_IP@l	/* MSR[IP] can be turned off */
-	andc	r3, r3, r7		/* (if it was on) */
-	SYNC				/* Some chip revs need this... */
-	mtmsr	r3
-	SYNC
-
-	mtlr	r4			/* restore link register    */
-	blr
diff --git a/arch/powerpc/cpu/mpc512x/traps.c b/arch/powerpc/cpu/mpc512x/traps.c
deleted file mode 100644
index 9f5bcd7fc3..0000000000
--- a/arch/powerpc/cpu/mpc512x/traps.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * (C) Copyright 2000 - 2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Derived from the MPC83xx code.
- */
-
-/*
- * This file handles the architecture-dependent parts of hardware
- * exceptions
- */
-
-#include <common.h>
-#include <kgdb.h>
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern unsigned long search_exception_table(unsigned long);
-
-/*
- * End of addressable memory.  This may be less than the actual
- * amount of memory on the system if we're unable to keep all
- * the memory mapped in.
- */
-#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize())
-
-/*
- * Trap & Exception support
- */
-
-static void print_backtrace(unsigned long *sp)
-{
-	int cnt = 0;
-	unsigned long i;
-
-	puts("Call backtrace: ");
-	while (sp) {
-		if ((uint)sp > END_OF_MEM)
-			break;
-
-		i = sp[1];
-		if (cnt++ % 7 == 0)
-			putc('\n');
-		printf("%08lX ", i);
-		if (cnt > 32) break;
-		sp = (unsigned long *) *sp;
-	}
-	putc('\n');
-}
-
-void show_regs(struct pt_regs *regs)
-{
-	int i;
-
-	printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
-	       regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
-	printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
-	       regs->msr, regs->msr & MSR_EE ? 1 : 0, regs->msr & MSR_PR ? 1 : 0,
-	       regs->msr & MSR_FP ? 1 : 0,regs->msr & MSR_ME ? 1 : 0,
-	       regs->msr & MSR_IR ? 1 : 0,
-	       regs->msr & MSR_DR ? 1 : 0);
-
-	putc('\n');
-	for (i = 0;  i < 32;  i++) {
-		if ((i % 8) == 0) {
-			printf("GPR%02d: ", i);
-		}
-
-		printf("%08lX ", regs->gpr[i]);
-		if ((i % 8) == 7) {
-			putc('\n');
-		}
-	}
-}
-
-
-static void _exception(int signr, struct pt_regs *regs)
-{
-	show_regs(regs);
-	print_backtrace((unsigned long *)regs->gpr[1]);
-	panic("Exception at pc %lx signal %d", regs->nip, signr);
-}
-
-
-void MachineCheckException(struct pt_regs *regs)
-{
-	unsigned long fixup = search_exception_table(regs->nip);
-
-	if (fixup) {
-		regs->nip = fixup;
-		return;
-	}
-
-#ifdef CONFIG_CMD_KGDB
-	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
-		return;
-#endif
-
-	puts("Machine check.\nCaused by (from msr): ");
-	printf("regs %p ", regs);
-	switch (regs->msr & 0x00FF0000) {
-	case (0x80000000 >> 10):
-		puts("Instruction cache parity signal\n");
-		break;
-	case (0x80000000 >> 11):
-		puts("Data cache parity signal\n");
-		break;
-	case (0x80000000 >> 12):
-		puts("Machine check signal\n");
-		break;
-	case (0x80000000 >> 13):
-		puts("Transfer error ack signal\n");
-		break;
-	case (0x80000000 >> 14):
-		puts("Data parity signal\n");
-		break;
-	case (0x80000000 >> 15):
-		puts("Address parity signal\n");
-		break;
-	default:
-		puts("Unknown values in msr\n");
-	}
-	show_regs(regs);
-	print_backtrace((unsigned long *)regs->gpr[1]);
-
-	panic("machine check");
-}
-
-void AlignmentException(struct pt_regs *regs)
-{
-#ifdef CONFIG_CMD_KGDB
-	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
-		return;
-#endif
-	show_regs(regs);
-	print_backtrace((unsigned long *)regs->gpr[1]);
-	panic("Alignment Exception");
-}
-
-void ProgramCheckException(struct pt_regs *regs)
-{
-#ifdef CONFIG_CMD_KGDB
-	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
-		return;
-#endif
-	show_regs(regs);
-	print_backtrace((unsigned long *)regs->gpr[1]);
-	panic("Program Check Exception");
-}
-
-void SoftEmuException(struct pt_regs *regs)
-{
-#ifdef CONFIG_CMD_KGDB
-	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
-		return;
-#endif
-	show_regs(regs);
-	print_backtrace((unsigned long *)regs->gpr[1]);
-	panic("Software Emulation Exception");
-}
-
-
-void UnknownException(struct pt_regs *regs)
-{
-#ifdef CONFIG_CMD_KGDB
-	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
-		return;
-#endif
-	printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
-	       regs->nip, regs->msr, regs->trap);
-	_exception(0, regs);
-}
-
-#ifdef CONFIG_CMD_BEDBUG
-extern void do_bedbug_breakpoint(struct pt_regs *);
-#endif
-
-void DebugException(struct pt_regs *regs)
-{
-	printf("Debugger trap at @ %lx\n", regs->nip);
-	show_regs(regs);
-#ifdef CONFIG_CMD_BEDBUG
-	do_bedbug_breakpoint(regs);
-#endif
-}
diff --git a/arch/powerpc/cpu/mpc512x/u-boot.lds b/arch/powerpc/cpu/mpc512x/u-boot.lds
deleted file mode 100644
index b32f74e002..0000000000
--- a/arch/powerpc/cpu/mpc512x/u-boot.lds
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * (C) Copyright 2007-2010 DENX Software Engineering.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
-  .text      :
-  {
-    arch/powerpc/cpu/mpc512x/start.o	(.text*)
-    *(.text*)
-    . = ALIGN(16);
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-    *(.fixup)
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
-ENTRY(_start)
diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig
deleted file mode 100644
index 6ba0dd492d..0000000000
--- a/arch/powerpc/cpu/mpc5xxx/Kconfig
+++ /dev/null
@@ -1,90 +0,0 @@
-menu "mpc5xxx CPU"
-	depends on MPC5xxx
-
-config SYS_CPU
-	default "mpc5xxx"
-
-choice
-	prompt "Target select"
-	optional
-
-config TARGET_A3M071
-	bool "Support a3m071"
-	select SUPPORT_SPL
-
-config TARGET_A4M072
-	bool "Support a4m072"
-
-config TARGET_CANMB
-	bool "Support canmb"
-
-config TARGET_CM5200
-	bool "Support cm5200"
-
-config TARGET_INKA4X0
-	bool "Support inka4x0"
-
-config TARGET_IPEK01
-	bool "Support ipek01"
-
-config TARGET_JUPITER
-	bool "Support jupiter"
-
-config TARGET_MOTIONPRO
-	bool "Support motionpro"
-
-config TARGET_MUNICES
-	bool "Support munices"
-
-config TARGET_V38B
-	bool "Support v38b"
-
-config TARGET_O2D
-	bool "Support O2D"
-
-config TARGET_O2D300
-	bool "Support O2D300"
-
-config TARGET_O2DNT2
-	bool "Support O2DNT2"
-
-config TARGET_O2I
-	bool "Support O2I"
-
-config TARGET_O2MNT
-	bool "Support O2MNT"
-
-config TARGET_O3DNT
-	bool "Support O3DNT"
-
-config TARGET_DIGSY_MTC
-	bool "Support digsy_mtc"
-	imply CMD_IRQ
-
-config TARGET_PCM030
-	bool "Support pcm030"
-
-config TARGET_CHARON
-	bool "Support charon"
-
-config TARGET_TQM5200
-	bool "Support TQM5200"
-
-endchoice
-
-source "board/a3m071/Kconfig"
-source "board/a4m072/Kconfig"
-source "board/canmb/Kconfig"
-source "board/cm5200/Kconfig"
-source "board/ifm/o2dnt2/Kconfig"
-source "board/inka4x0/Kconfig"
-source "board/intercontrol/digsy_mtc/Kconfig"
-source "board/ipek01/Kconfig"
-source "board/jupiter/Kconfig"
-source "board/motionpro/Kconfig"
-source "board/munices/Kconfig"
-source "board/phytec/pcm030/Kconfig"
-source "board/tqc/tqm5200/Kconfig"
-source "board/v38b/Kconfig"
-
-endmenu
diff --git a/arch/powerpc/cpu/mpc5xxx/Makefile b/arch/powerpc/cpu/mpc5xxx/Makefile
deleted file mode 100644
index 88e3b2e3ae..0000000000
--- a/arch/powerpc/cpu/mpc5xxx/Makefile
+++ /dev/null
@@ -1,25 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-extra-y	= start.o
-extra-y += traps.o
-obj-y  += io.o
-obj-y  += firmware_sc_task_bestcomm.impl.o
-obj-y += cpu.o
-obj-y += cpu_init.o
-obj-y += ide.o
-obj-y += interrupts.o
-obj-y += loadtask.o
-obj-y += pci_mpc5200.o
-obj-y += serial.o
-obj-y += speed.o
-obj-$(CONFIG_CMD_USB) += usb_ohci.o
-obj-$(CONFIG_CMD_USB) += usb.o
-
-ifdef CONFIG_SPL_BUILD
-obj-y += spl_boot.o
-endif
diff --git a/arch/powerpc/cpu/mpc5xxx/config.mk b/arch/powerpc/cpu/mpc5xxx/config.mk
deleted file mode 100644
index bcff2144a1..0000000000
--- a/arch/powerpc/cpu/mpc5xxx/config.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -mstring -mcpu=603e -mmultiple
diff --git a/arch/powerpc/cpu/mpc5xxx/cpu.c b/arch/powerpc/cpu/mpc5xxx/cpu.c
deleted file mode 100644
index 84fabbd473..0000000000
--- a/arch/powerpc/cpu/mpc5xxx/cpu.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * CPU specific code for the MPC5xxx CPUs
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <command.h>
-#include <net.h>
-#include <mpc5xxx.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
-
-#if defined(CONFIG_OF_IDE_FIXUP)
-#include <ide.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkcpu (void)
-{
-	ulong clock = gd->cpu_clk;
-	char buf[32];
-	uint svr, pvr;
-
-	puts ("CPU:   ");
-
-	svr = get_svr();
-	pvr = get_pvr();
-
-	switch (pvr) {
-	case PVR_5200:
-		printf("MPC5200");
-		break;
-	case PVR_5200B:
-		printf("MPC5200B");
-		break;
-	default:
-		printf("Unknown MPC5xxx");
-		break;
-	}
-
-	printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr),
-		PVR_MAJ(pvr), PVR_MIN(pvr));
-	printf (" at %s MHz\n", strmhz (buf, clock));
-	return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-int
-do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
-	ulong msr;
-	/* Interrupts and MMU off */
-	__asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
-
-	msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
-	__asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
-
-	/* Charge the watchdog timer */
-	*(vu_long *)(MPC5XXX_GPT0_COUNTER) = 0x0001000f;
-	*(vu_long *)(MPC5XXX_GPT0_ENABLE) = 0x9004; /* wden|ce|timer_ms */
-	while(1);
-
-	return 1;
-
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Get timebase clock frequency (like cpu_clk in Hz)
- *
- */
-unsigned long get_tbclk (void)
-{
-	ulong tbclk;
-
-	tbclk = (gd->bus_clk + 3L) / 4L;
-
-	return (tbclk);
-}
-
-/* ------------------------------------------------------------------------- */
-
-#ifdef CONFIG_OF_BOARD_SETUP
-void ft_cpu_setup(void *blob, bd_t *bd)
-{
-	int div = in_8((void*)CONFIG_SYS_MBAR + 0x204) & 0x0020 ? 8 : 4;
-	char * cpu_path = "/cpus/" OF_CPU;
-#ifdef CONFIG_MPC5xxx_FEC
-	uchar enetaddr[6];
-	char * eth_path = "/" OF_SOC "/ethernet@3000";
-#endif
-
-	do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
-	do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
-	do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
-	do_fixup_by_path_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipbfreq, 1);
-	do_fixup_by_path_u32(blob, "/" OF_SOC, "system-frequency",
-				bd->bi_busfreq*div, 1);
-#ifdef CONFIG_MPC5xxx_FEC
-	eth_getenv_enetaddr("ethaddr", enetaddr);
-	do_fixup_by_path(blob, eth_path, "mac-address", enetaddr, 6, 0);
-	do_fixup_by_path(blob, eth_path, "local-mac-address", enetaddr, 6, 0);
-#endif
-#ifdef CONFIG_OF_IDE_FIXUP
-	if (!ide_device_present(0)) {
-		/* NO CF card detected -> delete ata node in DTS */
-		int nodeoffset = 0;
-		char nodename[] = "/soc5200@f0000000/ata@3a00";
-
-		nodeoffset = fdt_path_offset(blob, nodename);
-		if (nodeoffset >= 0) {
-			fdt_del_node(blob, nodeoffset);
-		} else {
-			printf("%s: cannot find %s node err:%s\n",
-				__func__, nodename, fdt_strerror(nodeoffset));
-		}
-	}
-
-#endif /* CONFIG_OF_IDE_FIXUP */
-	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-#ifdef CONFIG_MPC5xxx_FEC
-/* Default initializations for FEC controllers.  To override,
- * create a board-specific function called:
- * 	int board_eth_init(bd_t *bis)
- */
-
-int cpu_eth_init(bd_t *bis)
-{
-	return mpc5xxx_fec_initialize(bis);
-}
-#endif
-
-#if defined(CONFIG_WATCHDOG)
-void watchdog_reset(void)
-{
-	int re_enable = disable_interrupts();
-	reset_5xxx_watchdog();
-	if (re_enable) enable_interrupts();
-}
-
-void reset_5xxx_watchdog(void)
-{
-	volatile struct mpc5xxx_gpt *gpt0 =
-		(struct mpc5xxx_gpt *) MPC5XXX_GPT;
-
-	/* Trigger TIMER_0 by writing A5 to OCPW */
-	clrsetbits_be32(&gpt0->emsr, 0xff000000, 0xa5000000);
-}
-#endif	/* CONFIG_WATCHDOG */
diff --git a/arch/powerpc/cpu/mpc5xxx/cpu_init.c b/arch/powerpc/cpu/mpc5xxx/cpu_init.c
deleted file mode 100644
index f9b57baf6d..0000000000
--- a/arch/powerpc/cpu/mpc5xxx/cpu_init.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <asm/io.h>
-#include <watchdog.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Breath some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers.
- */
-void cpu_init_f (void)
-{
-	volatile struct mpc5xxx_mmap_ctl *mm =
-		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
-	volatile struct mpc5xxx_lpb *lpb =
-		(struct mpc5xxx_lpb *) MPC5XXX_LPB;
-	volatile struct mpc5xxx_gpio *gpio =
-		(struct mpc5xxx_gpio *) MPC5XXX_GPIO;
-	volatile struct mpc5xxx_xlb *xlb =
-		(struct mpc5xxx_xlb *) MPC5XXX_XLBARB;
-#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
-	volatile struct mpc5xxx_cdm *cdm =
-		(struct mpc5xxx_cdm *) MPC5XXX_CDM;
-#endif	/* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
-#if defined(CONFIG_WATCHDOG)
-	volatile struct mpc5xxx_gpt *gpt0 =
-		(struct mpc5xxx_gpt *) MPC5XXX_GPT;
-#endif /* CONFIG_WATCHDOG */
-	unsigned long addecr = (1 << 25); /* Boot_CS */
-	/* Pointer is writable since we allocated a register for it */
-	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
-
-	/* Clear initial global data */
-	memset ((void *) gd, 0, sizeof (gd_t));
-
-	/*
-	 * Memory Controller: configure chip selects and enable them
-	 */
-#if defined(CONFIG_SYS_BOOTCS_START) && defined(CONFIG_SYS_BOOTCS_SIZE)
-	out_be32(&mm->boot_start, START_REG(CONFIG_SYS_BOOTCS_START));
-	out_be32(&mm->boot_stop, STOP_REG(CONFIG_SYS_BOOTCS_START,
-					  CONFIG_SYS_BOOTCS_SIZE));
-#endif
-#if defined(CONFIG_SYS_BOOTCS_CFG)
-	out_be32(&lpb->cs0_cfg, CONFIG_SYS_BOOTCS_CFG);
-#endif
-
-#if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE)
-	out_be32(&mm->cs0_start, START_REG(CONFIG_SYS_CS0_START));
-	out_be32(&mm->cs0_stop, STOP_REG(CONFIG_SYS_CS0_START,
-					 CONFIG_SYS_CS0_SIZE));
-	/* CS0 and BOOT_CS cannot be enabled at once. */
-	/*	addecr |= (1 << 16); */
-#endif
-#if defined(CONFIG_SYS_CS0_CFG)
-	out_be32(&lpb->cs0_cfg, CONFIG_SYS_CS0_CFG);
-#endif
-
-#if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE)
-	out_be32(&mm->cs1_start, START_REG(CONFIG_SYS_CS1_START));
-	out_be32(&mm->cs1_stop, STOP_REG(CONFIG_SYS_CS1_START,
-					 CONFIG_SYS_CS1_SIZE));
-	addecr |= (1 << 17);
-#endif
-#if defined(CONFIG_SYS_CS1_CFG)
-	out_be32(&lpb->cs1_cfg, CONFIG_SYS_CS1_CFG);
-#endif
-
-#if defined(CONFIG_SYS_CS2_START) && defined(CONFIG_SYS_CS2_SIZE)
-	out_be32(&mm->cs2_start, START_REG(CONFIG_SYS_CS2_START));
-	out_be32(&mm->cs2_stop, STOP_REG(CONFIG_SYS_CS2_START,
-					 CONFIG_SYS_CS2_SIZE));
-	addecr |= (1 << 18);
-#endif
-#if defined(CONFIG_SYS_CS2_CFG)
-	out_be32(&lpb->cs2_cfg, CONFIG_SYS_CS2_CFG);
-#endif
-
-#if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE)
-	out_be32(&mm->cs3_start, START_REG(CONFIG_SYS_CS3_START));
-	out_be32(&mm->cs3_stop, STOP_REG(CONFIG_SYS_CS3_START,
-					 CONFIG_SYS_CS3_SIZE));
-	addecr |= (1 << 19);
-#endif
-#if defined(CONFIG_SYS_CS3_CFG)
-	out_be32(&lpb->cs3_cfg, CONFIG_SYS_CS3_CFG);
-#endif
-
-#if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE)
-	out_be32(&mm->cs4_start, START_REG(CONFIG_SYS_CS4_START));
-	out_be32(&mm->cs4_stop, STOP_REG(CONFIG_SYS_CS4_START,
-					  CONFIG_SYS_CS4_SIZE));
-	addecr |= (1 << 20);
-#endif
-#if defined(CONFIG_SYS_CS4_CFG)
-	out_be32(&lpb->cs4_cfg, CONFIG_SYS_CS4_CFG);
-#endif
-
-#if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE)
-	out_be32(&mm->cs5_start, START_REG(CONFIG_SYS_CS5_START));
-	out_be32(&mm->cs5_stop, STOP_REG(CONFIG_SYS_CS5_START,
-					  CONFIG_SYS_CS5_SIZE));
-	addecr |= (1 << 21);
-#endif
-#if defined(CONFIG_SYS_CS5_CFG)
-	out_be32(&lpb->cs5_cfg, CONFIG_SYS_CS5_CFG);
-#endif
-
-	addecr |= 1;
-#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
-	out_be32(&mm->cs6_start, START_REG(CONFIG_SYS_CS6_START));
-	out_be32(&mm->cs6_stop, STOP_REG(CONFIG_SYS_CS6_START,
-					  CONFIG_SYS_CS6_SIZE));
-	addecr |= (1 << 26);
-#endif
-#if defined(CONFIG_SYS_CS6_CFG)
-	out_be32(&lpb->cs6_cfg, CONFIG_SYS_CS6_CFG);
-#endif
-
-#if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE)
-	out_be32(&mm->cs7_start, START_REG(CONFIG_SYS_CS7_START));
-	out_be32(&mm->cs7_stop, STOP_REG(CONFIG_SYS_CS7_START,
-					  CONFIG_SYS_CS7_SIZE));
-	addecr |= (1 << 27);
-#endif
-#if defined(CONFIG_SYS_CS7_CFG)
-	out_be32(&lpb->cs7_cfg, CONFIG_SYS_CS7_CFG);
-#endif
-
-#if defined(CONFIG_SYS_CS_BURST)
-	out_be32(&lpb->cs_burst, CONFIG_SYS_CS_BURST);
-#endif
-#if defined(CONFIG_SYS_CS_DEADCYCLE)
-	out_be32(&lpb->cs_deadcycle, CONFIG_SYS_CS_DEADCYCLE);
-#endif
-
-	/* Enable chip selects */
-	out_be32(&mm->ipbi_ws_ctrl, addecr);
-	out_be32(&lpb->cs_ctrl, (1 << 24));
-
-	/* Setup pin multiplexing */
-#if defined(CONFIG_SYS_GPS_PORT_CONFIG)
-	out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
-#endif
-
-	/* Setup gpios */
-#if defined(CONFIG_SYS_GPIO_DATADIR)
-	out_be32(&gpio->simple_ddr, CONFIG_SYS_GPIO_DATADIR);
-#endif
-#if defined(CONFIG_SYS_GPIO_OPENDRAIN)
-	out_be32(&gpio->simple_ode, CONFIG_SYS_GPIO_OPENDRAIN);
-#endif
-#if defined(CONFIG_SYS_GPIO_DATAVALUE)
-	out_be32(&gpio->simple_dvo, CONFIG_SYS_GPIO_DATAVALUE);
-#endif
-#if defined(CONFIG_SYS_GPIO_ENABLE)
-	out_be32(&gpio->simple_gpioe, CONFIG_SYS_GPIO_ENABLE);
-#endif
-
-	/* enable timebase */
-	setbits_be32(&xlb->config, (1 << 13));
-
-	/* Enable snooping for RAM */
-	setbits_be32(&xlb->config, (1 << 15));
-	out_be32(&xlb->snoop_window, CONFIG_SYS_SDRAM_BASE | 0x1d);
-
-#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
-	/* Motorola reports IPB should better run at 133 MHz. */
-	setbits_be32(&mm->ipbi_ws_ctrl, 1);
-	/* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
-	addecr = in_be32(&cdm->cfg);
-	addecr &= ~0x103;
-# if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2)
-	/* pci_clk_sel = 0x01 -> IPB_CLK/2 */
-	addecr |= 0x01;
-# else
-	/* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
-	addecr |= 0x02;
-# endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */
-	out_be32(&cdm->cfg, addecr);
-#endif	/* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
-	/* Configure the XLB Arbiter */
-	out_be32(&xlb->master_pri_enable, 0xff);
-	out_be32(&xlb->master_priority, 0x11111111);
-
-#if defined(CONFIG_SYS_XLB_PIPELINING)
-	/* Enable piplining */
-	clrbits_be32(&xlb->config, (1 << 31));
-#endif
-
-#if defined(CONFIG_WATCHDOG)
-	/* Charge the watchdog timer - prescaler = 64k, count = 64k*/
-	out_be32(&gpt0->cir, 0x0000ffff);
-	out_be32(&gpt0->emsr, 0x9004);	/* wden|ce|timer_ms */
-
-	reset_5xxx_watchdog();
-#endif /* CONFIG_WATCHDOG */
-}
-
-/*
- * initialize higher level parts of CPU like time base and timers
- */
-int cpu_init_r (void)
-{
-	volatile struct mpc5xxx_intr *intr =
-		(struct mpc5xxx_intr *) MPC5XXX_ICTL;
-
-	/* mask all interrupts */
-	out_be32(&intr->per_mask, 0xffffff00);
-	setbits_be32(&intr->main_mask, 0x0001ffff);
-	clrbits_be32(&intr->ctrl, 0x00000f00);
-	/* route critical ints to normal ints */
-	setbits_be32(&intr->ctrl, 0x00000001);
-
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC)
-	/* load FEC microcode */
-	loadtask(0, 2);
-#endif
-
-	return (0);
-}
diff --git a/arch/powerpc/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S b/arch/powerpc/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S
deleted file mode 100644
index 00c23121ac..0000000000
--- a/arch/powerpc/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S
+++ /dev/null
@@ -1,359 +0,0 @@
-/*
- * Copyright (C) 2001, Software Center, Motorola China.
- *
- * This file contains microcode for the FEC controller of the MPC5200 CPU.
- */
-
-#include <config.h>
-
-/* sas/sccg, gas target */
-.section        smartdmaInitData,"aw",@progbits	/* Initialized data for task variables */
-.section        smartdmaTaskTable,"aw",@progbits	/* Task tables */
-.align  9
-.globl taskTable
-taskTable:
-.globl scEthernetRecv_Entry
-scEthernetRecv_Entry:		/* Task 0 */
-.long   scEthernetRecv_TDT - taskTable	/* Task 0 Descriptor Table */
-.long   scEthernetRecv_TDT - taskTable + 0x000000a4
-.long   scEthernetRecv_VarTab - taskTable	/* Task 0 Variable Table */
-.long   scEthernetRecv_FDT - taskTable + 0x03	/* Task 0 Function Descriptor Table & Flags */
-.long   0x00000000
-.long   0x00000000
-.long   scEthernetRecv_CSave - taskTable	/* Task 0 context save space */
-.long   CONFIG_SYS_MBAR
-.globl scEthernetXmit_Entry
-scEthernetXmit_Entry:		/* Task 1 */
-.long   scEthernetXmit_TDT - taskTable	/* Task 1 Descriptor Table */
-.long   scEthernetXmit_TDT - taskTable + 0x000000d0
-.long   scEthernetXmit_VarTab - taskTable	/* Task 1 Variable Table */
-.long   scEthernetXmit_FDT - taskTable + 0x03	/* Task 1 Function Descriptor Table & Flags */
-.long   0x00000000
-.long   0x00000000
-.long   scEthernetXmit_CSave - taskTable	/* Task 1 context save space */
-.long   CONFIG_SYS_MBAR
-
-
-.globl scEthernetRecv_TDT
-scEthernetRecv_TDT:	/* Task 0 Descriptor Table */
-.long   0xc4c50000	/* 0000:  LCDEXT: idx0 = var9 + var10; idx0 once var0; idx0 += inc0 */
-.long   0x84c5e000	/* 0004:  LCD: idx1 = var9 + var11; ; idx1 += inc0 */
-.long   0x10001f08	/* 0008:    DRD1A: var7 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x10000380	/* 000C:    DRD1A: var0 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x00000f88	/* 0010:    DRD1A: var3 = *idx1; FN=0 init=0 WS=0 RS=0 */
-.long   0x81980000	/* 0014:  LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */
-.long   0x10000780	/* 0018:    DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x60000000	/* 001C:    DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
-.long   0x010cf04c	/* 0020:    DRD2B1: var4 = EU3(); EU3(var1,var12)  */
-.long   0x82180349	/* 0024:  LCD: idx0 = var4; idx0 != var13; idx0 += inc1 */
-.long   0x81c68004	/* 0028:    LCD: idx1 = var3 + var13 + 4; idx1 once var0; idx1 += inc0 */
-.long   0x70000000	/* 002C:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
-.long   0x018cf04e	/* 0030:      DRD2B1: var6 = EU3(); EU3(var1,var14)  */
-.long   0x70000000	/* 0034:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
-.long   0x020cf04f	/* 0038:      DRD2B1: var8 = EU3(); EU3(var1,var15)  */
-.long   0x00000b88	/* 003C:      DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */
-.long   0x8000d184	/* 0040:    LCDEXT: idx1 = 0xf0003184; ; */
-.long   0xc6990452	/* 0044:    LCDEXT: idx2 = var13; idx2 < var17; idx2 += inc2 */
-.long   0x81486010	/* 0048:    LCD: idx3 = var2 + var16; ; idx3 += inc2 */
-.long   0x006acf88	/* 004C:      DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */
-.long   0x8000d184	/* 0050:    LCDEXT: idx1 = 0xf0003184; ; */
-.long   0x86810492	/* 0054:    LCD: idx2 = var13, idx3 = var2; idx2 < var18; idx2 += inc2, idx3 += inc2 */
-.long   0x006acf88	/* 0058:      DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */
-.long   0x8000d184	/* 005C:    LCDEXT: idx1 = 0xf0003184; ; */
-.long   0x868184d2	/* 0060:    LCD: idx2 = var13, idx3 = var3; idx2 < var19; idx2 += inc2, idx3 += inc2 */
-.long   0x000acf88	/* 0064:      DRD1A: *idx3 = *idx1; FN=0 init=0 WS=1 RS=1 */
-.long   0xc318839b	/* 0068:    LCDEXT: idx1 = var6; idx1 == var14; idx1 += inc3 */
-.long   0x80190000	/* 006C:    LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */
-.long   0x04008468	/* 0070:      DRD1A: idx1 = var13; FN=0 INT init=0 WS=0 RS=0 */
-.long   0xc4038358	/* 0074:    LCDEXT: idx1 = var8, idx2 = var7; idx1 == var13; idx1 += inc3, idx2 += inc0 */
-.long   0x81c50000	/* 0078:    LCD: idx3 = var3 + var10; idx3 once var0; idx3 += inc0 */
-.long   0x1000cb18	/* 007C:      DRD1A: *idx2 = idx3; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x00000f18	/* 0080:      DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */
-.long   0xc4188364	/* 0084:    LCDEXT: idx1 = var8; idx1 > var13; idx1 += inc4 */
-.long   0x83990000	/* 0088:    LCD: idx2 = var7; idx2 once var0; idx2 += inc0 */
-.long   0x10000c00	/* 008C:      DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x0000c800	/* 0090:      DRD1A: *idx2 = var0; FN=0 init=0 WS=0 RS=0 */
-.long   0x81988000	/* 0094:    LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
-.long   0x10000788	/* 0098:      DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x60000000	/* 009C:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
-.long   0x080cf04c	/* 00A0:      DRD2B1: idx0 = EU3(); EU3(var1,var12)  */
-.long   0x000001f8	/* 00A4(:0):    NOP */
-
-
-.globl scEthernetXmit_TDT
-scEthernetXmit_TDT:	/* Task 1 Descriptor Table */
-.long   0x80024800	/* 0000:  LCDEXT: idx0 = 0xf0008800; ; */
-.long   0x85c60004	/* 0004:  LCD: idx1 = var11 + var12 + 4; idx1 once var0; idx1 += inc0 */
-.long   0x10002308	/* 0008:    DRD1A: var8 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x10000f88	/* 000C:    DRD1A: var3 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x00000380	/* 0010:    DRD1A: var0 = *idx0; FN=0 init=0 WS=0 RS=0 */
-.long   0x81980000	/* 0014:  LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */
-.long   0x10000780	/* 0018:    DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x60000000	/* 001C:    DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
-.long   0x024cf04d	/* 0020:    DRD2B1: var9 = EU3(); EU3(var1,var13)  */
-.long   0x84980309	/* 0024:  LCD: idx0 = var9; idx0 != var12; idx0 += inc1 */
-.long   0xc0004003	/* 0028:    LCDEXT: idx1 = 0x00000003; ; */
-.long   0x81c60004	/* 002C:    LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */
-.long   0x70000000	/* 0030:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
-.long   0x010cf04e	/* 0034:      DRD2B1: var4 = EU3(); EU3(var1,var14)  */
-.long   0x70000000	/* 0038:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
-.long   0x014cf04f	/* 003C:      DRD2B1: var5 = EU3(); EU3(var1,var15)  */
-.long   0x70000000	/* 0040:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
-.long   0x028cf050	/* 0044:      DRD2B1: var10 = EU3(); EU3(var1,var16)  */
-.long   0x70000000	/* 0048:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
-.long   0x018cf051	/* 004C:      DRD2B1: var6 = EU3(); EU3(var1,var17)  */
-.long   0x10000b90	/* 0050:      DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x60000000	/* 0054:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
-.long   0x01ccf0a1	/* 0058:      DRD2B1: var7 = EU3(); EU3(var2,idx1)  */
-.long   0xc2988312	/* 005C:    LCDEXT: idx1 = var5; idx1 > var12; idx1 += inc2 */
-.long   0x83490000	/* 0060:    LCD: idx2 = var6 + var18; idx2 once var0; idx2 += inc0 */
-.long   0x00001b10	/* 0064:      DRD1A: var6 = idx2; FN=0 init=0 WS=0 RS=0 */
-.long   0x8000d1a4	/* 0068:    LCDEXT: idx1 = 0xf00031a4; ; */
-.long   0x8301031c	/* 006C:    LCD: idx2 = var6, idx3 = var2; idx2 > var12; idx2 += inc3, idx3 += inc4 */
-.long   0x008ac798	/* 0070:      DRD1A: *idx1 = *idx3; FN=0 init=4 WS=1 RS=1 */
-.long   0x8000d1a4	/* 0074:    LCDEXT: idx1 = 0xf00031a4; ; */
-.long   0xc1430000	/* 0078:    LCDEXT: idx2 = var2 + var6; idx2 once var0; idx2 += inc0 */
-.long   0x82998312	/* 007C:    LCD: idx3 = var5; idx3 > var12; idx3 += inc2 */
-.long   0x088ac790	/* 0080:      DRD1A: *idx1 = *idx2; FN=0 TFD init=4 WS=1 RS=1 */
-.long   0x81988000	/* 0084:    LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
-.long   0x60000001	/* 0088:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=1 EXT init=0 WS=0 RS=0 */
-.long   0x0c4cfc4d	/* 008C:      DRD2B1: *idx1 = EU3(); EU3(*idx1,var13)  */
-.long   0xc21883ad	/* 0090:    LCDEXT: idx1 = var4; idx1 == var14; idx1 += inc5 */
-.long   0x80190000	/* 0094:    LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */
-.long   0x04008460	/* 0098:      DRD1A: idx1 = var12; FN=0 INT init=0 WS=0 RS=0 */
-.long   0xc4052305	/* 009C:    LCDEXT: idx1 = var8, idx2 = var10; idx2 == var12; idx1 += inc0, idx2 += inc5 */
-.long   0x81c98000	/* 00A0:    LCD: idx3 = var3 + var19; idx3 once var0; idx3 += inc0 */
-.long   0x1000c718	/* 00A4:      DRD1A: *idx1 = idx3; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x00000f18	/* 00A8:      DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */
-.long   0xc4188000	/* 00AC:    LCDEXT: idx1 = var8; idx1 once var0; idx1 += inc0 */
-.long   0x85190312	/* 00B0:    LCD: idx2 = var10; idx2 > var12; idx2 += inc2 */
-.long   0x10000c00	/* 00B4:      DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x1000c400	/* 00B8:      DRD1A: *idx1 = var0; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x00008860	/* 00BC:      DRD1A: idx2 = var12; FN=0 init=0 WS=0 RS=0 */
-.long   0x81988000	/* 00C0:    LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
-.long   0x10000788	/* 00C4:      DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
-.long   0x60000000	/* 00C8:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
-.long   0x080cf04d	/* 00CC:      DRD2B1: idx0 = EU3(); EU3(var1,var13)  */
-.long   0x000001f8	/* 00D0(:0):    NOP */
-
-.align  8
-
-.globl scEthernetRecv_VarTab
-scEthernetRecv_VarTab:	/* Task 0 Variable Table */
-.long   0x00000000	/* var[0] */
-.long   0x00000000	/* var[1] */
-.long   0x00000000	/* var[2] */
-.long   0x00000000	/* var[3] */
-.long   0x00000000	/* var[4] */
-.long   0x00000000	/* var[5] */
-.long   0x00000000	/* var[6] */
-.long   0x00000000	/* var[7] */
-.long   0x00000000	/* var[8] */
-.long   (CONFIG_SYS_MBAR + 0x8800)	/* var[9] */
-.long   0x00000008	/* var[10] */
-.long   0x0000000c	/* var[11] */
-.long   0x80000000	/* var[12] */
-.long   0x00000000	/* var[13] */
-.long   0x10000000	/* var[14] */
-.long   0x20000000	/* var[15] */
-.long   0x000005e4	/* var[16] */
-.long   0x0000000e	/* var[17] */
-.long   0x000005e0	/* var[18] */
-.long   0x00000004	/* var[19] */
-.long   0x00000000	/* var[20] */
-.long   0x00000000	/* var[21] */
-.long   0x00000000	/* var[22] */
-.long   0x00000000	/* var[23] */
-.long   0x00000000	/* inc[0] */
-.long   0x60000000	/* inc[1] */
-.long   0x20000001	/* inc[2] */
-.long   0x80000000	/* inc[3] */
-.long   0x40000000	/* inc[4] */
-.long   0x00000000	/* inc[5] */
-.long   0x00000000	/* inc[6] */
-.long   0x00000000	/* inc[7] */
-
-.align  8
-
-.globl scEthernetXmit_VarTab
-scEthernetXmit_VarTab:	/* Task 1 Variable Table */
-.long   0x00000000	/* var[0] */
-.long   0x00000000	/* var[1] */
-.long   0x00000000	/* var[2] */
-.long   0x00000000	/* var[3] */
-.long   0x00000000	/* var[4] */
-.long   0x00000000	/* var[5] */
-.long   0x00000000	/* var[6] */
-.long   0x00000000	/* var[7] */
-.long   0x00000000	/* var[8] */
-.long   0x00000000	/* var[9] */
-.long   0x00000000	/* var[10] */
-.long   (CONFIG_SYS_MBAR + 0x8800)	/* var[11] */
-.long   0x00000000	/* var[12] */
-.long   0x80000000	/* var[13] */
-.long   0x10000000	/* var[14] */
-.long   0x08000000	/* var[15] */
-.long   0x20000000	/* var[16] */
-.long   0x0000ffff	/* var[17] */
-.long   0xffffffff	/* var[18] */
-.long   0x00000008	/* var[19] */
-.long   0x00000000	/* var[20] */
-.long   0x00000000	/* var[21] */
-.long   0x00000000	/* var[22] */
-.long   0x00000000	/* var[23] */
-.long   0x00000000	/* inc[0] */
-.long   0x60000000	/* inc[1] */
-.long   0x40000000	/* inc[2] */
-.long   0x4000ffff	/* inc[3] */
-.long   0xe0000001	/* inc[4] */
-.long   0x80000000	/* inc[5] */
-.long   0x00000000	/* inc[6] */
-.long   0x00000000	/* inc[7] */
-
-.align  8
-
-.globl scEthernetRecv_FDT
-scEthernetRecv_FDT:	/* Task 0 Function Descriptor Table */
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x21800000	/* and(), EU# 3 */
-.long   0x21400000	/* andn(), EU# 3 */
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-
-.align  8
-
-.globl scEthernetXmit_FDT
-scEthernetXmit_FDT:	/* Task 1 Function Descriptor Table */
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x21800000	/* and(), EU# 3 */
-.long   0x21400000	/* andn(), EU# 3 */
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-.long   0x00000000
-
-
-.globl scEthernetRecv_CSave
-scEthernetRecv_CSave:	/* Task 0 context save space */
-.space  128, 0x0
-
-
-.globl scEthernetXmit_CSave
-scEthernetXmit_CSave:	/* Task 1 context save space */
-.space  128, 0x0
diff --git a/arch/powerpc/cpu/mpc5xxx/ide.c b/arch/powerpc/cpu/mpc5xxx/ide.c
deleted file mode 100644
index d1f4349184..0000000000
--- a/arch/powerpc/cpu/mpc5xxx/ide.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * (C) Copyright 2004
- * Pierre AUBERT, Staubli Faverges, <p.aubert@staubli.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Init is derived from Linux code.
- */
-#include <common.h>
-
-#if defined(CONFIG_IDE)
-#include <mpc5xxx.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define CALC_TIMING(t) (t + period - 1) / period
-
-#ifdef CONFIG_IDE_RESET
-extern void init_ide_reset (void);
-#endif
-
-int ide_preinit (void)
-{
-	long period, t0, t1, t2_8, t2_16, t4, ta;
-	vu_long reg;
-	struct mpc5xxx_sdma *psdma = (struct mpc5xxx_sdma *) MPC5XXX_SDMA;
-
-	reg = *(vu_long *) MPC5XXX_GPS_PORT_CONFIG;
-#if defined(CONFIG_SYS_ATA_CS_ON_I2C2)
-	/* ATA cs0/1 on i2c2 clk/io */
-	reg = (reg & ~0x03000000ul) | 0x02000000ul;
-#elif defined(CONFIG_SYS_ATA_CS_ON_TIMER01)
-	/* ATA cs0/1 on Timer 0/1 */
-	reg = (reg & ~0x03000000ul) | 0x03000000ul;
-#else
-	/* ATA cs0/1 on Local Plus cs4/5 */
-	reg = (reg & ~0x03000000ul) | 0x01000000ul;
-#endif	/* CONFIG_TOTAL5200 */
-	*(vu_long *) MPC5XXX_GPS_PORT_CONFIG = reg;
-
-	/* All sample codes do that... */
-	*(vu_long *) MPC5XXX_ATA_SHARE_COUNT = 0;
-
-	/* Configure and reset host */
-	*(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY |
-		MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR;
-	udelay (10);
-	*(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY;
-
-	/* Disable prefetch on Commbus */
-	psdma->PtdCntrl |= 1;
-
-	/* Init timings : we use PIO mode 0 timings */
-	period = 1000000000 / gd->arch.ipb_clk;	/* period in ns */
-
-	t0 = CALC_TIMING (600);
-	t2_8 = CALC_TIMING (290);
-	t2_16 = CALC_TIMING (165);
-	reg = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8);
-	*(vu_long *) MPC5XXX_ATA_PIO1 = reg;
-
-	t4 = CALC_TIMING (30);
-	t1 = CALC_TIMING (70);
-	ta = CALC_TIMING (35);
-	reg = (t4 << 24) | (t1 << 16) | (ta << 8);
-
-	*(vu_long *) MPC5XXX_ATA_PIO2 = reg;
-
-#ifdef CONFIG_IDE_RESET
-	init_ide_reset ();
-#endif /* CONFIG_IDE_RESET */
-
-	return (0);
-}
-#endif
diff --git a/arch/powerpc/cpu/mpc5xxx/interrupts.c b/arch/powerpc/cpu/mpc5xxx/interrupts.c
deleted file mode 100644
index 9121fa0cd0..0000000000
--- a/arch/powerpc/cpu/mpc5xxx/interrupts.c
+++ /dev/null
@@ -1,330 +0,0 @@
-/*
- * (C) Copyright 2006
- * Detlev Zundel, DENX Software Engineering, dzu@denx.de
- *
- * (C) Copyright -2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* this section was ripped out of arch/powerpc/syslib/mpc52xx_pic.c in the
- * Linux 2.6 source with the following copyright.
- *
- * Based on (well, mostly copied from) the code from the 2.4 kernel by
- * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
- *
- * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
- * Copyright (C) 2003 Montavista Software, Inc
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <command.h>
-
-struct irq_action {
-	interrupt_handler_t *handler;
-	void *arg;
-	ulong count;
-};
-
-static struct irq_action irq_handlers[NR_IRQS];
-
-static struct mpc5xxx_intr *intr;
-static struct mpc5xxx_sdma *sdma;
-
-static void mpc5xxx_ic_disable(unsigned int irq)
-{
-	u32 val;
-
-	if (irq == MPC5XXX_IRQ0) {
-		val = in_be32(&intr->ctrl);
-		val &= ~(1 << 11);
-		out_be32(&intr->ctrl, val);
-	} else if (irq < MPC5XXX_IRQ1) {
-		BUG();
-	} else if (irq <= MPC5XXX_IRQ3) {
-		val = in_be32(&intr->ctrl);
-		val &= ~(1 << (10 - (irq - MPC5XXX_IRQ1)));
-		out_be32(&intr->ctrl, val);
-	} else if (irq < MPC5XXX_SDMA_IRQ_BASE) {
-		val = in_be32(&intr->main_mask);
-		val |= 1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE));
-		out_be32(&intr->main_mask, val);
-	} else if (irq < MPC5XXX_PERP_IRQ_BASE) {
-		val = in_be32(&sdma->IntMask);
-		val |= 1 << (irq - MPC5XXX_SDMA_IRQ_BASE);
-		out_be32(&sdma->IntMask, val);
-	} else {
-		val = in_be32(&intr->per_mask);
-		val |= 1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE));
-		out_be32(&intr->per_mask, val);
-	}
-}
-
-static void mpc5xxx_ic_enable(unsigned int irq)
-{
-	u32 val;
-
-	if (irq == MPC5XXX_IRQ0) {
-		val = in_be32(&intr->ctrl);
-		val |= 1 << 11;
-		out_be32(&intr->ctrl, val);
-	} else if (irq < MPC5XXX_IRQ1) {
-		BUG();
-	} else if (irq <= MPC5XXX_IRQ3) {
-		val = in_be32(&intr->ctrl);
-		val |= 1 << (10 - (irq - MPC5XXX_IRQ1));
-		out_be32(&intr->ctrl, val);
-	} else if (irq < MPC5XXX_SDMA_IRQ_BASE) {
-		val = in_be32(&intr->main_mask);
-		val &= ~(1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE)));
-		out_be32(&intr->main_mask, val);
-	} else if (irq < MPC5XXX_PERP_IRQ_BASE) {
-		val = in_be32(&sdma->IntMask);
-		val &= ~(1 << (irq - MPC5XXX_SDMA_IRQ_BASE));
-		out_be32(&sdma->IntMask, val);
-	} else {
-		val = in_be32(&intr->per_mask);
-		val &= ~(1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE)));
-		out_be32(&intr->per_mask, val);
-	}
-}
-
-static void mpc5xxx_ic_ack(unsigned int irq)
-{
-	u32 val;
-
-	/*
-	 * Only some irqs are reset here, others in interrupting hardware.
-	 */
-
-	switch (irq) {
-	case MPC5XXX_IRQ0:
-		val = in_be32(&intr->ctrl);
-		val |= 0x08000000;
-		out_be32(&intr->ctrl, val);
-		break;
-	case MPC5XXX_CCS_IRQ:
-		val = in_be32(&intr->enc_status);
-		val |= 0x00000400;
-		out_be32(&intr->enc_status, val);
-		break;
-	case MPC5XXX_IRQ1:
-		val = in_be32(&intr->ctrl);
-		val |= 0x04000000;
-		out_be32(&intr->ctrl, val);
-		break;
-	case MPC5XXX_IRQ2:
-		val = in_be32(&intr->ctrl);
-		val |= 0x02000000;
-		out_be32(&intr->ctrl, val);
-		break;
-	case MPC5XXX_IRQ3:
-		val = in_be32(&intr->ctrl);
-		val |= 0x01000000;
-		out_be32(&intr->ctrl, val);
-		break;
-	default:
-		if (irq >= MPC5XXX_SDMA_IRQ_BASE
-		    && irq < (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)) {
-			out_be32(&sdma->IntPend,
-				 1 << (irq - MPC5XXX_SDMA_IRQ_BASE));
-		}
-		break;
-	}
-}
-
-static void mpc5xxx_ic_disable_and_ack(unsigned int irq)
-{
-	mpc5xxx_ic_disable(irq);
-	mpc5xxx_ic_ack(irq);
-}
-
-static void mpc5xxx_ic_end(unsigned int irq)
-{
-	mpc5xxx_ic_enable(irq);
-}
-
-void mpc5xxx_init_irq(void)
-{
-	u32 intr_ctrl;
-
-	/* Remap the necessary zones */
-	intr = (struct mpc5xxx_intr *)(MPC5XXX_ICTL);
-	sdma = (struct mpc5xxx_sdma *)(MPC5XXX_SDMA);
-
-	/* Disable all interrupt sources. */
-	out_be32(&sdma->IntPend, 0xffffffff);	/* 1 means clear pending */
-	out_be32(&sdma->IntMask, 0xffffffff);	/* 1 means disabled */
-	out_be32(&intr->per_mask, 0x7ffffc00);	/* 1 means disabled */
-	out_be32(&intr->main_mask, 0x00010fff);	/* 1 means disabled */
-	intr_ctrl = in_be32(&intr->ctrl);
-	intr_ctrl |= 0x0f000000 |	/* clear IRQ 0-3 */
-	    0x00ff0000 |	/* IRQ 0-3 level sensitive low active */
-	    0x00001000 |	/* MEE master external enable */
-	    0x00000000 |	/* 0 means disable IRQ 0-3 */
-	    0x00000001;		/* CEb route critical normally */
-	out_be32(&intr->ctrl, intr_ctrl);
-
-	/* Zero a bunch of the priority settings.  */
-	out_be32(&intr->per_pri1, 0);
-	out_be32(&intr->per_pri2, 0);
-	out_be32(&intr->per_pri3, 0);
-	out_be32(&intr->main_pri1, 0);
-	out_be32(&intr->main_pri2, 0);
-}
-
-int mpc5xxx_get_irq(struct pt_regs *regs)
-{
-	u32 status;
-	int irq = -1;
-
-	status = in_be32(&intr->enc_status);
-
-	if (status & 0x00000400) {	/* critical */
-		irq = (status >> 8) & 0x3;
-		if (irq == 2)	/* high priority peripheral */
-			goto peripheral;
-		irq += MPC5XXX_CRIT_IRQ_BASE;
-	} else if (status & 0x00200000) {	/* main */
-		irq = (status >> 16) & 0x1f;
-		if (irq == 4)	/* low priority peripheral */
-			goto peripheral;
-		irq += MPC5XXX_MAIN_IRQ_BASE;
-	} else if (status & 0x20000000) {	/* peripheral */
-	      peripheral:
-		irq = (status >> 24) & 0x1f;
-		if (irq == 0) {	/* bestcomm */
-			status = in_be32(&sdma->IntPend);
-			irq = ffs(status) + MPC5XXX_SDMA_IRQ_BASE - 1;
-		} else
-			irq += MPC5XXX_PERP_IRQ_BASE;
-	}
-
-	return irq;
-}
-
-/****************************************************************************/
-
-int interrupt_init_cpu(ulong * decrementer_count)
-{
-	*decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
-
-	mpc5xxx_init_irq();
-
-	return (0);
-}
-
-/****************************************************************************/
-
-/*
- * Handle external interrupts
- */
-void external_interrupt(struct pt_regs *regs)
-{
-	int irq, unmask = 1;
-
-	irq = mpc5xxx_get_irq(regs);
-
-	mpc5xxx_ic_disable_and_ack(irq);
-
-	enable_interrupts();
-
-	if (irq_handlers[irq].handler != NULL)
-		(*irq_handlers[irq].handler) (irq_handlers[irq].arg);
-	else {
-		printf("\nBogus External Interrupt IRQ %d\n", irq);
-		/*
-		 * turn off the bogus interrupt, otherwise it
-		 * might repeat forever
-		 */
-		unmask = 0;
-	}
-
-	if (unmask)
-		mpc5xxx_ic_end(irq);
-}
-
-void timer_interrupt_cpu(struct pt_regs *regs)
-{
-	/* nothing to do here */
-	return;
-}
-
-/****************************************************************************/
-
-/*
- * Install and free a interrupt handler.
- */
-
-void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg)
-{
-	if (irq < 0 || irq >= NR_IRQS) {
-		printf("irq_install_handler: bad irq number %d\n", irq);
-		return;
-	}
-
-	if (irq_handlers[irq].handler != NULL)
-		printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
-		       (ulong) handler, (ulong) irq_handlers[irq].handler);
-
-	irq_handlers[irq].handler = handler;
-	irq_handlers[irq].arg = arg;
-
-	mpc5xxx_ic_enable(irq);
-}
-
-void irq_free_handler(int irq)
-{
-	if (irq < 0 || irq >= NR_IRQS) {
-		printf("irq_free_handler: bad irq number %d\n", irq);
-		return;
-	}
-
-	mpc5xxx_ic_disable(irq);
-
-	irq_handlers[irq].handler = NULL;
-	irq_handlers[irq].arg = NULL;
-}
-
-/****************************************************************************/
-
-#if defined(CONFIG_CMD_IRQ)
-void do_irqinfo(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
-{
-	int irq, re_enable;
-	u32 intr_ctrl;
-	char *irq_config[] = { "level sensitive, active high",
-		"edge sensitive, rising active edge",
-		"edge sensitive, falling active edge",
-		"level sensitive, active low"
-	};
-
-	re_enable = disable_interrupts();
-
-	intr_ctrl = in_be32(&intr->ctrl);
-	printf("Interrupt configuration:\n");
-
-	for (irq = 0; irq <= 3; irq++) {
-		printf("IRQ%d: %s\n", irq,
-		       irq_config[(intr_ctrl >> (22 - 2 * irq)) & 0x3]);
-	}
-
-	puts("\nInterrupt-Information:\n" "Nr  Routine   Arg       Count\n");
-
-	for (irq = 0; irq < NR_IRQS; irq++)
-		if (irq_handlers[irq].handler != NULL)
-			printf("%02d  %08lx  %08lx  %ld\n", irq,
-			       (ulong) irq_handlers[irq].handler,
-			       (ulong) irq_handlers[irq].arg,
-			       irq_handlers[irq].count);
-
-	if (re_enable)
-		enable_interrupts();
-}
-#endif
diff --git a/arch/powerpc/cpu/mpc5xxx/io.S b/arch/powerpc/cpu/mpc5xxx/io.S
deleted file mode 100644
index 32641ed67f..0000000000
--- a/arch/powerpc/cpu/mpc5xxx/io.S
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
- *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
- *  Copyright (C) 2001	Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- *			Andreas Heppel <aheppel@sysgo.de>
- *  Copyright (C) 2003	Wolfgang Denk <wd@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <ppc_asm.tmpl>
-
-/* ------------------------------------------------------------------------------- */
-/*  Function:     in8 */
-/*  Description:  Input 8 bits */
-/* ------------------------------------------------------------------------------- */
-	.globl  in8
-in8:
-	lbz     r3,0(r3)
-	sync
-	blr
-
-/* ------------------------------------------------------------------------------- */
-/*  Function:     in16 */
-/*  Description:  Input 16 bits */
-/* ------------------------------------------------------------------------------- */
-	.globl  in16
-in16:
-	lhz     r3,0(r3)
-	sync
-	blr
-
-/* ------------------------------------------------------------------------------- */
-/*  Function:     in16r */
-/*  Description:  Input 16 bits and byte reverse */
-/* ------------------------------------------------------------------------------- */
-	.globl  in16r
-in16r:
-	lhbrx   r3,0,r3
-	sync
-	blr
-
-/* ------------------------------------------------------------------------------- */
-/*  Function:     in32 */
-/*  Description:  Input 32 bits */
-/* ------------------------------------------------------------------------------- */
-	.globl  in32
-in32:
-	lwz     3,0(3)
-	sync
-	blr
-
-/* ------------------------------------------------------------------------------- */
-/*  Function:     in32r */
-/*  Description:  Input 32 bits and byte reverse */
-/* ------------------------------------------------------------------------------- */
-    .globl  in32r
-in32r:
-	lwbrx   r3,0,r3
-	sync
-	blr
-
-/* ------------------------------------------------------------------------------- */
-/*  Function:     out8 */
-/*  Description:  Output 8 bits */
-/* ------------------------------------------------------------------------------- */
-	.globl  out8
-out8:
-	stb     r4,0(r3)
-	sync
-	blr
-
-/* ------------------------------------------------------------------------------- */
-/*  Function:     out16 */
-/*  Description:  Output 16 bits */
-/* ------------------------------------------------------------------------------- */
-	.globl  out16
-out16:
-	sth     r4,0(r3)
-	sync
-	blr
-
-/* ------------------------------------------------------------------------------- */
-/*  Function:     out16r */
-/*  Description:  Byte reverse and output 16 bits */
-/* ------------------------------------------------------------------------------- */
-	.globl  out16r
-out16r:
-	sthbrx  r4,0,r3
-	sync
-	blr
-
-/* ------------------------------------------------------------------------------- */
-/*  Function:     out32 */
-/*  Description:  Output 32 bits */
-/* ------------------------------------------------------------------------------- */
-	.globl  out32
-out32:
-	stw     r4,0(r3)
-	sync
-	blr
-
-/* ------------------------------------------------------------------------------- */
-/*  Function:     out32r */
-/*  Description:  Byte reverse and output 32 bits */
-/* ------------------------------------------------------------------------------- */
-	.globl  out32r
-out32r:
-	stwbrx  r4,0,r3
-	sync
-	blr
diff --git a/arch/powerpc/cpu/mpc5xxx/loadtask.c b/arch/powerpc/cpu/mpc5xxx/loadtask.c
deleted file mode 100644
index 47e7b596a6..0000000000
--- a/arch/powerpc/cpu/mpc5xxx/loadtask.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * This file is based on code
- * (C) Copyright Motorola, Inc., 2000
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-
-/* BestComm/SmartComm microcode */
-extern int taskTable;
-
-void loadtask(int basetask, int tasks)
-{
-	int *sram = (int *)MPC5XXX_SRAM;
-	int *task_org = &taskTable;
-	unsigned int start, offset, end;
-	int i;
-
-#ifdef DEBUG
-	printf("basetask = %d, tasks = %d\n", basetask, tasks);
-	printf("task_org = 0x%08x\n", (unsigned int)task_org);
-#endif
-
-	/* setup TaskBAR register */
-	*(vu_long *)MPC5XXX_SDMA = MPC5XXX_SRAM;
-
-	/* relocate task table entries */
-	offset = (unsigned int)sram;
-	for (i = basetask; i < basetask + tasks; i++) {
-		sram[i * 8 + 0] = task_org[i * 8 + 0] + offset;
-		sram[i * 8 + 1] = task_org[i * 8 + 1] + offset;
-		sram[i * 8 + 2] = task_org[i * 8 + 2] + offset;
-		sram[i * 8 + 3] = task_org[i * 8 + 3] + offset;
-		sram[i * 8 + 4] = task_org[i * 8 + 4];
-		sram[i * 8 + 5] = task_org[i * 8 + 5];
-		sram[i * 8 + 6] = task_org[i * 8 + 6] + offset;
-		sram[i * 8 + 7] = task_org[i * 8 + 7];
-	}
-
-	/* relocate task descriptors */
-	start = (sram[basetask * 8] - (unsigned int)sram);
-	end = (sram[(basetask + tasks - 1) * 8 + 1] - (unsigned int)sram);
-
-#ifdef DEBUG
-	printf ("TDT start = 0x%08x, end = 0x%08x\n", start, end);
-#endif
-
-	start /= 4;
-	end /= 4;
-	for (i = start; i <= end; i++) {
-		sram[i] = task_org[i];
-	}
-
-	/* relocate variables */
-	start = (sram[basetask * 8 + 2] - (unsigned int)sram);
-	end = (sram[(basetask + tasks - 1) * 8 + 2] + 256 - (unsigned int)sram);
-	start /= 4;
-	end /= 4;
-	for (i = start; i < end; i++) {
-		sram[i] = task_org[i];
-	}
-
-	/* relocate function decriptors */
-	start = ((sram[basetask * 8 + 3] & 0xfffffffc) - (unsigned int)sram);
-	end = ((sram[(basetask + tasks - 1) * 8 + 3] & 0xfffffffc) + 256 - (unsigned int)sram);
-	start /= 4;
-	end /= 4;
-	for (i = start; i < end; i++) {
-		sram[i] = task_org[i];
-	}
-
-	asm volatile ("sync");
-}
diff --git a/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c b/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c
deleted file mode 100644
index 70b7e6e6cb..0000000000
--- a/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-#if defined(CONFIG_PCI)
-
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <mpc5xxx.h>
-
-/* System RAM mapped over PCI */
-#define CONFIG_PCI_MEMORY_BUS	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_MEMORY_PHYS	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_MEMORY_SIZE	(1024 * 1024 * 1024)
-
-/* PCIIWCR bit fields */
-#define IWCR_MEM	(0 << 3)
-#define IWCR_IO		(1 << 3)
-#define IWCR_READ	(0 << 1)
-#define IWCR_READLINE	(1 << 1)
-#define IWCR_READMULT	(2 << 1)
-#define IWCR_EN		(1 << 0)
-
-static int mpc5200_read_config_dword(struct pci_controller *hose,
-			      pci_dev_t dev, int offset, u32* value)
-{
-	*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
-	eieio();
-	udelay(10);
-	*value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
-	eieio();
-	*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
-	udelay(10);
-	return 0;
-}
-
-static int mpc5200_write_config_dword(struct pci_controller *hose,
-			      pci_dev_t dev, int offset, u32 value)
-{
-	*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
-	eieio();
-	udelay(10);
-	out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value);
-	eieio();
-	*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
-	udelay(10);
-	return 0;
-}
-
-void pci_mpc5xxx_init (struct pci_controller *hose)
-{
-	hose->first_busno = 0;
-	hose->last_busno = 0xff;
-
-	/* System space */
-	pci_set_region(hose->regions + 0,
-		       CONFIG_PCI_MEMORY_BUS,
-		       CONFIG_PCI_MEMORY_PHYS,
-		       CONFIG_PCI_MEMORY_SIZE,
-		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
-	/* PCI memory space */
-	pci_set_region(hose->regions + 1,
-		       CONFIG_PCI_MEM_BUS,
-		       CONFIG_PCI_MEM_PHYS,
-		       CONFIG_PCI_MEM_SIZE,
-		       PCI_REGION_MEM);
-
-	/* PCI IO space */
-	pci_set_region(hose->regions + 2,
-		       CONFIG_PCI_IO_BUS,
-		       CONFIG_PCI_IO_PHYS,
-		       CONFIG_PCI_IO_SIZE,
-		       PCI_REGION_IO);
-
-	hose->region_count = 3;
-
-	pci_register_hose(hose);
-
-	/* GPIO Multiplexing - enable PCI */
-	*(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15);
-
-	/* Set host bridge as pci master and enable memory decoding */
-	*(vu_long *)MPC5XXX_PCI_CMD |=
-		PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-
-	/* Set maximum latency timer */
-	*(vu_long *)MPC5XXX_PCI_CFG |= (0xf800);
-
-	/* Set cache line size */
-	*(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) |
-		(CONFIG_SYS_CACHELINE_SIZE / 4);
-
-	/* Map MBAR to PCI space */
-	*(vu_long *)MPC5XXX_PCI_BAR0 = CONFIG_SYS_MBAR;
-	*(vu_long *)MPC5XXX_PCI_TBATR0 = CONFIG_SYS_MBAR | 1;
-
-	/* Map RAM to PCI space */
-	*(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
-	*(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1;
-
-	/* Park XLB on PCI */
-	*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5));
-	*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5);
-
-	/* Disable interrupts from PCI controller */
-	*(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12);
-	*(vu_long *)MPC5XXX_PCI_ICR  &= ~(7 << 24);
-
-	/* Set PCI retry counter to 0 = infinite retry. */
-	/* The default of 255 is too short for slow devices. */
-	*(vu_long *)MPC5XXX_PCI_ICR &= 0xFFFFFF00;
-
-	/* Disable initiator windows */
-	*(vu_long *)MPC5XXX_PCI_IWCR = 0;
-
-	/* Map PCI memory to physical space */
-	*(vu_long *)MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS |
-		(((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) |
-		(CONFIG_PCI_MEM_BUS >> 16);
-	*(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_MEM | IWCR_READ | IWCR_EN) << 24;
-
-	/* Map PCI I/O to physical space */
-	*(vu_long *)MPC5XXX_PCI_IW1BTAR = CONFIG_PCI_IO_PHYS |
-		(((CONFIG_PCI_IO_SIZE - 1) >> 8) & 0x00ff0000) |
-		(CONFIG_PCI_IO_BUS >> 16);
-	*(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_IO | IWCR_READ | IWCR_EN) << 16;
-
-	/* Reset the PCI bus */
-	*(vu_long *)MPC5XXX_PCI_GSCR |= 1;
-	udelay(1000);
-	*(vu_long *)MPC5XXX_PCI_GSCR &= ~1;
-	udelay(1000);
-
-	pci_set_ops(hose,
-		pci_hose_read_config_byte_via_dword,
-		pci_hose_read_config_word_via_dword,
-		mpc5200_read_config_dword,
-		pci_hose_write_config_byte_via_dword,
-		pci_hose_write_config_word_via_dword,
-		mpc5200_write_config_dword);
-
-	udelay(1000);
-
-#ifdef CONFIG_PCI_SCAN_SHOW
-	printf("PCI:   Bus Dev VenId DevId Class Int\n");
-#endif
-
-	hose->last_busno = pci_hose_scan(hose);
-}
-#endif /* CONFIG_PCI */
diff --git a/arch/powerpc/cpu/mpc5xxx/serial.c b/arch/powerpc/cpu/mpc5xxx/serial.c
deleted file mode 100644
index bccdcf7973..0000000000
--- a/arch/powerpc/cpu/mpc5xxx/serial.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * (C) Copyright 2000 - 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with
- * changes based on the file arch/powerpc/mbxboot/m8260_tty.c from the
- * Linux/PPC sources (m8260_tty.c had no copyright info in it).
- *
- * Martin Krause, 8 Jun 2006
- * Added SERIAL_MULTI support
- */
-
-/*
- * Minimal serial functions needed to use one of the PSC ports
- * as serial console interface.
- */
-
-#include <common.h>
-#include <linux/compiler.h>
-#include <mpc5xxx.h>
-#include <serial.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_PSC_CONSOLE)
-
-#if CONFIG_PSC_CONSOLE == 1
-#define PSC_BASE MPC5XXX_PSC1
-#elif CONFIG_PSC_CONSOLE == 2
-#define PSC_BASE MPC5XXX_PSC2
-#elif CONFIG_PSC_CONSOLE == 3
-#define PSC_BASE MPC5XXX_PSC3
-#elif CONFIG_PSC_CONSOLE == 4
-#define PSC_BASE MPC5XXX_PSC4
-#elif CONFIG_PSC_CONSOLE == 5
-#define PSC_BASE MPC5XXX_PSC5
-#elif CONFIG_PSC_CONSOLE == 6
-#define PSC_BASE MPC5XXX_PSC6
-#else
-#error CONFIG_PSC_CONSOLE must be in 1 ... 6
-#endif
-
-#if defined(CONFIG_PSC_CONSOLE2)
-
-#if CONFIG_PSC_CONSOLE2 == 1
-#define PSC_BASE2 MPC5XXX_PSC1
-#elif CONFIG_PSC_CONSOLE2 == 2
-#define PSC_BASE2 MPC5XXX_PSC2
-#elif CONFIG_PSC_CONSOLE2 == 3
-#define PSC_BASE2 MPC5XXX_PSC3
-#elif CONFIG_PSC_CONSOLE2 == 4
-#define PSC_BASE2 MPC5XXX_PSC4
-#elif CONFIG_PSC_CONSOLE2 == 5
-#define PSC_BASE2 MPC5XXX_PSC5
-#elif CONFIG_PSC_CONSOLE2 == 6
-#define PSC_BASE2 MPC5XXX_PSC6
-#else
-#error CONFIG_PSC_CONSOLE2 must be in 1 ... 6
-#endif
-
-#endif
-
-int serial_init_dev (unsigned long dev_base)
-{
-	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
-	unsigned long baseclk;
-	int div;
-
-	/* reset PSC */
-	psc->command = PSC_SEL_MODE_REG_1;
-
-	/* select clock sources */
-	psc->psc_clock_select = 0;
-	baseclk = (gd->arch.ipb_clk + 16) / 32;
-
-	/* switch to UART mode */
-	psc->sicr = 0;
-
-	/* configure parity, bit length and so on */
-	psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
-	psc->mode = PSC_MODE_ONE_STOP;
-
-	/* set up UART divisor */
-	div = (baseclk + (gd->baudrate/2)) / gd->baudrate;
-	psc->ctur = (div >> 8) & 0xff;
-	psc->ctlr = div & 0xff;
-
-	/* disable all interrupts */
-	psc->psc_imr = 0;
-
-	/* reset and enable Rx/Tx */
-	psc->command = PSC_RST_RX;
-	psc->command = PSC_RST_TX;
-	psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE;
-
-	return (0);
-}
-
-void serial_putc_dev (unsigned long dev_base, const char c)
-{
-	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
-
-	if (c == '\n')
-		serial_putc_dev (dev_base, '\r');
-
-	/* Wait for last character to go. */
-	while (!(psc->psc_status & PSC_SR_TXEMP))
-		;
-
-	psc->psc_buffer_8 = c;
-}
-
-void serial_puts_dev (unsigned long dev_base, const char *s)
-{
-	while (*s) {
-		serial_putc_dev (dev_base, *s++);
-	}
-}
-
-int serial_getc_dev (unsigned long dev_base)
-{
-	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
-
-	/* Wait for a character to arrive. */
-	while (!(psc->psc_status & PSC_SR_RXRDY))
-		;
-
-	return psc->psc_buffer_8;
-}
-
-int serial_tstc_dev (unsigned long dev_base)
-{
-	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
-
-	return (psc->psc_status & PSC_SR_RXRDY);
-}
-
-void serial_setbrg_dev (unsigned long dev_base)
-{
-	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
-	unsigned long baseclk, div;
-
-	baseclk = (gd->arch.ipb_clk + 16) / 32;
-
-	/* set up UART divisor */
-	div = (baseclk + (gd->baudrate/2)) / gd->baudrate;
-	psc->ctur = (div >> 8) & 0xFF;
-	psc->ctlr =  div & 0xff;
-}
-
-void serial_setrts_dev (unsigned long dev_base, int s)
-{
-	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
-
-	if (s) {
-		/* Assert RTS (become LOW) */
-		psc->op1 = 0x1;
-	}
-	else {
-		/* Negate RTS (become HIGH) */
-		psc->op0 = 0x1;
-	}
-}
-
-int serial_getcts_dev (unsigned long dev_base)
-{
-	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
-
-	return (psc->ip & 0x1) ? 0 : 1;
-}
-
-int serial0_init(void)
-{
-	return (serial_init_dev(PSC_BASE));
-}
-
-void serial0_setbrg (void)
-{
-	serial_setbrg_dev(PSC_BASE);
-}
-
-void serial0_putc(const char c)
-{
-	serial_putc_dev(PSC_BASE,c);
-}
-
-void serial0_puts(const char *s)
-{
-	serial_puts_dev(PSC_BASE, s);
-}
-
-int serial0_getc(void)
-{
-	return(serial_getc_dev(PSC_BASE));
-}
-
-int serial0_tstc(void)
-{
-	return (serial_tstc_dev(PSC_BASE));
-}
-
-struct serial_device serial0_device =
-{
-	.name	= "serial0",
-	.start	= serial0_init,
-	.stop	= NULL,
-	.setbrg	= serial0_setbrg,
-	.getc	= serial0_getc,
-	.tstc	= serial0_tstc,
-	.putc	= serial0_putc,
-	.puts	= serial0_puts,
-};
-
-__weak struct serial_device *default_serial_console(void)
-{
-	return &serial0_device;
-}
-
-#ifdef CONFIG_PSC_CONSOLE2
-int serial1_init(void)
-{
-	return serial_init_dev(PSC_BASE2);
-}
-
-void serial1_setbrg(void)
-{
-	serial_setbrg_dev(PSC_BASE2);
-}
-
-void serial1_putc(const char c)
-{
-	serial_putc_dev(PSC_BASE2, c);
-}
-
-void serial1_puts(const char *s)
-{
-	serial_puts_dev(PSC_BASE2, s);
-}
-
-int serial1_getc(void)
-{
-	return serial_getc_dev(PSC_BASE2);
-}
-
-int serial1_tstc(void)
-{
-	return serial_tstc_dev(PSC_BASE2);
-}
-
-struct serial_device serial1_device =
-{
-	.name	= "serial1",
-	.start	= serial1_init,
-	.stop	= NULL,
-	.setbrg	= serial1_setbrg,
-	.getc	= serial1_getc,
-	.tstc	= serial1_tstc,
-	.putc	= serial1_putc,
-	.puts	= serial1_puts,
-};
-#endif /* CONFIG_PSC_CONSOLE2 */
-
-#endif /* CONFIG_PSC_CONSOLE */
diff --git a/arch/powerpc/cpu/mpc5xxx/speed.c b/arch/powerpc/cpu/mpc5xxx/speed.c
deleted file mode 100644
index b37c4a5208..0000000000
--- a/arch/powerpc/cpu/mpc5xxx/speed.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * (C) Copyright 2000-2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-/* Bus-to-Core Multipliers */
-
-static int bus2core[] = {
-	3, 2, 2, 2, 4, 4, 5, 9,
-	6, 11, 8, 10, 3, 12, 7, 0,
-	6, 5, 13, 2, 14, 4, 15, 9,
-	0, 11, 8, 10, 16, 12, 7, 0
-};
-/* ------------------------------------------------------------------------- */
-
-/*
- *
- */
-
-int get_clocks (void)
-{
-	ulong val, vco;
-
-#if !defined(CONFIG_SYS_MPC5XXX_CLKIN)
-#error clock measuring not implemented yet - define CONFIG_SYS_MPC5XXX_CLKIN
-#endif
-
-	val = *(vu_long *)MPC5XXX_CDM_PORCFG;
-	if (val & (1 << 6)) {
-		vco = CONFIG_SYS_MPC5XXX_CLKIN * 12;
-	} else {
-		vco = CONFIG_SYS_MPC5XXX_CLKIN * 16;
-	}
-	if (val & (1 << 5)) {
-		gd->bus_clk = vco / 8;
-	} else {
-		gd->bus_clk = vco / 4;
-	}
-	gd->cpu_clk = gd->bus_clk * bus2core[val & 0x1f] / 2;
-
-	val = *(vu_long *)MPC5XXX_CDM_CFG;
-	if (val & (1 << 8)) {
-		gd->arch.ipb_clk = gd->bus_clk / 2;
-	} else {
-		gd->arch.ipb_clk = gd->bus_clk;
-	}
-	switch (val & 3) {
-	case 0:
-		gd->pci_clk = gd->arch.ipb_clk;
-		break;
-	case 1:
-		gd->pci_clk = gd->arch.ipb_clk / 2;
-		break;
-	default:
-		gd->pci_clk = gd->bus_clk / 4;
-		break;
-	}
-
-	return (0);
-}
-
-int print_cpuinfo(void)
-{
-	char buf1[32], buf2[32], buf3[32];
-
-	printf ("       Bus %s MHz, IPB %s MHz, PCI %s MHz\n",
-		strmhz(buf1, gd->bus_clk),
-		strmhz(buf2, gd->arch.ipb_clk),
-		strmhz(buf3, gd->pci_clk)
-	);
-	return (0);
-}
-
-/* ------------------------------------------------------------------------- */
diff --git a/arch/powerpc/cpu/mpc5xxx/spl_boot.c b/arch/powerpc/cpu/mpc5xxx/spl_boot.c
deleted file mode 100644
index 2d7f6c4a93..0000000000
--- a/arch/powerpc/cpu/mpc5xxx/spl_boot.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (C) 2012 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Needed to align size SPL image to a 4-byte length
- */
-u32 end_align __attribute__ ((section(".end_align")));
-
-/*
- * Return selected boot device. On MPC5200 its only NOR flash right now.
- */
-u32 spl_boot_device(void)
-{
-	return BOOT_DEVICE_NOR;
-}
-
-/*
- * SPL version of board_init_f()
- */
-void board_init_f(ulong bootflag)
-{
-	end_align = (u32)__spl_flash_end;
-
-	/*
-	 * On MPC5200, the initial RAM (and gd) is located in the internal
-	 * SRAM. So we can actually call the preloader console init code
-	 * before calling dram_init(). This makes serial output (printf)
-	 * available very early, even before SDRAM init, which has been
-	 * an U-Boot priciple from day 1.
-	 */
-
-	/*
-	 * Init global_data pointer. Has to be done before calling
-	 * get_clocks(), as it stores some clock values into gd needed
-	 * later on in the serial driver.
-	 */
-	/* Pointer is writable since we allocated a register for it */
-	gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
-	/* Clear initial global data */
-	memset((void *)gd, 0, sizeof(gd_t));
-
-	/*
-	 * get_clocks() needs to be called so that the serial driver
-	 * works correctly
-	 */
-	get_clocks();
-
-	/*
-	 * Do rudimental console / serial setup
-	 */
-	preloader_console_init();
-
-	/*
-	 * First we need to initialize the SDRAM, so that the real
-	 * U-Boot or the OS (Linux) can be loaded
-	 */
-	dram_init();
-
-	/* Clear bss */
-	memset(__bss_start, '\0', __bss_end - __bss_start);
-
-	/*
-	 * Call board_init_r() (SPL framework version) to load and boot
-	 * real U-Boot or OS
-	 */
-	board_init_r(NULL, 0);
-	/* Does not return!!! */
-}
diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S
deleted file mode 100644
index b4c5543eb5..0000000000
--- a/arch/powerpc/cpu/mpc5xxx/start.S
+++ /dev/null
@@ -1,780 +0,0 @@
-/*
- *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
- *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
- *  Copyright (C) 2000 - 2003 Wolfgang Denk <wd@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- *  U-Boot - Startup Code for MPC5xxx CPUs
- */
-#include <asm-offsets.h>
-#include <config.h>
-#include <mpc5xxx.h>
-#include <version.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <asm/u-boot.h>
-
-/* We don't want the  MMU yet.
-*/
-#undef	MSR_KERNEL
-/* Floating Point enable, Machine Check and Recoverable Interr. */
-#ifdef DEBUG
-#define MSR_KERNEL (MSR_FP|MSR_RI)
-#else
-#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
-#endif
-
-#ifndef CONFIG_SPL_BUILD
-/*
- * Set up GOT: Global Offset Table
- *
- * Use r12 to access the GOT
- */
-	START_GOT
-	GOT_ENTRY(_GOT2_TABLE_)
-	GOT_ENTRY(_FIXUP_TABLE_)
-
-	GOT_ENTRY(_start)
-	GOT_ENTRY(_start_of_vectors)
-	GOT_ENTRY(_end_of_vectors)
-	GOT_ENTRY(transfer_to_handler)
-
-	GOT_ENTRY(__init_end)
-	GOT_ENTRY(__bss_end)
-	GOT_ENTRY(__bss_start)
-	END_GOT
-#endif
-
-/*
- * Version string
- */
-	.data
-	.globl	version_string
-version_string:
-	.ascii U_BOOT_VERSION_STRING, "\0"
-
-/*
- * Exception vectors
- */
-	.text
-	. = EXC_OFF_SYS_RESET
-	.globl	_start
-_start:
-
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-	/*
-	 * This is the entry of the real U-Boot from a board port
-	 * that supports SPL booting on the MPC5200. We only need
-	 * to call board_init_f() here. Everything else has already
-	 * been done in the SPL u-boot version.
-	 */
-	GET_GOT			/* initialize GOT access		*/
-
-	/*
-	 * The GD (global data) struct needs to get cleared. Lets do
-	 * this by calling memset().
-	 * This function is called when the platform is build with SPL
-	 * support from the main (full-blown) U-Boot. And the GD needs
-	 * to get cleared (again) so that the following generic
-	 * board support code initializes all variables correctly.
-	 */
-	mr	r3, r2		/* parameter 1:	 GD pointer		*/
-	li	r4,0		/* parameter 2:	 value to fill		*/
-	li	r5,GD_SIZE	/* parameter 3:	 count			*/
-	bl	memset
-
-	li	r3, 0		/* parameter 1:	 bootflag		*/
-	bl	board_init_f	/* run 1st part of board init code (in Flash)*/
-	/* NOTREACHED - board_init_f() does not return */
-#else
-	mfmsr	r5			/* save msr contents		*/
-
-	/* Move CSBoot and adjust instruction pointer                   */
-	/*--------------------------------------------------------------*/
-
-#if defined(CONFIG_SYS_LOWBOOT)
-# if defined(CONFIG_SYS_RAMBOOT)
-#  error CONFIG_SYS_LOWBOOT is incompatible with CONFIG_SYS_RAMBOOT
-# endif /* CONFIG_SYS_RAMBOOT */
-	lis	r4, CONFIG_SYS_DEFAULT_MBAR@h
-	lis	r3,	START_REG(CONFIG_SYS_BOOTCS_START)@h
-	ori	r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l
-	stw	r3, 0x4(r4)		/* CS0 start */
-	lis	r3,	STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h
-	ori	r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l
-	stw	r3, 0x8(r4)		/* CS0 stop */
-	lis	r3,     0x02010000@h
-	ori	r3, r3, 0x02010000@l
-	stw	r3, 0x54(r4)		/* CS0 and Boot enable */
-
-	lis     r3,	lowboot_reentry@h	/* jump from bootlow address space (0x0000xxxx) */
-	ori     r3, r3, lowboot_reentry@l	/* to the address space the linker used */
-	mtlr	r3
-	blr
-
-lowboot_reentry:
-	lis	r3,	START_REG(CONFIG_SYS_BOOTCS_START)@h
-	ori	r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l
-	stw	r3, 0x4c(r4)		/* Boot start */
-	lis	r3,	STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h
-	ori	r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l
-	stw	r3, 0x50(r4)		/* Boot stop */
-	lis	r3,     0x02000001@h
-	ori	r3, r3, 0x02000001@l
-	stw	r3, 0x54(r4)		/* Boot enable, CS0 disable */
-#endif	/* CONFIG_SYS_LOWBOOT */
-
-#if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT)
-	lis	r3, CONFIG_SYS_MBAR@h
-	ori	r3, r3, CONFIG_SYS_MBAR@l
-	/* MBAR is mirrored into the MBAR SPR */
-	mtspr	MBAR,r3
-	rlwinm	r3, r3, 16, 16, 31
-	lis	r4, CONFIG_SYS_DEFAULT_MBAR@h
-	stw	r3, 0(r4)
-#endif /* CONFIG_SYS_DEFAULT_MBAR */
-
-	/* Initialise the MPC5xxx processor core			*/
-	/*--------------------------------------------------------------*/
-
-	bl	init_5xxx_core
-
-	/* initialize some things that are hard to access from C	*/
-	/*--------------------------------------------------------------*/
-
-	/* set up stack in on-chip SRAM */
-	lis	r3, CONFIG_SYS_INIT_RAM_ADDR@h
-	ori	r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
-	ori	r1, r3, CONFIG_SYS_INIT_SP_OFFSET
-	li	r0, 0			/* Make room for stack frame header and	*/
-	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
-	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/
-
-	/* let the C-code set up the rest				*/
-	/*								*/
-	/* Be careful to keep code relocatable !			*/
-	/*--------------------------------------------------------------*/
-
-#ifndef CONFIG_SPL_BUILD
-	GET_GOT			/* initialize GOT access		*/
-#endif
-
-	/* r3: IMMR */
-	bl	cpu_init_f	/* run low-level CPU init code (in Flash)*/
-
-	li	r3, 0		/* parameter 1:	 bootflag		*/
-	bl	board_init_f	/* run 1st part of board init code (in Flash)*/
-
-	/* NOTREACHED - board_init_f() does not return */
-#endif
-
-#ifndef CONFIG_SPL_BUILD
-/*
- * Vector Table
- */
-
-	.globl	_start_of_vectors
-_start_of_vectors:
-
-/* Machine check */
-	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
-
-/* Data Storage exception. */
-	STD_EXCEPTION(0x300, DataStorage, UnknownException)
-
-/* Instruction Storage exception. */
-	STD_EXCEPTION(0x400, InstStorage, UnknownException)
-
-/* External Interrupt exception. */
-	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
-
-/* Alignment exception. */
-	. = 0x600
-Alignment:
-	EXCEPTION_PROLOG(SRR0, SRR1)
-	mfspr	r4,DAR
-	stw	r4,_DAR(r21)
-	mfspr	r5,DSISR
-	stw	r5,_DSISR(r21)
-	addi	r3,r1,STACK_FRAME_OVERHEAD
-	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
-
-/* Program check exception */
-	. = 0x700
-ProgramCheck:
-	EXCEPTION_PROLOG(SRR0, SRR1)
-	addi	r3,r1,STACK_FRAME_OVERHEAD
-	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
-		MSR_KERNEL, COPY_EE)
-
-	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
-
-	/* I guess we could implement decrementer, and may have
-	 * to someday for timekeeping.
-	 */
-	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
-
-	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
-	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
-	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
-	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
-
-	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
-	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
-
-	STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
-	STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
-	STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
-#ifdef DEBUG
-	. = 0x1300
-	/*
-	 * This exception occurs when the program counter matches the
-	 * Instruction Address Breakpoint Register (IABR).
-	 *
-	 * I want the cpu to halt if this occurs so I can hunt around
-	 * with the debugger and look at things.
-	 *
-	 * When DEBUG is defined, both machine check enable (in the MSR)
-	 * and checkstop reset enable (in the reset mode register) are
-	 * turned off and so a checkstop condition will result in the cpu
-	 * halting.
-	 *
-	 * I force the cpu into a checkstop condition by putting an illegal
-	 * instruction here (at least this is the theory).
-	 *
-	 * well - that didnt work, so just do an infinite loop!
-	 */
-1:	b	1b
-#else
-	STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
-#endif
-	STD_EXCEPTION(0x1400, SMI, UnknownException)
-
-	STD_EXCEPTION(0x1500, Trap_15, UnknownException)
-	STD_EXCEPTION(0x1600, Trap_16, UnknownException)
-	STD_EXCEPTION(0x1700, Trap_17, UnknownException)
-	STD_EXCEPTION(0x1800, Trap_18, UnknownException)
-	STD_EXCEPTION(0x1900, Trap_19, UnknownException)
-	STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
-	STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
-	STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
-	STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
-	STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
-	STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
-	STD_EXCEPTION(0x2000, Trap_20, UnknownException)
-	STD_EXCEPTION(0x2100, Trap_21, UnknownException)
-	STD_EXCEPTION(0x2200, Trap_22, UnknownException)
-	STD_EXCEPTION(0x2300, Trap_23, UnknownException)
-	STD_EXCEPTION(0x2400, Trap_24, UnknownException)
-	STD_EXCEPTION(0x2500, Trap_25, UnknownException)
-	STD_EXCEPTION(0x2600, Trap_26, UnknownException)
-	STD_EXCEPTION(0x2700, Trap_27, UnknownException)
-	STD_EXCEPTION(0x2800, Trap_28, UnknownException)
-	STD_EXCEPTION(0x2900, Trap_29, UnknownException)
-	STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
-	STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
-	STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
-	STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
-	STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
-	STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
-
-
-	.globl	_end_of_vectors
-_end_of_vectors:
-
-	. = 0x3000
-
-/*
- * This code finishes saving the registers to the exception frame
- * and jumps to the appropriate handler for the exception.
- * Register r21 is pointer into trap frame, r1 has new stack pointer.
- */
-	.globl	transfer_to_handler
-transfer_to_handler:
-	stw	r22,_NIP(r21)
-	lis	r22,MSR_POW@h
-	andc	r23,r23,r22
-	stw	r23,_MSR(r21)
-	SAVE_GPR(7, r21)
-	SAVE_4GPRS(8, r21)
-	SAVE_8GPRS(12, r21)
-	SAVE_8GPRS(24, r21)
-	mflr	r23
-	andi.	r24,r23,0x3f00		/* get vector offset */
-	stw	r24,TRAP(r21)
-	li	r22,0
-	stw	r22,RESULT(r21)
-	lwz	r24,0(r23)		/* virtual address of handler */
-	lwz	r23,4(r23)		/* where to go when done */
-	mtspr	SRR0,r24
-	mtspr	SRR1,r20
-	mtlr	r23
-	SYNC
-	rfi				/* jump to handler, enable MMU */
-
-int_return:
-	mfmsr	r28		/* Disable interrupts */
-	li	r4,0
-	ori	r4,r4,MSR_EE
-	andc	r28,r28,r4
-	SYNC			/* Some chip revs need this... */
-	mtmsr	r28
-	SYNC
-	lwz	r2,_CTR(r1)
-	lwz	r0,_LINK(r1)
-	mtctr	r2
-	mtlr	r0
-	lwz	r2,_XER(r1)
-	lwz	r0,_CCR(r1)
-	mtspr	XER,r2
-	mtcrf	0xFF,r0
-	REST_10GPRS(3, r1)
-	REST_10GPRS(13, r1)
-	REST_8GPRS(23, r1)
-	REST_GPR(31, r1)
-	lwz	r2,_NIP(r1)	/* Restore environment */
-	lwz	r0,_MSR(r1)
-	mtspr	SRR0,r2
-	mtspr	SRR1,r0
-	lwz	r0,GPR0(r1)
-	lwz	r2,GPR2(r1)
-	lwz	r1,GPR1(r1)
-	SYNC
-	rfi
-#endif /* CONFIG_SPL_BUILD */
-
-/*
- * This code initialises the MPC5xxx processor core
- * (conforms to PowerPC 603e spec)
- * Note: expects original MSR contents to be in r5.
- */
-
-	.globl	init_5xx_core
-init_5xxx_core:
-
-	/* Initialize machine status; enable machine check interrupt	*/
-	/*--------------------------------------------------------------*/
-
-	li	r3, MSR_KERNEL		/* Set ME and RI flags */
-	rlwimi	r3, r5, 0, 25, 25	/* preserve IP bit set by HRCW */
-#ifdef DEBUG
-	rlwimi	r3, r5, 0, 21, 22	/* debugger might set SE & BE bits */
-#endif
-	SYNC				/* Some chip revs need this... */
-	mtmsr	r3
-	SYNC
-	mtspr	SRR1, r3		/* Make SRR1 match MSR */
-
-	/* Initialize the Hardware Implementation-dependent Registers	*/
-	/* HID0 also contains cache control				*/
-	/*--------------------------------------------------------------*/
-
-	lis	r3, CONFIG_SYS_HID0_INIT@h
-	ori	r3, r3, CONFIG_SYS_HID0_INIT@l
-	SYNC
-	mtspr	HID0, r3
-
-	lis	r3, CONFIG_SYS_HID0_FINAL@h
-	ori	r3, r3, CONFIG_SYS_HID0_FINAL@l
-	SYNC
-	mtspr	HID0, r3
-
-	/* clear all BAT's						*/
-	/*--------------------------------------------------------------*/
-
-	li	r0, 0
-	mtspr	DBAT0U, r0
-	mtspr	DBAT0L, r0
-	mtspr	DBAT1U, r0
-	mtspr	DBAT1L, r0
-	mtspr	DBAT2U, r0
-	mtspr	DBAT2L, r0
-	mtspr	DBAT3U, r0
-	mtspr	DBAT3L, r0
-	mtspr	DBAT4U, r0
-	mtspr	DBAT4L, r0
-	mtspr	DBAT5U, r0
-	mtspr	DBAT5L, r0
-	mtspr	DBAT6U, r0
-	mtspr	DBAT6L, r0
-	mtspr	DBAT7U, r0
-	mtspr	DBAT7L, r0
-	mtspr	IBAT0U, r0
-	mtspr	IBAT0L, r0
-	mtspr	IBAT1U, r0
-	mtspr	IBAT1L, r0
-	mtspr	IBAT2U, r0
-	mtspr	IBAT2L, r0
-	mtspr	IBAT3U, r0
-	mtspr	IBAT3L, r0
-	mtspr	IBAT4U, r0
-	mtspr	IBAT4L, r0
-	mtspr	IBAT5U, r0
-	mtspr	IBAT5L, r0
-	mtspr	IBAT6U, r0
-	mtspr	IBAT6L, r0
-	mtspr	IBAT7U, r0
-	mtspr	IBAT7L, r0
-	SYNC
-
-	/* invalidate all tlb's						*/
-	/*								*/
-	/* From the 603e User Manual: "The 603e provides the ability to	*/
-	/* invalidate a TLB entry. The TLB Invalidate Entry (tlbie)	*/
-	/* instruction invalidates the TLB entry indexed by the EA, and	*/
-	/* operates on both the instruction and data TLBs simultaneously*/
-	/* invalidating four TLB entries (both sets in each TLB). The	*/
-	/* index corresponds to bits 15-19 of the EA. To invalidate all	*/
-	/* entries within both TLBs, 32 tlbie instructions should be	*/
-	/* issued, incrementing this field by one each time."		*/
-	/*								*/
-	/* "Note that the tlbia instruction is not implemented on the	*/
-	/* 603e."							*/
-	/*								*/
-	/* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000	*/
-	/* incrementing by 0x1000 each time. The code below is sort of	*/
-	/* based on code in "flush_tlbs" from arch/powerpc/kernel/head.S	*/
-	/*								*/
-	/*--------------------------------------------------------------*/
-
-	li	r3, 32
-	mtctr	r3
-	li	r3, 0
-1:	tlbie	r3
-	addi	r3, r3, 0x1000
-	bdnz	1b
-	SYNC
-
-	/* Done!							*/
-	/*--------------------------------------------------------------*/
-
-	blr
-
-/* Cache functions.
- *
- * Note: requires that all cache bits in
- * HID0 are in the low half word.
- */
-	.globl	icache_enable
-icache_enable:
-	mfspr	r3, HID0
-	ori	r3, r3, HID0_ICE
-	lis	r4, 0
-	ori	r4, r4, HID0_ILOCK
-	andc	r3, r3, r4
-	ori	r4, r3, HID0_ICFI
-	isync
-	mtspr	HID0, r4	/* sets enable and invalidate, clears lock */
-	isync
-	mtspr	HID0, r3	/* clears invalidate */
-	blr
-
-	.globl	icache_disable
-icache_disable:
-	mfspr	r3, HID0
-	lis	r4, 0
-	ori	r4, r4, HID0_ICE|HID0_ILOCK
-	andc	r3, r3, r4
-	ori	r4, r3, HID0_ICFI
-	isync
-	mtspr	HID0, r4	/* sets invalidate, clears enable and lock */
-	isync
-	mtspr	HID0, r3	/* clears invalidate */
-	blr
-
-	.globl	icache_status
-icache_status:
-	mfspr	r3, HID0
-	rlwinm	r3, r3, HID0_ICE_BITPOS + 1, 31, 31
-	blr
-
-	.globl	dcache_enable
-dcache_enable:
-	mfspr	r3, HID0
-	ori	r3, r3, HID0_DCE
-	lis	r4, 0
-	ori	r4, r4, HID0_DLOCK
-	andc	r3, r3, r4
-	ori	r4, r3, HID0_DCI
-	sync
-	mtspr	HID0, r4	/* sets enable and invalidate, clears lock */
-	sync
-	mtspr	HID0, r3	/* clears invalidate */
-	blr
-
-	.globl	dcache_disable
-dcache_disable:
-	mfspr	r3, HID0
-	lis	r4, 0
-	ori	r4, r4, HID0_DCE|HID0_DLOCK
-	andc	r3, r3, r4
-	ori	r4, r3, HID0_DCI
-	sync
-	mtspr	HID0, r4	/* sets invalidate, clears enable and lock */
-	sync
-	mtspr	HID0, r3	/* clears invalidate */
-	blr
-
-	.globl	dcache_status
-dcache_status:
-	mfspr	r3, HID0
-	rlwinm	r3, r3, HID0_DCE_BITPOS + 1, 31, 31
-	blr
-
-	.globl get_svr
-get_svr:
-	mfspr	r3, SVR
-	blr
-
-	.globl get_pvr
-get_pvr:
-	mfspr	r3, PVR
-	blr
-
-#ifndef CONFIG_SPL_BUILD
-/*------------------------------------------------------------------------------*/
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- * r3 = dest
- * r4 = src
- * r5 = length in bytes
- * r6 = cachelinesize
- */
-	.globl	relocate_code
-relocate_code:
-	mr	r1,  r3		/* Set new stack pointer		*/
-	mr	r9,  r4		/* Save copy of Global Data pointer	*/
-	mr	r10, r5		/* Save copy of Destination Address	*/
-
-	GET_GOT
-	mr	r3,  r5				/* Destination Address	*/
-	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
-	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
-	lwz	r5, GOT(__init_end)
-	sub	r5, r5, r4
-	li	r6, CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size	*/
-
-	/*
-	 * Fix GOT pointer:
-	 *
-	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
-	 *
-	 * Offset:
-	 */
-	sub	r15, r10, r4
-
-	/* First our own GOT */
-	add	r12, r12, r15
-	/* then the one used by the C code */
-	add	r30, r30, r15
-
-	/*
-	 * Now relocate code
-	 */
-
-	cmplw	cr1,r3,r4
-	addi	r0,r5,3
-	srwi.	r0,r0,2
-	beq	cr1,4f		/* In place copy is not necessary	*/
-	beq	7f		/* Protect against 0 count		*/
-	mtctr	r0
-	bge	cr1,2f
-
-	la	r8,-4(r4)
-	la	r7,-4(r3)
-1:	lwzu	r0,4(r8)
-	stwu	r0,4(r7)
-	bdnz	1b
-	b	4f
-
-2:	slwi	r0,r0,2
-	add	r8,r4,r0
-	add	r7,r3,r0
-3:	lwzu	r0,-4(r8)
-	stwu	r0,-4(r7)
-	bdnz	3b
-
-/*
- * Now flush the cache: note that we must start from a cache aligned
- * address. Otherwise we might miss one cache line.
- */
-4:	cmpwi	r6,0
-	add	r5,r3,r5
-	beq	7f		/* Always flush prefetch queue in any case */
-	subi	r0,r6,1
-	andc	r3,r3,r0
-	mfspr	r7,HID0		/* don't do dcbst if dcache is disabled */
-	rlwinm	r7,r7,HID0_DCE_BITPOS+1,31,31
-	cmpwi	r7,0
-	beq	9f
-	mr	r4,r3
-5:	dcbst	0,r4
-	add	r4,r4,r6
-	cmplw	r4,r5
-	blt	5b
-	sync			/* Wait for all dcbst to complete on bus */
-9:	mfspr	r7,HID0		/* don't do icbi if icache is disabled */
-	rlwinm	r7,r7,HID0_ICE_BITPOS+1,31,31
-	cmpwi	r7,0
-	beq	7f
-	mr	r4,r3
-6:	icbi	0,r4
-	add	r4,r4,r6
-	cmplw	r4,r5
-	blt	6b
-7:	sync			/* Wait for all icbi to complete on bus	*/
-	isync
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-
-	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
-	mtlr	r0
-	blr
-
-in_ram:
-
-	/*
-	 * Relocation Function, r12 point to got2+0x8000
-	 *
-	 * Adjust got2 pointers, no need to check for 0, this code
-	 * already puts a few entries in the table.
-	 */
-	li	r0,__got2_entries@sectoff@l
-	la	r3,GOT(_GOT2_TABLE_)
-	lwz	r11,GOT(_GOT2_TABLE_)
-	mtctr	r0
-	sub	r11,r3,r11
-	addi	r3,r3,-4
-1:	lwzu	r0,4(r3)
-	cmpwi	r0,0
-	beq-	2f
-	add	r0,r0,r11
-	stw	r0,0(r3)
-2:	bdnz	1b
-
-	/*
-	 * Now adjust the fixups and the pointers to the fixups
-	 * in case we need to move ourselves again.
-	 */
-	li	r0,__fixup_entries@sectoff@l
-	lwz	r3,GOT(_FIXUP_TABLE_)
-	cmpwi	r0,0
-	mtctr	r0
-	addi	r3,r3,-4
-	beq	4f
-3:	lwzu	r4,4(r3)
-	lwzux	r0,r4,r11
-	cmpwi	r0,0
-	add	r0,r0,r11
-	stw	r4,0(r3)
-	beq-	5f
-	stw	r0,0(r4)
-5:	bdnz	3b
-4:
-clear_bss:
-	/*
-	 * Now clear BSS segment
-	 */
-	lwz	r3,GOT(__bss_start)
-	lwz	r4,GOT(__bss_end)
-
-	cmplw	0, r3, r4
-	beq	6f
-
-	li	r0, 0
-5:
-	stw	r0, 0(r3)
-	addi	r3, r3, 4
-	cmplw	0, r3, r4
-	bne	5b
-6:
-
-	mr	r3, r9		/* Global Data pointer		*/
-	mr	r4, r10		/* Destination Address		*/
-	bl	board_init_r
-
-	/*
-	 * Copy exception vector code to low memory
-	 *
-	 * r3: dest_addr
-	 * r7: source address, r8: end address, r9: target address
-	 */
-	.globl	trap_init
-trap_init:
-	mflr	r4			/* save link register		*/
-	GET_GOT
-	lwz	r7, GOT(_start)
-	lwz	r8, GOT(_end_of_vectors)
-
-	li	r9, 0x100		/* reset vector always at 0x100 */
-
-	cmplw	0, r7, r8
-	bgelr				/* return if r7>=r8 - just in case */
-1:
-	lwz	r0, 0(r7)
-	stw	r0, 0(r9)
-	addi	r7, r7, 4
-	addi	r9, r9, 4
-	cmplw	0, r7, r8
-	bne	1b
-
-	/*
-	 * relocate `hdlr' and `int_return' entries
-	 */
-	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
-	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
-2:
-	bl	trap_reloc
-	addi	r7, r7, 0x100		/* next exception vector	*/
-	cmplw	0, r7, r8
-	blt	2b
-
-	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
-	bl	trap_reloc
-
-	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
-	bl	trap_reloc
-
-	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
-	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
-3:
-	bl	trap_reloc
-	addi	r7, r7, 0x100		/* next exception vector	*/
-	cmplw	0, r7, r8
-	blt	3b
-
-	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
-	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
-4:
-	bl	trap_reloc
-	addi	r7, r7, 0x100		/* next exception vector	*/
-	cmplw	0, r7, r8
-	blt	4b
-
-	mfmsr	r3			/* now that the vectors have	*/
-	lis	r7, MSR_IP@h		/* relocated into low memory	*/
-	ori	r7, r7, MSR_IP@l	/* MSR[IP] can be turned off	*/
-	andc	r3, r3, r7		/* (if it was on)		*/
-	SYNC				/* Some chip revs need this... */
-	mtmsr	r3
-	SYNC
-
-	mtlr	r4			/* restore link register    */
-	blr
-
-#endif /* CONFIG_SPL_BUILD */
diff --git a/arch/powerpc/cpu/mpc5xxx/traps.c b/arch/powerpc/cpu/mpc5xxx/traps.c
deleted file mode 100644
index 5498b7e699..0000000000
--- a/arch/powerpc/cpu/mpc5xxx/traps.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * linux/arch/powerpc/kernel/traps.c
- *
- * Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
- *
- * Modified by Cort Dougan (cort@cs.nmt.edu)
- * and Paul Mackerras (paulus@cs.anu.edu.au)
- * fixed Machine Check Reasons by Reinhard Meyer (r.meyer@emk-elektronik.de)
- *
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * This file handles the architecture-dependent parts of hardware exceptions
- */
-
-#include <common.h>
-#include <command.h>
-#include <kgdb.h>
-#include <asm/processor.h>
-
-/* Returns 0 if exception not found and fixup otherwise.  */
-extern unsigned long search_exception_table(unsigned long);
-
-/* THIS NEEDS CHANGING to use the board info structure.
-*/
-#define END_OF_MEM	0x02000000
-
-/*
- * Trap & Exception support
- */
-
-static void print_backtrace(unsigned long *sp)
-{
-	int cnt = 0;
-	unsigned long i;
-
-	printf("Call backtrace: ");
-	while (sp) {
-		if ((uint)sp > END_OF_MEM)
-			break;
-
-		i = sp[1];
-		if (cnt++ % 7 == 0)
-			printf("\n");
-		printf("%08lX ", i);
-		if (cnt > 32) break;
-		sp = (unsigned long *)*sp;
-	}
-	printf("\n");
-}
-
-void show_regs(struct pt_regs *regs)
-{
-	int i;
-
-	printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
-	       regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
-	printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
-	       regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
-	       regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
-	       regs->msr&MSR_IR ? 1 : 0,
-	       regs->msr&MSR_DR ? 1 : 0);
-
-	printf("\n");
-	for (i = 0;  i < 32;  i++) {
-		if ((i % 8) == 0)
-		{
-			printf("GPR%02d: ", i);
-		}
-
-		printf("%08lX ", regs->gpr[i]);
-		if ((i % 8) == 7)
-		{
-			printf("\n");
-		}
-	}
-}
-
-
-static void _exception(int signr, struct pt_regs *regs)
-{
-	show_regs(regs);
-	print_backtrace((unsigned long *)regs->gpr[1]);
-	panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
-}
-
-void MachineCheckException(struct pt_regs *regs)
-{
-	unsigned long fixup;
-
-	/* Probing PCI using config cycles cause this exception
-	 * when a device is not present.  Catch it and return to
-	 * the PCI exception handler.
-	 */
-	if ((fixup = search_exception_table(regs->nip)) != 0) {
-		regs->nip = fixup;
-		return;
-	}
-
-#if defined(CONFIG_CMD_KGDB)
-	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
-		return;
-#endif
-
-	printf("Machine check in kernel mode.\n");
-	printf("Caused by (from msr): ");
-	printf("regs %p ",regs);
-	/* refer to 603e Manual (MPC603EUM/AD), chapter 4.5.2.1 */
-	switch( regs->msr & 0x000F0000)
-	{
-	case (0x80000000>>12) :
-		printf("Machine check signal - probably due to mm fault\n"
-			"with mmu off\n");
-		break;
-	case (0x80000000>>13) :
-		printf("Transfer error ack signal\n");
-		break;
-	case (0x80000000>>14) :
-		printf("Data parity signal\n");
-		break;
-	case (0x80000000>>15) :
-		printf("Address parity signal\n");
-		break;
-	default:
-		printf("Unknown values in msr\n");
-	}
-	show_regs(regs);
-	print_backtrace((unsigned long *)regs->gpr[1]);
-	panic("machine check");
-}
-
-void AlignmentException(struct pt_regs *regs)
-{
-#if defined(CONFIG_CMD_KGDB)
-	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
-		return;
-#endif
-	show_regs(regs);
-	print_backtrace((unsigned long *)regs->gpr[1]);
-	panic("Alignment Exception");
-}
-
-void ProgramCheckException(struct pt_regs *regs)
-{
-#if defined(CONFIG_CMD_KGDB)
-	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
-		return;
-#endif
-	show_regs(regs);
-	print_backtrace((unsigned long *)regs->gpr[1]);
-	panic("Program Check Exception");
-}
-
-void SoftEmuException(struct pt_regs *regs)
-{
-#if defined(CONFIG_CMD_KGDB)
-	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
-		return;
-#endif
-	show_regs(regs);
-	print_backtrace((unsigned long *)regs->gpr[1]);
-	panic("Software Emulation Exception");
-}
-
-
-void UnknownException(struct pt_regs *regs)
-{
-#if defined(CONFIG_CMD_KGDB)
-	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
-		return;
-#endif
-	printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
-	       regs->nip, regs->msr, regs->trap);
-	_exception(0, regs);
-}
-
-#if defined(CONFIG_CMD_BEDBUG)
-extern void do_bedbug_breakpoint(struct pt_regs *);
-#endif
-
-void DebugException(struct pt_regs *regs)
-{
-
-  printf("Debugger trap at @ %lx\n", regs->nip );
-  show_regs(regs);
-#if defined(CONFIG_CMD_BEDBUG)
-  do_bedbug_breakpoint( regs );
-#endif
-}
-
-/* Probe an address by reading.  If not present, return -1, otherwise
- * return 0.
- */
-int addr_probe(uint *addr)
-{
-#if 0
-	int	retval;
-
-	__asm__ __volatile__(			\
-		"1:	lwz %0,0(%1)\n"		\
-		"	eieio\n"		\
-		"	li %0,0\n"		\
-		"2:\n"				\
-		".section .fixup,\"ax\"\n"	\
-		"3:	li %0,-1\n"		\
-		"	b 2b\n"			\
-		".section __ex_table,\"a\"\n"	\
-		"	.align 2\n"		\
-		"	.long 1b,3b\n"		\
-		".text"				\
-		: "=r" (retval) : "r"(addr));
-
-	return (retval);
-#endif
-	return 0;
-}
diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds b/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds
deleted file mode 100644
index 5354172af0..0000000000
--- a/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within  */
-    /* the sector layout of our flash chips!    XXX FIXME XXX   */
-
-    arch/powerpc/cpu/mpc5xxx/start.o	(.text*)
-    arch/powerpc/cpu/mpc5xxx/traps.o	(.text*)
-
-    . = DEFINED(env_offset) ? env_offset : .;
-    common/env_embedded.o		(.ppcenv*)
-
-    *(.text*)
-    . = ALIGN(16);
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    KEEP(*(.got))
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
-  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds b/arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds
deleted file mode 100644
index 1aa925e932..0000000000
--- a/arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright 2012 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-MEMORY
-{
-	sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
-		LENGTH = CONFIG_SPL_BSS_MAX_SIZE
-	flash : ORIGIN = CONFIG_SPL_TEXT_BASE,
-		LENGTH = CONFIG_SYS_SPL_MAX_LEN
-}
-
-OUTPUT_ARCH(powerpc)
-ENTRY(_start)
-SECTIONS
-{
-	.text :
-	{
-		__start = .;
-		arch/powerpc/cpu/mpc5xxx/start.o	(.text)
-		*(.text*)
-	} > flash
-
-	. = ALIGN(4);
-	.data : { *(SORT_BY_ALIGNMENT(.data*)) } > flash
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } > flash
-
-	. = ALIGN(4);
-	.end_align : { *(.end_align*) } > flash
-	__spl_flash_end = .;
-
-	.bss :
-	{
-		. = ALIGN(4);
-		__bss_start = .;
-		*(.bss*)
-		. = ALIGN(4);
-		__bss_end = .;
-	} > sdram
-}
diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot.lds b/arch/powerpc/cpu/mpc5xxx/u-boot.lds
deleted file mode 100644
index aa80d3dbb1..0000000000
--- a/arch/powerpc/cpu/mpc5xxx/u-boot.lds
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * (C) Copyright 2003-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  .text      :
-  {
-    arch/powerpc/cpu/mpc5xxx/start.o	(.text*)
-    arch/powerpc/cpu/mpc5xxx/traps.o	(.text*)
-    *(.text*)
-    . = ALIGN(16);
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(COMMON)
-   *(.bss*)
-   *(.sbss*)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/arch/powerpc/cpu/mpc5xxx/usb.c b/arch/powerpc/cpu/mpc5xxx/usb.c
deleted file mode 100644
index bdf1484e25..0000000000
--- a/arch/powerpc/cpu/mpc5xxx/usb.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * (C) Copyright 2007
- * Markus Klotzbuecher, DENX Software Engineering <mk@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
-
-#include <mpc5xxx.h>
-
-int usb_cpu_init(void)
-{
-	/* Set the USB Clock						     */
-	*(vu_long *)MPC5XXX_CDM_48_FDC = CONFIG_USB_CLOCK;
-
-#ifdef CONFIG_PSC3_USB /* USB is using the alternate configuration */
-	/* remove all PSC3 USB bits first before ORing in ours */
-	*(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00804f00;
-#else
-	/* remove all USB bits first before ORing in ours */
-	*(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00807000;
-#endif
-	/* Activate USB port						     */
-	*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= CONFIG_USB_CONFIG;
-
-	return 0;
-}
-
-int usb_cpu_stop(void)
-{
-	return 0;
-}
-
-int usb_cpu_init_fail(void)
-{
-	return 0;
-}
-
-#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
diff --git a/arch/powerpc/cpu/mpc5xxx/usb_ohci.c b/arch/powerpc/cpu/mpc5xxx/usb_ohci.c
deleted file mode 100644
index cf36954fe7..0000000000
--- a/arch/powerpc/cpu/mpc5xxx/usb_ohci.c
+++ /dev/null
@@ -1,1529 +0,0 @@
-/*
- * URB OHCI HCD (Host Controller Driver) for USB on the MPC5200.
- *
- * (C) Copyright 2003-2004
- * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Pierre Aubert, Staubli Faverges <p.aubert@staubli.com>
- *
- * Note: Much of this code has been derived from Linux 2.4
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2002 David Brownell
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/*
- * IMPORTANT NOTES
- * 1 - this driver is intended for use with USB Mass Storage Devices
- *     (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
- */
-
-#include <common.h>
-
-#ifdef CONFIG_USB_OHCI
-
-#include <malloc.h>
-#include <usb.h>
-#include "usb_ohci.h"
-
-#include <mpc5xxx.h>
-
-#define OHCI_USE_NPS		/* force NoPowerSwitching mode */
-#undef OHCI_VERBOSE_DEBUG	/* not always helpful */
-#undef DEBUG
-#undef SHOW_INFO
-#undef OHCI_FILL_TRACE
-
-/* For initializing controller (mask in an HCFS mode too) */
-#define OHCI_CONTROL_INIT \
-	(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
-
-#define readl(a) (*((volatile u32 *)(a)))
-#define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
-
-#ifdef DEBUG
-#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
-#else
-#define dbg(format, arg...) do {} while(0)
-#endif /* DEBUG */
-#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
-#ifdef SHOW_INFO
-#define info(format, arg...) printf("INFO: " format "\n", ## arg)
-#else
-#define info(format, arg...) do {} while(0)
-#endif
-
-#define m16_swap(x) swap_16(x)
-#define m32_swap(x) swap_32(x)
-
-#define ohci_cpu_to_le16(x) (x)
-#define ohci_cpu_to_le32(x) (x)
-
-/* global ohci_t */
-static ohci_t gohci;
-/* this must be aligned to a 256 byte boundary */
-struct ohci_hcca ghcca[1];
-/* a pointer to the aligned storage */
-struct ohci_hcca *phcca;
-/* this allocates EDs for all possible endpoints */
-struct ohci_device ohci_dev;
-/* urb_priv */
-urb_priv_t urb_priv;
-/* RHSC flag */
-int got_rhsc;
-/* device which was disconnected */
-struct usb_device *devgone;
-/* flag guarding URB transation */
-int urb_finished = 0;
-
-/*-------------------------------------------------------------------------*/
-
-/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
- * The erratum (#4) description is incorrect.  AMD's workaround waits
- * till some bits (mostly reserved) are clear; ok for all revs.
- */
-#define OHCI_QUIRK_AMD756 0xabcd
-#define read_roothub(hc, register, mask) ({ \
-	u32 temp = readl (&hc->regs->roothub.register); \
-	if (hc->flags & OHCI_QUIRK_AMD756) \
-		while (temp & mask) \
-			temp = readl (&hc->regs->roothub.register); \
-	temp; })
-
-static u32 roothub_a (struct ohci *hc)
-	{ return read_roothub (hc, a, 0xfc0fe000); }
-static inline u32 roothub_b (struct ohci *hc)
-	{ return readl (&hc->regs->roothub.b); }
-static inline u32 roothub_status (struct ohci *hc)
-	{ return readl (&hc->regs->roothub.status); }
-static u32 roothub_portstatus (struct ohci *hc, int i)
-	{ return read_roothub (hc, portstatus [i], 0xffe0fce0); }
-
-
-/* forward declaration */
-static int hc_interrupt (void);
-static void
-td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
-	int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
-
-/*-------------------------------------------------------------------------*
- * URB support functions
- *-------------------------------------------------------------------------*/
-
-/* free HCD-private data associated with this URB */
-
-static void urb_free_priv (urb_priv_t * urb)
-{
-	int		i;
-	int		last;
-	struct td	* td;
-
-	last = urb->length - 1;
-	if (last >= 0) {
-		for (i = 0; i <= last; i++) {
-			td = urb->td[i];
-			if (td) {
-				td->usb_dev = NULL;
-				urb->td[i] = NULL;
-			}
-		}
-	}
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef DEBUG
-static int sohci_get_current_frame_number (struct usb_device * dev);
-
-/* debug| print the main components of an URB
- * small: 0) header + data packets 1) just header */
-
-static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
-	int transfer_len, struct devrequest * setup, char * str, int small)
-{
-	urb_priv_t * purb = &urb_priv;
-
-	dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
-			str,
-			sohci_get_current_frame_number (dev),
-			usb_pipedevice (pipe),
-			usb_pipeendpoint (pipe),
-			usb_pipeout (pipe)? 'O': 'I',
-			usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
-				(usb_pipecontrol (pipe)? "CTRL": "BULK"),
-			purb->actual_length,
-			transfer_len, dev->status);
-#ifdef	OHCI_VERBOSE_DEBUG
-	if (!small) {
-		int i, len;
-
-		if (usb_pipecontrol (pipe)) {
-			printf (__FILE__ ": cmd(8):");
-			for (i = 0; i < 8 ; i++)
-				printf (" %02x", ((__u8 *) setup) [i]);
-			printf ("\n");
-		}
-		if (transfer_len > 0 && buffer) {
-			printf (__FILE__ ": data(%d/%d):",
-				purb->actual_length,
-				transfer_len);
-			len = usb_pipeout (pipe)?
-					transfer_len: purb->actual_length;
-			for (i = 0; i < 16 && i < len; i++)
-				printf (" %02x", ((__u8 *) buffer) [i]);
-			printf ("%s\n", i < len? "...": "");
-		}
-	}
-#endif
-}
-
-/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
-void ep_print_int_eds (ohci_t *ohci, char * str) {
-	int i, j;
-	 __u32 * ed_p;
-	for (i= 0; i < 32; i++) {
-		j = 5;
-		ed_p = &(ohci->hcca->int_table [i]);
-		if (*ed_p == 0)
-		    continue;
-		printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
-		while (*ed_p != 0 && j--) {
-			ed_t *ed = (ed_t *)ohci_cpu_to_le32(ed_p);
-			printf (" ed: %4x;", ed->hwINFO);
-			ed_p = &ed->hwNextED;
-		}
-		printf ("\n");
-	}
-}
-
-static void ohci_dump_intr_mask (char *label, __u32 mask)
-{
-	dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
-		label,
-		mask,
-		(mask & OHCI_INTR_MIE) ? " MIE" : "",
-		(mask & OHCI_INTR_OC) ? " OC" : "",
-		(mask & OHCI_INTR_RHSC) ? " RHSC" : "",
-		(mask & OHCI_INTR_FNO) ? " FNO" : "",
-		(mask & OHCI_INTR_UE) ? " UE" : "",
-		(mask & OHCI_INTR_RD) ? " RD" : "",
-		(mask & OHCI_INTR_SF) ? " SF" : "",
-		(mask & OHCI_INTR_WDH) ? " WDH" : "",
-		(mask & OHCI_INTR_SO) ? " SO" : ""
-		);
-}
-
-static void maybe_print_eds (char *label, __u32 value)
-{
-	ed_t *edp = (ed_t *)value;
-
-	if (value) {
-		dbg ("%s %08x", label, value);
-		dbg ("%08x", edp->hwINFO);
-		dbg ("%08x", edp->hwTailP);
-		dbg ("%08x", edp->hwHeadP);
-		dbg ("%08x", edp->hwNextED);
-	}
-}
-
-static char * hcfs2string (int state)
-{
-	switch (state) {
-		case OHCI_USB_RESET:	return "reset";
-		case OHCI_USB_RESUME:	return "resume";
-		case OHCI_USB_OPER:	return "operational";
-		case OHCI_USB_SUSPEND:	return "suspend";
-	}
-	return "?";
-}
-
-/* dump control and status registers */
-static void ohci_dump_status (ohci_t *controller)
-{
-	struct ohci_regs	*regs = controller->regs;
-	__u32			temp;
-
-	temp = readl (&regs->revision) & 0xff;
-	if (temp != 0x10)
-		dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
-
-	temp = readl (&regs->control);
-	dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
-		(temp & OHCI_CTRL_RWE) ? " RWE" : "",
-		(temp & OHCI_CTRL_RWC) ? " RWC" : "",
-		(temp & OHCI_CTRL_IR) ? " IR" : "",
-		hcfs2string (temp & OHCI_CTRL_HCFS),
-		(temp & OHCI_CTRL_BLE) ? " BLE" : "",
-		(temp & OHCI_CTRL_CLE) ? " CLE" : "",
-		(temp & OHCI_CTRL_IE) ? " IE" : "",
-		(temp & OHCI_CTRL_PLE) ? " PLE" : "",
-		temp & OHCI_CTRL_CBSR
-		);
-
-	temp = readl (&regs->cmdstatus);
-	dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
-		(temp & OHCI_SOC) >> 16,
-		(temp & OHCI_OCR) ? " OCR" : "",
-		(temp & OHCI_BLF) ? " BLF" : "",
-		(temp & OHCI_CLF) ? " CLF" : "",
-		(temp & OHCI_HCR) ? " HCR" : ""
-		);
-
-	ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
-	ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
-
-	maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
-
-	maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
-	maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
-
-	maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
-	maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
-
-	maybe_print_eds ("donehead", readl (&regs->donehead));
-}
-
-static void ohci_dump_roothub (ohci_t *controller, int verbose)
-{
-	__u32			temp, ndp, i;
-
-	temp = roothub_a (controller);
-	ndp = (temp & RH_A_NDP);
-
-	if (verbose) {
-		dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
-			((temp & RH_A_POTPGT) >> 24) & 0xff,
-			(temp & RH_A_NOCP) ? " NOCP" : "",
-			(temp & RH_A_OCPM) ? " OCPM" : "",
-			(temp & RH_A_DT) ? " DT" : "",
-			(temp & RH_A_NPS) ? " NPS" : "",
-			(temp & RH_A_PSM) ? " PSM" : "",
-			ndp
-			);
-		temp = roothub_b (controller);
-		dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
-			temp,
-			(temp & RH_B_PPCM) >> 16,
-			(temp & RH_B_DR)
-			);
-		temp = roothub_status (controller);
-		dbg ("roothub.status: %08x%s%s%s%s%s%s",
-			temp,
-			(temp & RH_HS_CRWE) ? " CRWE" : "",
-			(temp & RH_HS_OCIC) ? " OCIC" : "",
-			(temp & RH_HS_LPSC) ? " LPSC" : "",
-			(temp & RH_HS_DRWE) ? " DRWE" : "",
-			(temp & RH_HS_OCI) ? " OCI" : "",
-			(temp & RH_HS_LPS) ? " LPS" : ""
-			);
-	}
-
-	for (i = 0; i < ndp; i++) {
-		temp = roothub_portstatus (controller, i);
-		dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
-			i,
-			temp,
-			(temp & RH_PS_PRSC) ? " PRSC" : "",
-			(temp & RH_PS_OCIC) ? " OCIC" : "",
-			(temp & RH_PS_PSSC) ? " PSSC" : "",
-			(temp & RH_PS_PESC) ? " PESC" : "",
-			(temp & RH_PS_CSC) ? " CSC" : "",
-
-			(temp & RH_PS_LSDA) ? " LSDA" : "",
-			(temp & RH_PS_PPS) ? " PPS" : "",
-			(temp & RH_PS_PRS) ? " PRS" : "",
-			(temp & RH_PS_POCI) ? " POCI" : "",
-			(temp & RH_PS_PSS) ? " PSS" : "",
-
-			(temp & RH_PS_PES) ? " PES" : "",
-			(temp & RH_PS_CCS) ? " CCS" : ""
-			);
-	}
-}
-
-static void ohci_dump (ohci_t *controller, int verbose)
-{
-	dbg ("OHCI controller usb-%s state", controller->slot_name);
-
-	/* dumps some of the state we know about */
-	ohci_dump_status (controller);
-	if (verbose)
-		ep_print_int_eds (controller, "hcca");
-	dbg ("hcca frame #%04x", controller->hcca->frame_no);
-	ohci_dump_roothub (controller, 1);
-}
-
-
-#endif /* DEBUG */
-
-/*-------------------------------------------------------------------------*
- * Interface functions (URB)
- *-------------------------------------------------------------------------*/
-
-/* get a transfer request */
-
-int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
-		int transfer_len, struct devrequest *setup, int interval)
-{
-	ohci_t *ohci;
-	ed_t * ed;
-	urb_priv_t *purb_priv;
-	int i, size = 0;
-
-	ohci = &gohci;
-
-	/* when controller's hung, permit only roothub cleanup attempts
-	 * such as powering down ports */
-	if (ohci->disabled) {
-		err("sohci_submit_job: EPIPE");
-		return -1;
-	}
-
-	/* if we have an unfinished URB from previous transaction let's
-	 * fail and scream as quickly as possible so as not to corrupt
-	 * further communication */
-	if (!urb_finished) {
-		err("sohci_submit_job: URB NOT FINISHED");
-		return -1;
-	}
-	/* we're about to begin a new transaction here so mark the URB unfinished */
-	urb_finished = 0;
-
-	/* every endpoint has a ed, locate and fill it */
-	if (!(ed = ep_add_ed (dev, pipe))) {
-		err("sohci_submit_job: ENOMEM");
-		return -1;
-	}
-
-	/* for the private part of the URB we need the number of TDs (size) */
-	switch (usb_pipetype (pipe)) {
-		case PIPE_BULK: /* one TD for every 4096 Byte */
-			size = (transfer_len - 1) / 4096 + 1;
-			break;
-		case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
-			size = (transfer_len == 0)? 2:
-						(transfer_len - 1) / 4096 + 3;
-			break;
-	}
-
-	if (size >= (N_URB_TD - 1)) {
-		err("need %d TDs, only have %d", size, N_URB_TD);
-		return -1;
-	}
-	purb_priv = &urb_priv;
-	purb_priv->pipe = pipe;
-
-	/* fill the private part of the URB */
-	purb_priv->length = size;
-	purb_priv->ed = ed;
-	purb_priv->actual_length = 0;
-
-	/* allocate the TDs */
-	/* note that td[0] was allocated in ep_add_ed */
-	for (i = 0; i < size; i++) {
-		purb_priv->td[i] = td_alloc (dev);
-		if (!purb_priv->td[i]) {
-			purb_priv->length = i;
-			urb_free_priv (purb_priv);
-			err("sohci_submit_job: ENOMEM");
-			return -1;
-		}
-	}
-
-	if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
-		urb_free_priv (purb_priv);
-		err("sohci_submit_job: EINVAL");
-		return -1;
-	}
-
-	/* link the ed into a chain if is not already */
-	if (ed->state != ED_OPER)
-		ep_link (ohci, ed);
-
-	/* fill the TDs and link it to the ed */
-	td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
-
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef DEBUG
-/* tell us the current USB frame number */
-
-static int sohci_get_current_frame_number (struct usb_device *usb_dev)
-{
-	ohci_t *ohci = &gohci;
-
-	return ohci_cpu_to_le16 (ohci->hcca->frame_no);
-}
-#endif
-
-/*-------------------------------------------------------------------------*
- * ED handling functions
- *-------------------------------------------------------------------------*/
-
-/* link an ed into one of the HC chains */
-
-static int ep_link (ohci_t *ohci, ed_t *edi)
-{
-	volatile ed_t *ed = edi;
-
-	ed->state = ED_OPER;
-
-	switch (ed->type) {
-	case PIPE_CONTROL:
-		ed->hwNextED = 0;
-		if (ohci->ed_controltail == NULL) {
-			writel (ed, &ohci->regs->ed_controlhead);
-		} else {
-			ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
-		}
-		ed->ed_prev = ohci->ed_controltail;
-		if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
-			!ohci->ed_rm_list[1] && !ohci->sleeping) {
-			ohci->hc_control |= OHCI_CTRL_CLE;
-			writel (ohci->hc_control, &ohci->regs->control);
-		}
-		ohci->ed_controltail = edi;
-		break;
-
-	case PIPE_BULK:
-		ed->hwNextED = 0;
-		if (ohci->ed_bulktail == NULL) {
-			writel (ed, &ohci->regs->ed_bulkhead);
-		} else {
-			ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
-		}
-		ed->ed_prev = ohci->ed_bulktail;
-		if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
-			!ohci->ed_rm_list[1] && !ohci->sleeping) {
-			ohci->hc_control |= OHCI_CTRL_BLE;
-			writel (ohci->hc_control, &ohci->regs->control);
-		}
-		ohci->ed_bulktail = edi;
-		break;
-	}
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* unlink an ed from one of the HC chains.
- * just the link to the ed is unlinked.
- * the link from the ed still points to another operational ed or 0
- * so the HC can eventually finish the processing of the unlinked ed */
-
-static int ep_unlink (ohci_t *ohci, ed_t *edi)
-{
-	volatile ed_t *ed = edi;
-
-	ed->hwINFO |= ohci_cpu_to_le32 (OHCI_ED_SKIP);
-
-	switch (ed->type) {
-	case PIPE_CONTROL:
-		if (ed->ed_prev == NULL) {
-			if (!ed->hwNextED) {
-				ohci->hc_control &= ~OHCI_CTRL_CLE;
-				writel (ohci->hc_control, &ohci->regs->control);
-			}
-			writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
-		} else {
-			ed->ed_prev->hwNextED = ed->hwNextED;
-		}
-		if (ohci->ed_controltail == ed) {
-			ohci->ed_controltail = ed->ed_prev;
-		} else {
-			((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
-		}
-		break;
-
-	case PIPE_BULK:
-		if (ed->ed_prev == NULL) {
-			if (!ed->hwNextED) {
-				ohci->hc_control &= ~OHCI_CTRL_BLE;
-				writel (ohci->hc_control, &ohci->regs->control);
-			}
-			writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
-		} else {
-			ed->ed_prev->hwNextED = ed->hwNextED;
-		}
-		if (ohci->ed_bulktail == ed) {
-			ohci->ed_bulktail = ed->ed_prev;
-		} else {
-			((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
-		}
-		break;
-	}
-	ed->state = ED_UNLINK;
-	return 0;
-}
-
-
-/*-------------------------------------------------------------------------*/
-
-/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
- * but the USB stack is a little bit stateless	so we do it at every transaction
- * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
- * in all other cases the state is left unchanged
- * the ed info fields are setted anyway even though most of them should not change */
-
-static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
-{
-	td_t *td;
-	ed_t *ed_ret;
-	volatile ed_t *ed;
-
-	ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
-			(usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
-
-	if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
-		err("ep_add_ed: pending delete");
-		/* pending delete request */
-		return NULL;
-	}
-
-	if (ed->state == ED_NEW) {
-		ed->hwINFO = ohci_cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */
-		/* dummy td; end of td list for ed */
-		td = td_alloc (usb_dev);
-		ed->hwTailP = ohci_cpu_to_le32 ((unsigned long)td);
-		ed->hwHeadP = ed->hwTailP;
-		ed->state = ED_UNLINK;
-		ed->type = usb_pipetype (pipe);
-		ohci_dev.ed_cnt++;
-	}
-
-	ed->hwINFO = ohci_cpu_to_le32 (usb_pipedevice (pipe)
-			| usb_pipeendpoint (pipe) << 7
-			| (usb_pipeisoc (pipe)? 0x8000: 0)
-			| (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
-			| (usb_dev->speed == USB_SPEED_LOW) << 13
-			| usb_maxpacket (usb_dev, pipe) << 16);
-
-	return ed_ret;
-}
-
-/*-------------------------------------------------------------------------*
- * TD handling functions
- *-------------------------------------------------------------------------*/
-
-/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
-
-static void td_fill (ohci_t *ohci, unsigned int info,
-	void *data, int len,
-	struct usb_device *dev, int index, urb_priv_t *urb_priv)
-{
-	volatile td_t  *td, *td_pt;
-#ifdef OHCI_FILL_TRACE
-	int i;
-#endif
-
-	if (index > urb_priv->length) {
-		err("index > length");
-		return;
-	}
-	/* use this td as the next dummy */
-	td_pt = urb_priv->td [index];
-	td_pt->hwNextTD = 0;
-
-	/* fill the old dummy TD */
-	td = urb_priv->td [index] = (td_t *)(ohci_cpu_to_le32 (urb_priv->ed->hwTailP) & ~0xf);
-
-	td->ed = urb_priv->ed;
-	td->next_dl_td = NULL;
-	td->index = index;
-	td->data = (__u32)data;
-#ifdef OHCI_FILL_TRACE
-	if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
-		for (i = 0; i < len; i++)
-		printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
-		printf("\n");
-	}
-#endif
-	if (!len)
-		data = 0;
-
-	td->hwINFO = ohci_cpu_to_le32 (info);
-	td->hwCBP = ohci_cpu_to_le32 ((unsigned long)data);
-	if (data)
-		td->hwBE = ohci_cpu_to_le32 ((unsigned long)(data + len - 1));
-	else
-		td->hwBE = 0;
-	td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt);
-
-	/* append to queue */
-	td->ed->hwTailP = td->hwNextTD;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* prepare all TDs of a transfer */
-static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
-	int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
-{
-	ohci_t *ohci = &gohci;
-	int data_len = transfer_len;
-	void *data;
-	int cnt = 0;
-	__u32 info = 0;
-	unsigned int toggle = 0;
-
-	/* OHCI handles the DATA-toggles itself, we just use the
-	   USB-toggle bits for resetting */
-	if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
-		toggle = TD_T_TOGGLE;
-	} else {
-		toggle = TD_T_DATA0;
-		usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
-	}
-	urb->td_cnt = 0;
-	if (data_len)
-		data = buffer;
-	else
-		data = 0;
-
-	switch (usb_pipetype (pipe)) {
-	case PIPE_BULK:
-		info = usb_pipeout (pipe)?
-			TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
-		while(data_len > 4096) {
-			td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
-			data += 4096; data_len -= 4096; cnt++;
-		}
-		info = usb_pipeout (pipe)?
-			TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
-		td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
-		cnt++;
-
-		if (!ohci->sleeping)
-			writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
-		break;
-
-	case PIPE_CONTROL:
-		info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
-		td_fill (ohci, info, setup, 8, dev, cnt++, urb);
-		if (data_len > 0) {
-			info = usb_pipeout (pipe)?
-				TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
-			/* NOTE:  mishandles transfers >8K, some >4K */
-			td_fill (ohci, info, data, data_len, dev, cnt++, urb);
-		}
-		info = usb_pipeout (pipe)?
-			TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
-		td_fill (ohci, info, data, 0, dev, cnt++, urb);
-		if (!ohci->sleeping)
-			writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
-		break;
-	}
-	if (urb->length != cnt)
-		dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
-}
-
-/*-------------------------------------------------------------------------*
- * Done List handling functions
- *-------------------------------------------------------------------------*/
-
-
-/* calculate the transfer length and update the urb */
-
-static void dl_transfer_length(td_t * td)
-{
-	__u32 tdBE, tdCBP;
-	urb_priv_t *lurb_priv = &urb_priv;
-
-	tdBE   = ohci_cpu_to_le32 (td->hwBE);
-	tdCBP  = ohci_cpu_to_le32 (td->hwCBP);
-
-
-	if (!(usb_pipecontrol(lurb_priv->pipe) &&
-	    ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
-		if (tdBE != 0) {
-			if (td->hwCBP == 0)
-				lurb_priv->actual_length += tdBE - td->data + 1;
-			else
-				lurb_priv->actual_length += tdCBP - td->data;
-		}
-	}
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* replies to the request have to be on a FIFO basis so
- * we reverse the reversed done-list */
-
-static td_t * dl_reverse_done_list (ohci_t *ohci)
-{
-	__u32 td_list_hc;
-	td_t *td_rev = NULL;
-	td_t *td_list = NULL;
-	urb_priv_t *lurb_priv = NULL;
-
-	td_list_hc = ohci_cpu_to_le32 (ohci->hcca->done_head) & 0xfffffff0;
-	ohci->hcca->done_head = 0;
-
-	while (td_list_hc) {
-		td_list = (td_t *)td_list_hc;
-
-		if (TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO))) {
-			lurb_priv = &urb_priv;
-			dbg(" USB-error/status: %x : %p",
-					TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO)), td_list);
-			if (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x1)) {
-				if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
-					td_list->ed->hwHeadP =
-						(lurb_priv->td[lurb_priv->length - 1]->hwNextTD & ohci_cpu_to_le32 (0xfffffff0)) |
-									(td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x2));
-					lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
-				} else
-					td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2);
-			}
-			td_list->hwNextTD = 0;
-		}
-
-		td_list->next_dl_td = td_rev;
-		td_rev = td_list;
-		td_list_hc = ohci_cpu_to_le32 (td_list->hwNextTD) & 0xfffffff0;
-	}
-	return td_list;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* td done list */
-static int dl_done_list (ohci_t *ohci, td_t *td_list)
-{
-	td_t *td_list_next = NULL;
-	ed_t *ed;
-	int cc = 0;
-	int stat = 0;
-	/* urb_t *urb; */
-	urb_priv_t *lurb_priv;
-	__u32 tdINFO, edHeadP, edTailP;
-
-	while (td_list) {
-		td_list_next = td_list->next_dl_td;
-
-		lurb_priv = &urb_priv;
-		tdINFO = ohci_cpu_to_le32 (td_list->hwINFO);
-
-		ed = td_list->ed;
-
-		dl_transfer_length(td_list);
-
-		/* error code of transfer */
-		cc = TD_CC_GET (tdINFO);
-		if (++(lurb_priv->td_cnt) == lurb_priv->length) {
-			if ((ed->state & (ED_OPER | ED_UNLINK))
-					&& (lurb_priv->state != URB_DEL)) {
-				dbg("ConditionCode %#x", cc);
-				stat = cc_to_error[cc];
-				urb_finished = 1;
-			}
-		}
-
-		if (ed->state != ED_NEW) {
-			edHeadP = ohci_cpu_to_le32 (ed->hwHeadP) & 0xfffffff0;
-			edTailP = ohci_cpu_to_le32 (ed->hwTailP);
-
-			/* unlink eds if they are not busy */
-			if ((edHeadP == edTailP) && (ed->state == ED_OPER))
-				ep_unlink (ohci, ed);
-		}
-
-		td_list = td_list_next;
-	}
-	return stat;
-}
-
-/*-------------------------------------------------------------------------*
- * Virtual Root Hub
- *-------------------------------------------------------------------------*/
-
-#include <usbroothubdes.h>
-
-/* Hub class-specific descriptor is constructed dynamically */
-
-
-/*-------------------------------------------------------------------------*/
-
-#define OK(x)			len = (x); break
-#ifdef DEBUG
-#define WR_RH_STAT(x)		{info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
-#define WR_RH_PORTSTAT(x)	{info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
-#else
-#define WR_RH_STAT(x)		writel((x), &gohci.regs->roothub.status)
-#define WR_RH_PORTSTAT(x)	writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
-#endif
-#define RD_RH_STAT		roothub_status(&gohci)
-#define RD_RH_PORTSTAT		roothub_portstatus(&gohci,wIndex-1)
-
-/* request to virtual root hub */
-
-int rh_check_port_status(ohci_t *controller)
-{
-	__u32 temp, ndp, i;
-	int res;
-
-	res = -1;
-	temp = roothub_a (controller);
-	ndp = (temp & RH_A_NDP);
-	for (i = 0; i < ndp; i++) {
-		temp = roothub_portstatus (controller, i);
-		/* check for a device disconnect */
-		if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
-			(RH_PS_PESC | RH_PS_CSC)) &&
-			((temp & RH_PS_CCS) == 0)) {
-			res = i;
-			break;
-		}
-	}
-	return res;
-}
-
-static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
-		void *buffer, int transfer_len, struct devrequest *cmd)
-{
-	void * data = buffer;
-	int leni = transfer_len;
-	int len = 0;
-	int stat = 0;
-	__u32 datab[4];
-	__u8 *data_buf = (__u8 *)datab;
-	__u16 bmRType_bReq;
-	__u16 wValue;
-	__u16 wIndex;
-	__u16 wLength;
-
-#ifdef DEBUG
-urb_priv.actual_length = 0;
-pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
-#endif
-	if (usb_pipeint(pipe)) {
-		info("Root-Hub submit IRQ: NOT implemented");
-		return 0;
-	}
-
-	bmRType_bReq  = cmd->requesttype | (cmd->request << 8);
-	wValue	      = m16_swap (cmd->value);
-	wIndex	      = m16_swap (cmd->index);
-	wLength	      = m16_swap (cmd->length);
-
-	info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
-		dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
-
-	switch (bmRType_bReq) {
-	/* Request Destination:
-	   without flags: Device,
-	   RH_INTERFACE: interface,
-	   RH_ENDPOINT: endpoint,
-	   RH_CLASS means HUB here,
-	   RH_OTHER | RH_CLASS	almost ever means HUB_PORT here
-	*/
-
-	case RH_GET_STATUS:
-			*(__u16 *) data_buf = m16_swap (1); OK (2);
-	case RH_GET_STATUS | RH_INTERFACE:
-			*(__u16 *) data_buf = m16_swap (0); OK (2);
-	case RH_GET_STATUS | RH_ENDPOINT:
-			*(__u16 *) data_buf = m16_swap (0); OK (2);
-	case RH_GET_STATUS | RH_CLASS:
-			*(__u32 *) data_buf = m32_swap (
-				RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
-			OK (4);
-	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
-			*(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
-
-	case RH_CLEAR_FEATURE | RH_ENDPOINT:
-		switch (wValue) {
-			case (RH_ENDPOINT_STALL): OK (0);
-		}
-		break;
-
-	case RH_CLEAR_FEATURE | RH_CLASS:
-		switch (wValue) {
-			case RH_C_HUB_LOCAL_POWER:
-				OK(0);
-			case (RH_C_HUB_OVER_CURRENT):
-					WR_RH_STAT(RH_HS_OCIC); OK (0);
-		}
-		break;
-
-	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
-		switch (wValue) {
-			case (RH_PORT_ENABLE):
-					WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
-			case (RH_PORT_SUSPEND):
-					WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
-			case (RH_PORT_POWER):
-					WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
-			case (RH_C_PORT_CONNECTION):
-					WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
-			case (RH_C_PORT_ENABLE):
-					WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
-			case (RH_C_PORT_SUSPEND):
-					WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
-			case (RH_C_PORT_OVER_CURRENT):
-					WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
-			case (RH_C_PORT_RESET):
-					WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
-		}
-		break;
-
-	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
-		switch (wValue) {
-			case (RH_PORT_SUSPEND):
-					WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
-			case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
-					if (RD_RH_PORTSTAT & RH_PS_CCS)
-					    WR_RH_PORTSTAT (RH_PS_PRS);
-					OK (0);
-			case (RH_PORT_POWER):
-					WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
-			case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
-					if (RD_RH_PORTSTAT & RH_PS_CCS)
-					    WR_RH_PORTSTAT (RH_PS_PES );
-					OK (0);
-		}
-		break;
-
-	case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
-
-	case RH_GET_DESCRIPTOR:
-		switch ((wValue & 0xff00) >> 8) {
-			case (0x01): /* device descriptor */
-				len = min_t(unsigned int,
-					  leni,
-					  min_t(unsigned int,
-					      sizeof (root_hub_dev_des),
-					      wLength));
-				data_buf = root_hub_dev_des; OK(len);
-			case (0x02): /* configuration descriptor */
-				len = min_t(unsigned int,
-					  leni,
-					  min_t(unsigned int,
-					      sizeof (root_hub_config_des),
-					      wLength));
-				data_buf = root_hub_config_des; OK(len);
-			case (0x03): /* string descriptors */
-				if(wValue==0x0300) {
-					len = min_t(unsigned int,
-						  leni,
-						  min_t(unsigned int,
-						      sizeof (root_hub_str_index0),
-						      wLength));
-					data_buf = root_hub_str_index0;
-					OK(len);
-				}
-				if(wValue==0x0301) {
-					len = min_t(unsigned int,
-						  leni,
-						  min_t(unsigned int,
-						      sizeof (root_hub_str_index1),
-						      wLength));
-					data_buf = root_hub_str_index1;
-					OK(len);
-			}
-			default:
-				stat = USB_ST_STALLED;
-		}
-		break;
-
-	case RH_GET_DESCRIPTOR | RH_CLASS:
-	    {
-		    __u32 temp = roothub_a (&gohci);
-
-		    data_buf [0] = 9;		/* min length; */
-		    data_buf [1] = 0x29;
-		    data_buf [2] = temp & RH_A_NDP;
-		    data_buf [3] = 0;
-		    if (temp & RH_A_PSM)	/* per-port power switching? */
-			data_buf [3] |= 0x1;
-		    if (temp & RH_A_NOCP)	/* no overcurrent reporting? */
-			data_buf [3] |= 0x10;
-		    else if (temp & RH_A_OCPM)	/* per-port overcurrent reporting? */
-			data_buf [3] |= 0x8;
-
-		    /* corresponds to data_buf[4-7] */
-		    datab [1] = 0;
-		    data_buf [5] = (temp & RH_A_POTPGT) >> 24;
-		    temp = roothub_b (&gohci);
-		    data_buf [7] = temp & RH_B_DR;
-		    if (data_buf [2] < 7) {
-			data_buf [8] = 0xff;
-		    } else {
-			data_buf [0] += 2;
-			data_buf [8] = (temp & RH_B_DR) >> 8;
-			data_buf [10] = data_buf [9] = 0xff;
-		    }
-
-		    len = min_t(unsigned int, leni,
-			      min_t(unsigned int, data_buf [0], wLength));
-		    OK (len);
-		}
-
-	case RH_GET_CONFIGURATION:	*(__u8 *) data_buf = 0x01; OK (1);
-
-	case RH_SET_CONFIGURATION:	WR_RH_STAT (0x10000); OK (0);
-
-	default:
-		dbg ("unsupported root hub command");
-		stat = USB_ST_STALLED;
-	}
-
-#ifdef	DEBUG
-	ohci_dump_roothub (&gohci, 1);
-#endif
-
-	len = min_t(int, len, leni);
-	if (data != data_buf)
-	    memcpy (data, data_buf, len);
-	dev->act_len = len;
-	dev->status = stat;
-
-#ifdef DEBUG
-	if (transfer_len)
-		urb_priv.actual_length = transfer_len;
-	pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
-#endif
-
-	return stat;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* common code for handling submit messages - used for all but root hub */
-/* accesses. */
-int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		int transfer_len, struct devrequest *setup, int interval)
-{
-	int stat = 0;
-	int maxsize = usb_maxpacket(dev, pipe);
-	int timeout;
-
-	/* device pulled? Shortcut the action. */
-	if (devgone == dev) {
-		dev->status = USB_ST_CRC_ERR;
-		return 0;
-	}
-
-#ifdef DEBUG
-	urb_priv.actual_length = 0;
-	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
-#endif
-	if (!maxsize) {
-		err("submit_common_message: pipesize for pipe %lx is zero",
-			pipe);
-		return -1;
-	}
-
-	if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
-		err("sohci_submit_job failed");
-		return -1;
-	}
-
-	/* allow more time for a BULK device to react - some are slow */
-#define BULK_TO	 5000	/* timeout in milliseconds */
-	if (usb_pipebulk(pipe))
-		timeout = BULK_TO;
-	else
-		timeout = 100;
-
-	/* wait for it to complete */
-	for (;;) {
-		/* check whether the controller is done */
-		stat = hc_interrupt();
-		if (stat < 0) {
-			stat = USB_ST_CRC_ERR;
-			break;
-		}
-
-		/* NOTE: since we are not interrupt driven in U-Boot and always
-		 * handle only one URB at a time, we cannot assume the
-		 * transaction finished on the first successful return from
-		 * hc_interrupt().. unless the flag for current URB is set,
-		 * meaning that all TD's to/from device got actually
-		 * transferred and processed. If the current URB is not
-		 * finished we need to re-iterate this loop so as
-		 * hc_interrupt() gets called again as there needs to be some
-		 * more TD's to process still */
-		if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {
-			/* 0xff is returned for an SF-interrupt */
-			break;
-		}
-
-		if (--timeout) {
-			mdelay(1);
-			if (!urb_finished)
-				dbg("\%");
-
-		} else {
-			err("CTL:TIMEOUT ");
-			dbg("submit_common_msg: TO status %x\n", stat);
-			stat = USB_ST_CRC_ERR;
-			urb_finished = 1;
-			break;
-		}
-	}
-#if 0
-	/* we got an Root Hub Status Change interrupt */
-	if (got_rhsc) {
-#ifdef DEBUG
-		ohci_dump_roothub (&gohci, 1);
-#endif
-		got_rhsc = 0;
-		/* abuse timeout */
-		timeout = rh_check_port_status(&gohci);
-		if (timeout >= 0) {
-#if 0 /* this does nothing useful, but leave it here in case that changes */
-			/* the called routine adds 1 to the passed value */
-			usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
-#endif
-			/*
-			 * XXX
-			 * This is potentially dangerous because it assumes
-			 * that only one device is ever plugged in!
-			 */
-			devgone = dev;
-		}
-	}
-#endif
-
-	dev->status = stat;
-	dev->act_len = transfer_len;
-
-#ifdef DEBUG
-	pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
-#endif
-
-	/* free TDs in urb_priv */
-	urb_free_priv (&urb_priv);
-	return 0;
-}
-
-/* submit routines called from usb.c */
-int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		int transfer_len)
-{
-	info("submit_bulk_msg");
-	return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
-}
-
-int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		int transfer_len, struct devrequest *setup)
-{
-	int maxsize = usb_maxpacket(dev, pipe);
-
-	info("submit_control_msg");
-#ifdef DEBUG
-	urb_priv.actual_length = 0;
-	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
-#endif
-	if (!maxsize) {
-		err("submit_control_message: pipesize for pipe %lx is zero",
-			pipe);
-		return -1;
-	}
-	if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
-		gohci.rh.dev = dev;
-		/* root hub - redirect */
-		return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
-			setup);
-	}
-
-	return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
-}
-
-int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		int transfer_len, int interval)
-{
-	info("submit_int_msg");
-	return -1;
-}
-
-/*-------------------------------------------------------------------------*
- * HC functions
- *-------------------------------------------------------------------------*/
-
-/* reset the HC and BUS */
-
-static int hc_reset (ohci_t *ohci)
-{
-	int timeout = 30;
-	int smm_timeout = 50; /* 0,5 sec */
-
-	if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
-		writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
-		info("USB HC TakeOver from SMM");
-		while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
-			mdelay (10);
-			if (--smm_timeout == 0) {
-				err("USB HC TakeOver failed!");
-				return -1;
-			}
-		}
-	}
-
-	/* Disable HC interrupts */
-	writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
-
-	dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
-		ohci->slot_name,
-		readl (&ohci->regs->control));
-
-	/* Reset USB (needed by some controllers) */
-	ohci->hc_control = 0;
-	writel (ohci->hc_control, &ohci->regs->control);
-
-	/* HC Reset requires max 10 us delay */
-	writel (OHCI_HCR,  &ohci->regs->cmdstatus);
-	while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
-		if (--timeout == 0) {
-			err("USB HC reset timed out!");
-			return -1;
-		}
-		udelay (1);
-	}
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* Start an OHCI controller, set the BUS operational
- * enable interrupts
- * connect the virtual root hub */
-
-static int hc_start (ohci_t * ohci)
-{
-	__u32 mask;
-	unsigned int fminterval;
-
-	ohci->disabled = 1;
-
-	/* Tell the controller where the control and bulk lists are
-	 * The lists are empty now. */
-
-	writel (0, &ohci->regs->ed_controlhead);
-	writel (0, &ohci->regs->ed_bulkhead);
-
-	writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
-
-	fminterval = 0x2edf;
-	writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
-	fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
-	writel (fminterval, &ohci->regs->fminterval);
-	writel (0x628, &ohci->regs->lsthresh);
-
-	/* start controller operations */
-	ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
-	ohci->disabled = 0;
-	writel (ohci->hc_control, &ohci->regs->control);
-
-	/* disable all interrupts */
-	mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
-			OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
-			OHCI_INTR_OC | OHCI_INTR_MIE);
-	writel (mask, &ohci->regs->intrdisable);
-	/* clear all interrupts */
-	mask &= ~OHCI_INTR_MIE;
-	writel (mask, &ohci->regs->intrstatus);
-	/* Choose the interrupts we care about now  - but w/o MIE */
-	mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
-	writel (mask, &ohci->regs->intrenable);
-
-#ifdef	OHCI_USE_NPS
-	/* required for AMD-756 and some Mac platforms */
-	writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
-		&ohci->regs->roothub.a);
-	writel (RH_HS_LPSC, &ohci->regs->roothub.status);
-#endif	/* OHCI_USE_NPS */
-
-	/* POTPGT delay is bits 24-31, in 2 ms units. */
-	mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
-
-	/* connect the virtual root hub */
-	ohci->rh.devnum = 0;
-
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* an interrupt happens */
-
-static int
-hc_interrupt (void)
-{
-	ohci_t *ohci = &gohci;
-	struct ohci_regs *regs = ohci->regs;
-	int ints;
-	int stat = -1;
-
-	if ((ohci->hcca->done_head != 0) &&
-	     !(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) {
-
-		ints =  OHCI_INTR_WDH;
-
-	} else if ((ints = readl (&regs->intrstatus)) == ~(u32)0) {
-		ohci->disabled++;
-		err ("%s device removed!", ohci->slot_name);
-		return -1;
-
-	} else if ((ints &= readl (&regs->intrenable)) == 0) {
-		dbg("hc_interrupt: returning..\n");
-		return 0xff;
-	}
-
-	/* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
-
-	if (ints & OHCI_INTR_RHSC) {
-		got_rhsc = 1;
-		stat = 0xff;
-	}
-
-	if (ints & OHCI_INTR_UE) {
-		ohci->disabled++;
-		err ("OHCI Unrecoverable Error, controller usb-%s disabled",
-			ohci->slot_name);
-		/* e.g. due to PCI Master/Target Abort */
-
-#ifdef	DEBUG
-		ohci_dump (ohci, 1);
-#endif
-		/* FIXME: be optimistic, hope that bug won't repeat often. */
-		/* Make some non-interrupt context restart the controller. */
-		/* Count and limit the retries though; either hardware or */
-		/* software errors can go forever... */
-		hc_reset (ohci);
-		return -1;
-	}
-
-	if (ints & OHCI_INTR_WDH) {
-		writel (OHCI_INTR_WDH, &regs->intrdisable);
-		stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
-		writel (OHCI_INTR_WDH, &regs->intrenable);
-	}
-
-	if (ints & OHCI_INTR_SO) {
-		dbg("USB Schedule overrun\n");
-		writel (OHCI_INTR_SO, &regs->intrenable);
-		stat = -1;
-	}
-
-	/* FIXME:  this assumes SOF (1/ms) interrupts don't get lost... */
-	if (ints & OHCI_INTR_SF) {
-		unsigned int frame = ohci_cpu_to_le16 (ohci->hcca->frame_no) & 1;
-		mdelay(1);
-		writel (OHCI_INTR_SF, &regs->intrdisable);
-		if (ohci->ed_rm_list[frame] != NULL)
-			writel (OHCI_INTR_SF, &regs->intrenable);
-		stat = 0xff;
-	}
-
-	writel (ints, &regs->intrstatus);
-	return stat;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/*-------------------------------------------------------------------------*/
-
-/* De-allocate all resources.. */
-
-static void hc_release_ohci (ohci_t *ohci)
-{
-	dbg ("USB HC release ohci usb-%s", ohci->slot_name);
-
-	if (!ohci->disabled)
-		hc_reset (ohci);
-}
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * low level initalisation routine, called from usb.c
- */
-static char ohci_inited = 0;
-
-int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
-{
-
-	/* Set the USB Clock						     */
-	*(vu_long *)MPC5XXX_CDM_48_FDC = CONFIG_USB_CLOCK;
-
-#ifdef CONFIG_PSC3_USB /* USB is using the alternate configuration */
-	/* remove all PSC3 USB bits first before ORing in ours */
-	*(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00804f00;
-#else
-	/* remove all USB bits first before ORing in ours */
-	*(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00807000;
-#endif
-	/* Activate USB port						     */
-	*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= CONFIG_USB_CONFIG;
-
-	memset (&gohci, 0, sizeof (ohci_t));
-	memset (&urb_priv, 0, sizeof (urb_priv_t));
-
-	/* align the storage */
-	if ((__u32)&ghcca[0] & 0xff) {
-		err("HCCA not aligned!!");
-		return -1;
-	}
-	phcca = &ghcca[0];
-	info("aligned ghcca %p", phcca);
-	memset(&ohci_dev, 0, sizeof(struct ohci_device));
-	if ((__u32)&ohci_dev.ed[0] & 0x7) {
-		err("EDs not aligned!!");
-		return -1;
-	}
-	memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
-	if ((__u32)gtd & 0x7) {
-		err("TDs not aligned!!");
-		return -1;
-	}
-	ptd = gtd;
-	gohci.hcca = phcca;
-	memset (phcca, 0, sizeof (struct ohci_hcca));
-
-	gohci.disabled = 1;
-	gohci.sleeping = 0;
-	gohci.irq = -1;
-	gohci.regs = (struct ohci_regs *)MPC5XXX_USB;
-
-	gohci.flags = 0;
-	gohci.slot_name = "mpc5200";
-
-	if (hc_reset (&gohci) < 0) {
-		hc_release_ohci (&gohci);
-		return -1;
-	}
-
-	if (hc_start (&gohci) < 0) {
-		err ("can't start usb-%s", gohci.slot_name);
-		hc_release_ohci (&gohci);
-		return -1;
-	}
-
-#ifdef	DEBUG
-	ohci_dump (&gohci, 1);
-#endif
-	ohci_inited = 1;
-	urb_finished = 1;
-
-	return 0;
-}
-
-int usb_lowlevel_stop(int index)
-{
-	/* this gets called really early - before the controller has */
-	/* even been initialized! */
-	if (!ohci_inited)
-		return 0;
-	/* TODO release any interrupts, etc. */
-	/* call hc_release_ohci() here ? */
-	hc_reset (&gohci);
-	return 0;
-}
-
-#endif /* CONFIG_USB_OHCI */
diff --git a/arch/powerpc/cpu/mpc5xxx/usb_ohci.h b/arch/powerpc/cpu/mpc5xxx/usb_ohci.h
deleted file mode 100644
index 629b529a69..0000000000
--- a/arch/powerpc/cpu/mpc5xxx/usb_ohci.h
+++ /dev/null
@@ -1,418 +0,0 @@
-/*
- * URB OHCI HCD (Host Controller Driver) for USB.
- *
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
- *
- * usb-ohci.h
- */
-
-
-static int cc_to_error[16] = {
-
-/* mapping of the OHCI CC status to error codes */
-	/* No  Error  */	       0,
-	/* CRC Error  */	       USB_ST_CRC_ERR,
-	/* Bit Stuff  */	       USB_ST_BIT_ERR,
-	/* Data Togg  */	       USB_ST_CRC_ERR,
-	/* Stall      */	       USB_ST_STALLED,
-	/* DevNotResp */	       -1,
-	/* PIDCheck   */	       USB_ST_BIT_ERR,
-	/* UnExpPID   */	       USB_ST_BIT_ERR,
-	/* DataOver   */	       USB_ST_BUF_ERR,
-	/* DataUnder  */	       USB_ST_BUF_ERR,
-	/* reservd    */	       -1,
-	/* reservd    */	       -1,
-	/* BufferOver */	       USB_ST_BUF_ERR,
-	/* BuffUnder  */	       USB_ST_BUF_ERR,
-	/* Not Access */	       -1,
-	/* Not Access */	       -1
-};
-
-/* ED States */
-
-#define ED_NEW		0x00
-#define ED_UNLINK	0x01
-#define ED_OPER		0x02
-#define ED_DEL		0x04
-#define ED_URB_DEL	0x08
-
-/* usb_ohci_ed */
-struct ed {
-	__u32 hwINFO;
-	__u32 hwTailP;
-	__u32 hwHeadP;
-	__u32 hwNextED;
-
-	struct ed *ed_prev;
-	__u8 int_period;
-	__u8 int_branch;
-	__u8 int_load;
-	__u8 int_interval;
-	__u8 state;
-	__u8 type;
-	__u16 last_iso;
-	struct ed *ed_rm_list;
-
-	struct usb_device *usb_dev;
-	__u32 unused[3];
-} __attribute__((aligned(16)));
-typedef struct ed ed_t;
-
-
-/* TD info field */
-#define TD_CC	    0xf0000000
-#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
-#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
-#define TD_EC	    0x0C000000
-#define TD_T	    0x03000000
-#define TD_T_DATA0  0x02000000
-#define TD_T_DATA1  0x03000000
-#define TD_T_TOGGLE 0x00000000
-#define TD_R	    0x00040000
-#define TD_DI	    0x00E00000
-#define TD_DI_SET(X) (((X) & 0x07)<< 21)
-#define TD_DP	    0x00180000
-#define TD_DP_SETUP 0x00000000
-#define TD_DP_IN    0x00100000
-#define TD_DP_OUT   0x00080000
-
-#define TD_ISO	    0x00010000
-#define TD_DEL	    0x00020000
-
-/* CC Codes */
-#define TD_CC_NOERROR	   0x00
-#define TD_CC_CRC	   0x01
-#define TD_CC_BITSTUFFING  0x02
-#define TD_CC_DATATOGGLEM  0x03
-#define TD_CC_STALL	   0x04
-#define TD_DEVNOTRESP	   0x05
-#define TD_PIDCHECKFAIL	   0x06
-#define TD_UNEXPECTEDPID   0x07
-#define TD_DATAOVERRUN	   0x08
-#define TD_DATAUNDERRUN	   0x09
-#define TD_BUFFEROVERRUN   0x0C
-#define TD_BUFFERUNDERRUN  0x0D
-#define TD_NOTACCESSED	   0x0F
-
-
-#define MAXPSW 1
-
-struct td {
-	__u32 hwINFO;
-	__u32 hwCBP;		/* Current Buffer Pointer */
-	__u32 hwNextTD;		/* Next TD Pointer */
-	__u32 hwBE;		/* Memory Buffer End Pointer */
-
-	__u8 unused;
-	__u8 index;
-	struct ed *ed;
-	struct td *next_dl_td;
-	struct usb_device *usb_dev;
-	int transfer_len;
-	__u32 data;
-
-	__u32 unused2[2];
-} __attribute__((aligned(32)));
-typedef struct td td_t;
-
-#define OHCI_ED_SKIP	(1 << 14)
-
-/*
- * The HCCA (Host Controller Communications Area) is a 256 byte
- * structure defined in the OHCI spec. that the host controller is
- * told the base address of.  It must be 256-byte aligned.
- */
-
-#define NUM_INTS 32	/* part of the OHCI standard */
-struct ohci_hcca {
-	__u32	int_table[NUM_INTS];	/* Interrupt ED table */
-	__u16	pad1;			/* set to 0 on each frame_no change */
-	__u16	frame_no;		/* current frame number */
-	__u32	done_head;		/* info returned for an interrupt */
-	u8		reserved_for_hc[116];
-} __attribute__((aligned(256)));
-
-
-/*
- * Maximum number of root hub ports.
- */
-#define MAX_ROOT_PORTS	15	/* maximum OHCI root hub ports */
-
-/*
- * This is the structure of the OHCI controller's memory mapped I/O
- * region.  This is Memory Mapped I/O.	You must use the readl() and
- * writel() macros defined in asm/io.h to access these!!
- */
-struct ohci_regs {
-	/* control and status registers */
-	__u32	revision;
-	__u32	control;
-	__u32	cmdstatus;
-	__u32	intrstatus;
-	__u32	intrenable;
-	__u32	intrdisable;
-	/* memory pointers */
-	__u32	hcca;
-	__u32	ed_periodcurrent;
-	__u32	ed_controlhead;
-	__u32	ed_controlcurrent;
-	__u32	ed_bulkhead;
-	__u32	ed_bulkcurrent;
-	__u32	donehead;
-	/* frame counters */
-	__u32	fminterval;
-	__u32	fmremaining;
-	__u32	fmnumber;
-	__u32	periodicstart;
-	__u32	lsthresh;
-	/* Root hub ports */
-	struct	ohci_roothub_regs {
-		__u32	a;
-		__u32	b;
-		__u32	status;
-		__u32	portstatus[MAX_ROOT_PORTS];
-	} roothub;
-} __attribute__((aligned(32)));
-
-
-/* OHCI CONTROL AND STATUS REGISTER MASKS */
-
-/*
- * HcControl (control) register masks
- */
-#define OHCI_CTRL_CBSR	(3 << 0)	/* control/bulk service ratio */
-#define OHCI_CTRL_PLE	(1 << 2)	/* periodic list enable */
-#define OHCI_CTRL_IE	(1 << 3)	/* isochronous enable */
-#define OHCI_CTRL_CLE	(1 << 4)	/* control list enable */
-#define OHCI_CTRL_BLE	(1 << 5)	/* bulk list enable */
-#define OHCI_CTRL_HCFS	(3 << 6)	/* host controller functional state */
-#define OHCI_CTRL_IR	(1 << 8)	/* interrupt routing */
-#define OHCI_CTRL_RWC	(1 << 9)	/* remote wakeup connected */
-#define OHCI_CTRL_RWE	(1 << 10)	/* remote wakeup enable */
-
-/* pre-shifted values for HCFS */
-#	define OHCI_USB_RESET	(0 << 6)
-#	define OHCI_USB_RESUME	(1 << 6)
-#	define OHCI_USB_OPER	(2 << 6)
-#	define OHCI_USB_SUSPEND (3 << 6)
-
-/*
- * HcCommandStatus (cmdstatus) register masks
- */
-#define OHCI_HCR	(1 << 0)	/* host controller reset */
-#define OHCI_CLF	(1 << 1)	/* control list filled */
-#define OHCI_BLF	(1 << 2)	/* bulk list filled */
-#define OHCI_OCR	(1 << 3)	/* ownership change request */
-#define OHCI_SOC	(3 << 16)	/* scheduling overrun count */
-
-/*
- * masks used with interrupt registers:
- * HcInterruptStatus (intrstatus)
- * HcInterruptEnable (intrenable)
- * HcInterruptDisable (intrdisable)
- */
-#define OHCI_INTR_SO	(1 << 0)	/* scheduling overrun */
-#define OHCI_INTR_WDH	(1 << 1)	/* writeback of done_head */
-#define OHCI_INTR_SF	(1 << 2)	/* start frame */
-#define OHCI_INTR_RD	(1 << 3)	/* resume detect */
-#define OHCI_INTR_UE	(1 << 4)	/* unrecoverable error */
-#define OHCI_INTR_FNO	(1 << 5)	/* frame number overflow */
-#define OHCI_INTR_RHSC	(1 << 6)	/* root hub status change */
-#define OHCI_INTR_OC	(1 << 30)	/* ownership change */
-#define OHCI_INTR_MIE	(1 << 31)	/* master interrupt enable */
-
-
-/* Virtual Root HUB */
-struct virt_root_hub {
-	int devnum; /* Address of Root Hub endpoint */
-	void *dev;  /* was urb */
-	void *int_addr;
-	int send;
-	int interval;
-};
-
-/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
-
-/* destination of request */
-#define RH_INTERFACE		   0x01
-#define RH_ENDPOINT		   0x02
-#define RH_OTHER		   0x03
-
-#define RH_CLASS		   0x20
-#define RH_VENDOR		   0x40
-
-/* Requests: bRequest << 8 | bmRequestType */
-#define RH_GET_STATUS		0x0080
-#define RH_CLEAR_FEATURE	0x0100
-#define RH_SET_FEATURE		0x0300
-#define RH_SET_ADDRESS		0x0500
-#define RH_GET_DESCRIPTOR	0x0680
-#define RH_SET_DESCRIPTOR	0x0700
-#define RH_GET_CONFIGURATION	0x0880
-#define RH_SET_CONFIGURATION	0x0900
-#define RH_GET_STATE		0x0280
-#define RH_GET_INTERFACE	0x0A80
-#define RH_SET_INTERFACE	0x0B00
-#define RH_SYNC_FRAME		0x0C80
-/* Our Vendor Specific Request */
-#define RH_SET_EP		0x2000
-
-
-/* Hub port features */
-#define RH_PORT_CONNECTION	   0x00
-#define RH_PORT_ENABLE		   0x01
-#define RH_PORT_SUSPEND		   0x02
-#define RH_PORT_OVER_CURRENT	   0x03
-#define RH_PORT_RESET		   0x04
-#define RH_PORT_POWER		   0x08
-#define RH_PORT_LOW_SPEED	   0x09
-
-#define RH_C_PORT_CONNECTION	   0x10
-#define RH_C_PORT_ENABLE	   0x11
-#define RH_C_PORT_SUSPEND	   0x12
-#define RH_C_PORT_OVER_CURRENT	   0x13
-#define RH_C_PORT_RESET		   0x14
-
-/* Hub features */
-#define RH_C_HUB_LOCAL_POWER	   0x00
-#define RH_C_HUB_OVER_CURRENT	   0x01
-
-#define RH_DEVICE_REMOTE_WAKEUP	   0x00
-#define RH_ENDPOINT_STALL	   0x01
-
-#define RH_ACK			   0x01
-#define RH_REQ_ERR		   -1
-#define RH_NACK			   0x00
-
-
-/* OHCI ROOT HUB REGISTER MASKS */
-
-/* roothub.portstatus [i] bits */
-#define RH_PS_CCS	     0x00000001		/* current connect status */
-#define RH_PS_PES	     0x00000002		/* port enable status*/
-#define RH_PS_PSS	     0x00000004		/* port suspend status */
-#define RH_PS_POCI	     0x00000008		/* port over current indicator */
-#define RH_PS_PRS	     0x00000010		/* port reset status */
-#define RH_PS_PPS	     0x00000100		/* port power status */
-#define RH_PS_LSDA	     0x00000200		/* low speed device attached */
-#define RH_PS_CSC	     0x00010000		/* connect status change */
-#define RH_PS_PESC	     0x00020000		/* port enable status change */
-#define RH_PS_PSSC	     0x00040000		/* port suspend status change */
-#define RH_PS_OCIC	     0x00080000		/* over current indicator change */
-#define RH_PS_PRSC	     0x00100000		/* port reset status change */
-
-/* roothub.status bits */
-#define RH_HS_LPS	     0x00000001		/* local power status */
-#define RH_HS_OCI	     0x00000002		/* over current indicator */
-#define RH_HS_DRWE	     0x00008000		/* device remote wakeup enable */
-#define RH_HS_LPSC	     0x00010000		/* local power status change */
-#define RH_HS_OCIC	     0x00020000		/* over current indicator change */
-#define RH_HS_CRWE	     0x80000000		/* clear remote wakeup enable */
-
-/* roothub.b masks */
-#define RH_B_DR		0x0000ffff		/* device removable flags */
-#define RH_B_PPCM	0xffff0000		/* port power control mask */
-
-/* roothub.a masks */
-#define RH_A_NDP	(0xff << 0)		/* number of downstream ports */
-#define RH_A_PSM	(1 << 8)		/* power switching mode */
-#define RH_A_NPS	(1 << 9)		/* no power switching */
-#define RH_A_DT		(1 << 10)		/* device type (mbz) */
-#define RH_A_OCPM	(1 << 11)		/* over current protection mode */
-#define RH_A_NOCP	(1 << 12)		/* no over current protection */
-#define RH_A_POTPGT	(0xff << 24)		/* power on to power good time */
-
-/* urb */
-#define N_URB_TD 48
-typedef struct
-{
-	ed_t *ed;
-	__u16 length;	/* number of tds associated with this request */
-	__u16 td_cnt;	/* number of tds already serviced */
-	int   state;
-	unsigned long pipe;
-	int actual_length;
-	td_t *td[N_URB_TD];	/* list pointer to all corresponding TDs associated with this request */
-} urb_priv_t;
-#define URB_DEL 1
-
-/*
- * This is the full ohci controller description
- *
- * Note how the "proper" USB information is just
- * a subset of what the full implementation needs. (Linus)
- */
-
-
-typedef struct ohci {
-	struct ohci_hcca *hcca;		/* hcca */
-	/*dma_addr_t hcca_dma;*/
-
-	int irq;
-	int disabled;			/* e.g. got a UE, we're hung */
-	int sleeping;
-	unsigned long flags;		/* for HC bugs */
-
-	struct ohci_regs *regs; /* OHCI controller's memory */
-
-	ed_t *ed_rm_list[2];	 /* lists of all endpoints to be removed */
-	ed_t *ed_bulktail;	 /* last endpoint of bulk list */
-	ed_t *ed_controltail;	 /* last endpoint of control list */
-	int intrstatus;
-	__u32 hc_control;		/* copy of the hc control reg */
-	struct usb_device *dev[32];
-	struct virt_root_hub rh;
-
-	const char	*slot_name;
-} ohci_t;
-
-#define NUM_EDS 8		/* num of preallocated endpoint descriptors */
-
-struct ohci_device {
-	ed_t	ed[NUM_EDS];
-	int ed_cnt;
-};
-
-/* hcd */
-/* endpoint */
-static int ep_link(ohci_t * ohci, ed_t * ed);
-static int ep_unlink(ohci_t * ohci, ed_t * ed);
-static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe);
-
-/*-------------------------------------------------------------------------*/
-
-/* we need more TDs than EDs */
-#define NUM_TD 64
-
-/* +1 so we can align the storage */
-td_t gtd[NUM_TD+1];
-/* pointers to aligned storage */
-td_t *ptd;
-
-/* TDs ... */
-static inline struct td *
-td_alloc (struct usb_device *usb_dev)
-{
-	int i;
-	struct td	*td;
-
-	td = NULL;
-	for (i = 0; i < NUM_TD; i++)
-	{
-		if (ptd[i].usb_dev == NULL)
-		{
-			td = &ptd[i];
-			td->usb_dev = usb_dev;
-			break;
-		}
-	}
-
-	return td;
-}
-
-static inline void
-ed_free (struct ed *ed)
-{
-	ed->usb_dev = NULL;
-}
diff --git a/arch/powerpc/cpu/ppc4xx/usb_ohci.c b/arch/powerpc/cpu/ppc4xx/usb_ohci.c
index 27423e3779..45f0093855 100644
--- a/arch/powerpc/cpu/ppc4xx/usb_ohci.c
+++ b/arch/powerpc/cpu/ppc4xx/usb_ohci.c
@@ -782,9 +782,6 @@ static td_t * dl_reverse_done_list (ohci_t *ohci)
 				} else
 					td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2);
 			}
-#ifdef CONFIG_MPC5200
-			td_list->hwNextTD = 0;
-#endif
 		}
 
 		td_list->next_dl_td = td_rev;
diff --git a/arch/powerpc/cpu/ppc4xx/usb_ohci.h b/arch/powerpc/cpu/ppc4xx/usb_ohci.h
index 2c3dc4f99c..9e7da0d162 100644
--- a/arch/powerpc/cpu/ppc4xx/usb_ohci.h
+++ b/arch/powerpc/cpu/ppc4xx/usb_ohci.h
@@ -125,13 +125,8 @@ typedef struct td td_t;
 #define NUM_INTS 32		/* part of the OHCI standard */
 struct ohci_hcca {
 	__u32 int_table[NUM_INTS];	/* Interrupt ED table */
-#if defined(CONFIG_MPC5200)
-	__u16 pad1;		/* set to 0 on each frame_no change */
-	__u16 frame_no;		/* current frame number */
-#else
 	__u16 frame_no;		/* current frame number */
 	__u16 pad1;		/* set to 0 on each frame_no change */
-#endif
 	__u32 done_head;	/* info returned for an interrupt */
 	u8 reserved_for_hc[116];
 } __attribute__((aligned(256)));
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 3943d0e92b..2efa6240c5 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -84,13 +84,6 @@ struct arch_global_data {
 #if defined(CONFIG_E500)
 	u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32];
 #endif
-#if defined(CONFIG_MPC5xxx)
-	unsigned long ipb_clk;
-#endif
-#if defined(CONFIG_MPC512X)
-	u32 ips_clk;
-	u32 csb_clk;
-#endif /* CONFIG_MPC512X */
 	unsigned long reset_status;	/* reset status register at boot */
 #if defined(CONFIG_MPC83xx)
 	unsigned long arbiter_event_attributes;
diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h
deleted file mode 100644
index bed80aa933..0000000000
--- a/arch/powerpc/include/asm/immap_512x.h
+++ /dev/null
@@ -1,1264 +0,0 @@
-/*
- * (C) Copyright 2007-2009 DENX Software Engineering
- *
- * MPC512x Internal Memory Map
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Based on the MPC83xx header.
- */
-
-#ifndef __IMMAP_512x__
-#define __IMMAP_512x__
-
-#include <asm/types.h>
-#if defined(CONFIG_E300)
-#include <asm/e300.h>
-#endif
-
-/*
- * System reset offset (PowerPC standard)
- */
-#define EXC_OFF_SYS_RESET	0x0100
-#define	_START_OFFSET		EXC_OFF_SYS_RESET
-
-#define SPR_5121E		0x80180000
-
-/*
- * IMMRBAR - Internal Memory Register Base Address
- */
-#define CONFIG_DEFAULT_IMMR	0xFF400000	/* Default IMMR base address */
-#define IMMRBAR			0x0000		/* Register offset to immr */
-#define IMMRBAR_BASE_ADDR	0xFFF00000	/* Base address mask */
-#define IMMRBAR_RES		~(IMMRBAR_BASE_ADDR)
-
-
-#ifndef __ASSEMBLY__
-typedef struct law512x {
-	u32 bar;	/* Base Addr Register */
-	u32 ar;		/* Attributes Register */
-} law512x_t;
-
-/*
- * System configuration registers
- */
-typedef struct sysconf512x {
-	u32 immrbar;		/* Internal memory map base address register */
-	u8 res0[0x1c];
-	u32 lpbaw;		/* LP Boot Access Window */
-	u32 lpcs0aw;		/* LP CS0 Access Window */
-	u32 lpcs1aw;		/* LP CS1 Access Window */
-	u32 lpcs2aw;		/* LP CS2 Access Window */
-	u32 lpcs3aw;		/* LP CS3 Access Window */
-	u32 lpcs4aw;		/* LP CS4 Access Window */
-	u32 lpcs5aw;		/* LP CS5 Access Window */
-	u32 lpcs6aw;		/* LP CS6 Access Window */
-	u32 lpcs7aw;		/* LP CS7 Access Window */
-	u8 res1[0x1c];
-	law512x_t pcilaw[3];	/* PCI Local Access Window 0-2 Registers */
-	u8 res2[0x28];
-	law512x_t ddrlaw;	/* DDR Local Access Window */
-	u8 res3[0x18];
-	u32 mbxbar;		/* MBX Base Address */
-	u32 srambar;		/* SRAM Base Address */
-	u32 nfcbar;		/* NFC Base Address */
-	u8 res4[0x34];
-	u32 spridr;		/* System Part and Revision ID Register */
-	u32 spcr;		/* System Priority Configuration Register */
-	u8 res5[0xf8];
-} sysconf512x_t;
-
-#define LAWBAR_BAR	0xFFFFF000	/* Base address mask */
-
-/*
- * Watch Dog Timer (WDT) Registers
- */
-typedef struct wdt512x {
-	u8 res0[4];
-	u32 swcrr;		/* System watchdog control register */
-	u32 swcnr;		/* System watchdog count register */
-	u8 res1[2];
-	u16 swsrr;		/* System watchdog service register */
-	u8 res2[0xF0];
-} wdt512x_t;
-
-/*
- * RTC Module Registers
- */
-typedef struct rtclk512x {
-	u8 fixme[0x100];
-} rtclk512x_t;
-
-/*
- * General Purpose Timer
- */
-typedef struct gpt512x {
-	u8 fixme[0x100];
-} gpt512x_t;
-
-/*
- * Integrated Programmable Interrupt Controller
- */
-typedef struct ipic512x {
-	u8 fixme[0x100];
-} ipic512x_t;
-
-/*
- * System Arbiter Registers
- */
-typedef struct arbiter512x {
-	u32 acr;		/* Arbiter Configuration Register */
-	u32 atr;		/* Arbiter Timers Register */
-	u32 ater;		/* Arbiter Transfer Error Register */
-	u32 aer;		/* Arbiter Event Register */
-	u32 aidr;		/* Arbiter Interrupt Definition Register */
-	u32 amr;		/* Arbiter Mask Register */
-	u32 aeatr;		/* Arbiter Event Attributes Register */
-	u32 aeadr;		/* Arbiter Event Address Register */
-	u32 aerr;		/* Arbiter Event Response Register */
-	u8 res1[0xDC];
-} arbiter512x_t;
-
-/*
- * Reset Module
- */
-typedef struct reset512x {
-	u32 rcwl;		/* Reset Configuration Word Low Register */
-	u32 rcwh;		/* Reset Configuration Word High Register */
-	u8 res0[8];
-	u32 rsr;		/* Reset Status Register */
-	u32 rmr;		/* Reset Mode Register */
-	u32 rpr;		/* Reset protection Register */
-	u32 rcr;		/* Reset Control Register */
-	u32 rcer;		/* Reset Control Enable Register */
-	u8 res1[0xDC];
-} reset512x_t;
-
-/* RSR - Reset Status Register */
-#define RSR_SWSR	0x00002000	/* software soft reset */
-#define RSR_SWHR	0x00001000	/* software hard reset */
-#define RSR_JHRS	0x00000200	/* jtag hreset */
-#define RSR_JSRS	0x00000100	/* jtag sreset status */
-#define RSR_CSHR	0x00000010	/* checkstop reset status */
-#define RSR_SWRS	0x00000008	/* software watchdog reset status */
-#define RSR_BMRS	0x00000004	/* bus monitop reset status */
-#define RSR_SRS		0x00000002	/* soft reset status */
-#define RSR_HRS		0x00000001	/* hard reset status */
-#define RSR_RES		~(RSR_SWSR | RSR_SWHR |\
-			 RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\
-			 RSR_BMRS | RSR_SRS | RSR_HRS)
-
-/* RMR - Reset Mode Register */
-#define RMR_CSRE	0x00000001	/* checkstop reset enable */
-#define RMR_CSRE_SHIFT	0
-#define RMR_RES		(~(RMR_CSRE))
-
-/* RCR - Reset Control Register */
-#define RCR_SWHR	0x00000002	/* software hard reset */
-#define RCR_SWSR	0x00000001	/* software soft reset */
-#define RCR_RES		(~(RCR_SWHR | RCR_SWSR))
-
-/* RCER - Reset Control Enable Register */
-#define RCER_CRE	0x00000001	/* software hard reset */
-#define RCER_RES	(~(RCER_CRE))
-
-/*
- * Clock Module
- */
-typedef struct clk512x {
-	u32 spmr;		/* System PLL Mode Register */
-	u32 sccr[2];		/* System Clock Control Registers */
-	u32 scfr[2];		/* System Clock Frequency Registers */
-	u8 res0[4];
-	u32 bcr;		/* Bread Crumb Register */
-	u32 pscccr[12];		/* PSC0-11 Clock Control Registers */
-	u32 spccr;		/* SPDIF Clock Control Register */
-	u32 cccr;		/* CFM Clock Control Register */
-	u32 dccr;		/* DIU Clock Control Register */
-	u32 msccr[4];		/* MSCAN1-4 Clock Control Registers */
-	u8 res1[0x98];
-} clk512x_t;
-
-/* SPMR - System PLL Mode Register */
-#define SPMR_SPMF		0x0F000000
-#define SPMR_SPMF_SHIFT		24
-#define SPMR_CPMF		0x000F0000
-#define SPMR_CPMF_SHIFT		16
-
-/* System Clock Control Register 1 commands */
-#define CLOCK_SCCR1_CFG_EN		0x80000000
-#define CLOCK_SCCR1_LPC_EN		0x40000000
-#define CLOCK_SCCR1_NFC_EN		0x20000000
-#define CLOCK_SCCR1_PATA_EN		0x10000000
-#define CLOCK_SCCR1_PSC_EN(cn)		(0x08000000 >> (cn))
-#define CLOCK_SCCR1_PSCFIFO_EN		0x00008000
-#define CLOCK_SCCR1_SATA_EN		0x00004000
-#define CLOCK_SCCR1_FEC_EN		0x00002000
-#define CLOCK_SCCR1_TPR_EN		0x00001000
-#define CLOCK_SCCR1_PCI_EN		0x00000800
-#define CLOCK_SCCR1_DDR_EN		0x00000400
-
-/* System Clock Control Register 2 commands */
-#define CLOCK_SCCR2_DIU_EN		0x80000000
-#define CLOCK_SCCR2_AXE_EN		0x40000000
-#define CLOCK_SCCR2_MEM_EN		0x20000000
-#define CLOCK_SCCR2_USB1_EN		0x10000000
-#define CLOCK_SCCR2_USB2_EN		0x08000000
-#define CLOCK_SCCR2_I2C_EN		0x04000000
-#define CLOCK_SCCR2_BDLC_EN		0x02000000
-#define CLOCK_SCCR2_SDHC_EN		0x01000000
-#define CLOCK_SCCR2_SPDIF_EN		0x00800000
-#define CLOCK_SCCR2_MBX_BUS_EN		0x00400000
-#define CLOCK_SCCR2_MBX_EN		0x00200000
-#define CLOCK_SCCR2_MBX_3D_EN		0x00100000
-#define CLOCK_SCCR2_IIM_EN		0x00080000
-
-/* SCFR1 System Clock Frequency Register 1 */
-#ifndef SCFR1_IPS_DIV
-#define SCFR1_IPS_DIV		0x3
-#endif
-#define SCFR1_IPS_DIV_MASK	0x03800000
-#define SCFR1_IPS_DIV_SHIFT	23
-
-#define SCFR1_PCI_DIV		0x6
-#define SCFR1_PCI_DIV_MASK	0x00700000
-#define SCFR1_PCI_DIV_SHIFT	20
-
-#define SCFR1_LPC_DIV_MASK	0x00003800
-#define SCFR1_LPC_DIV_SHIFT	11
-
-#define SCFR1_NFC_DIV_MASK	0x00000700
-#define SCFR1_NFC_DIV_SHIFT	8
-
-#define SCFR1_DIU_DIV_MASK	0x000000FF
-#define SCFR1_DIU_DIV_SHIFT	0
-
-/* SCFR2 System Clock Frequency Register 2 */
-#define SCFR2_SYS_DIV		0xFC000000
-#define SCFR2_SYS_DIV_SHIFT	26
-
-/* SPCR - System Priority Configuration Register */
-#define SPCR_TBEN	0x00400000	/* E300 core time base unit enable */
-
-/*
- * Power Management Control Module
- */
-typedef struct pmc512x {
-	u8 fixme[0x100];
-} pmc512x_t;
-
-/*
- * General purpose I/O module
- */
-typedef struct gpio512x {
-	u32 gpdir;
-	u32 gpodr;
-	u32 gpdat;
-	u32 gpier;
-	u32 gpimr;
-	u32 gpicr1;
-	u32 gpicr2;
-	u8 res0[0xE4];
-} gpio512x_t;
-
-/*
- * DDR Memory Controller Memory Map
- */
-typedef struct ddr512x {
-	u32 ddr_sys_config;	/* System Configuration Register */
-	u32 ddr_time_config0;	/* Timing Configuration Register */
-	u32 ddr_time_config1;	/* Timing Configuration Register */
-	u32 ddr_time_config2;	/* Timing Configuration Register */
-	u32 ddr_command;	/* Command Register */
-	u32 ddr_compact_command;	/* Compact Command Register */
-	u32 self_refresh_cmd_0;	/* Enter/Exit Self Refresh Registers */
-	u32 self_refresh_cmd_1;	/* Enter/Exit Self Refresh Registers */
-	u32 self_refresh_cmd_2;	/* Enter/Exit Self Refresh Registers */
-	u32 self_refresh_cmd_3;	/* Enter/Exit Self Refresh Registers */
-	u32 self_refresh_cmd_4;	/* Enter/Exit Self Refresh Registers */
-	u32 self_refresh_cmd_5;	/* Enter/Exit Self Refresh Registers */
-	u32 self_refresh_cmd_6;	/* Enter/Exit Self Refresh Registers */
-	u32 self_refresh_cmd_7;	/* Enter/Exit Self Refresh Registers */
-	u32 dqs_config_offset_count;	/* DQS Config Offset Count */
-	u32 dqs_config_offset_time;	/* DQS Config Offset Time */
-	u32 DQS_delay_status;	/* DQS Delay Status */
-	u32 res0[0xF];
-	u32 prioman_config1;	/* Priority Manager Configuration */
-	u32 prioman_config2;	/* Priority Manager Configuration */
-	u32 hiprio_config;	/* High Priority Configuration */
-	u32 lut_table0_main_upper;	/* LUT0 Main Upper */
-	u32 lut_table1_main_upper;	/* LUT1 Main Upper */
-	u32 lut_table2_main_upper;	/* LUT2 Main Upper */
-	u32 lut_table3_main_upper;	/* LUT3 Main Upper */
-	u32 lut_table4_main_upper;	/* LUT4 Main Upper */
-	u32 lut_table0_main_lower;	/* LUT0 Main Lower */
-	u32 lut_table1_main_lower;	/* LUT1 Main Lower */
-	u32 lut_table2_main_lower;	/* LUT2 Main Lower */
-	u32 lut_table3_main_lower;	/* LUT3 Main Lower */
-	u32 lut_table4_main_lower;	/* LUT4 Main Lower */
-	u32 lut_table0_alternate_upper;	/* LUT0 Alternate Upper */
-	u32 lut_table1_alternate_upper; /* LUT1 Alternate Upper */
-	u32 lut_table2_alternate_upper; /* LUT2 Alternate Upper */
-	u32 lut_table3_alternate_upper; /* LUT3 Alternate Upper */
-	u32 lut_table4_alternate_upper; /* LUT4 Alternate Upper */
-	u32 lut_table0_alternate_lower; /* LUT0 Alternate Lower */
-	u32 lut_table1_alternate_lower; /* LUT1 Alternate Lower */
-	u32 lut_table2_alternate_lower; /* LUT2 Alternate Lower */
-	u32 lut_table3_alternate_lower; /* LUT3 Alternate Lower */
-	u32 lut_table4_alternate_lower; /* LUT4 Alternate Lower */
-	u32 performance_monitor_config;
-	u32 event_time_counter;
-	u32 event_time_preset;
-	u32 performance_monitor1_address_low;
-	u32 performance_monitor2_address_low;
-	u32 performance_monitor1_address_hi;
-	u32 performance_monitor2_address_hi;
-	u32 res1[2];
-	u32 performance_monitor1_read_counter;
-	u32 performance_monitor2_read_counter;
-	u32 performance_monitor1_write_counter;
-	u32 performance_monitor2_write_counter;
-	u32 granted_ack_counter0;
-	u32 granted_ack_counter1;
-	u32 granted_ack_counter2;
-	u32 granted_ack_counter3;
-	u32 granted_ack_counter4;
-	u32 cumulative_wait_counter0;
-	u32 cumulative_wait_counter1;
-	u32 cumulative_wait_counter2;
-	u32 cumulative_wait_counter3;
-	u32 cumulative_wait_counter4;
-	u32 summed_priority_counter0;
-	u32 summed_priority_counter1;
-	u32 summed_priority_counter2;
-	u32 summed_priority_counter3;
-	u32 summed_priority_counter4;
-	u32 res2[0x3AD];
-} ddr512x_t;
-
-/* MDDRC SYS CFG and Timing CFG0 Registers */
-#define MDDRC_SYS_CFG_EN	0xF0000000
-#define MDDRC_SYS_CFG_CKE_MASK	0x40000000
-#define MDDRC_SYS_CFG_CMD_MASK	0x10000000
-#define MDDRC_REFRESH_ZERO_MASK	0x0000FFFF
-
-/*
- * DDR Memory Controller Configuration settings
- */
-typedef struct ddr512x_config {
-	u32 ddr_sys_config;	/* System Configuration Register */
-	u32 ddr_time_config0;	/* Timing Configuration Register */
-	u32 ddr_time_config1;	/* Timing Configuration Register */
-	u32 ddr_time_config2;	/* Timing Configuration Register */
-} ddr512x_config_t;
-
-typedef struct sdram_conf_s {
-	unsigned long size;
-	ddr512x_config_t cfg;
-} sdram_conf_t;
-
-/*
- * DMA/Messaging Unit
- */
-typedef struct dma512x {
-	u8 fixme[0x1800];
-} dma512x_t;
-
-/*
- * PCI Software Configuration Registers
- */
-typedef struct pciconf512x {
-	u32 config_address;
-	u32 config_data;
-	u32 int_ack;
-	u8 res[116];
-} pciconf512x_t;
-
-/*
- * PCI Outbound Translation Register
- */
-typedef struct pci_outbound_window {
-	u32 potar;
-	u8 res0[4];
-	u32 pobar;
-	u8 res1[4];
-	u32 pocmr;
-	u8 res2[4];
-} pot512x_t;
-
-/* POTAR - PCI Outbound Translation Address Register */
-#define POTAR_TA_MASK	0x000fffff
-
-/* POBAR - PCI Outbound Base Address Register */
-#define POBAR_BA_MASK	0x000fffff
-
-/* POCMR - PCI Outbound Comparision Mask Register */
-#define POCMR_EN	0x80000000
-#define POCMR_IO	0x40000000	/* 0-memory space 1-I/O space */
-#define POCMR_PRE	0x20000000	/* prefetch enable */
-#define POCMR_SBS	0x00100000	/* special byte swap enable */
-#define POCMR_CM_MASK	0x000fffff
-#define POCMR_CM_4G	0x00000000
-#define POCMR_CM_2G	0x00080000
-#define POCMR_CM_1G	0x000C0000
-#define POCMR_CM_512M	0x000E0000
-#define POCMR_CM_256M	0x000F0000
-#define POCMR_CM_128M	0x000F8000
-#define POCMR_CM_64M	0x000FC000
-#define POCMR_CM_32M	0x000FE000
-#define POCMR_CM_16M	0x000FF000
-#define POCMR_CM_8M	0x000FF800
-#define POCMR_CM_4M	0x000FFC00
-#define POCMR_CM_2M	0x000FFE00
-#define POCMR_CM_1M	0x000FFF00
-#define POCMR_CM_512K	0x000FFF80
-#define POCMR_CM_256K	0x000FFFC0
-#define POCMR_CM_128K	0x000FFFE0
-#define POCMR_CM_64K	0x000FFFF0
-#define POCMR_CM_32K	0x000FFFF8
-#define POCMR_CM_16K	0x000FFFFC
-#define POCMR_CM_8K	0x000FFFFE
-#define POCMR_CM_4K	0x000FFFFF
-
-/*
- * Sequencer
- */
-typedef struct ios512x {
-	pot512x_t pot[6];
-	u8 res0[0x60];
-	u32 pmcr;
-	u8 res1[4];
-	u32 dtcr;
-	u8 res2[4];
-} ios512x_t;
-
-/*
- * PCI Controller
- */
-typedef struct pcictrl512x {
-	u32 esr;
-	u32 ecdr;
-	u32 eer;
-	u32 eatcr;
-	u32 eacr;
-	u32 eeacr;
-	u32 edlcr;
-	u32 edhcr;
-	u32 gcr;
-	u32 ecr;
-	u32 gsr;
-	u8 res0[12];
-	u32 pitar2;
-	u8 res1[4];
-	u32 pibar2;
-	u32 piebar2;
-	u32 piwar2;
-	u8 res2[4];
-	u32 pitar1;
-	u8 res3[4];
-	u32 pibar1;
-	u32 piebar1;
-	u32 piwar1;
-	u8 res4[4];
-	u32 pitar0;
-	u8 res5[4];
-	u32 pibar0;
-	u8 res6[4];
-	u32 piwar0;
-	u8 res7[132];
-} pcictrl512x_t;
-
-
-/* PITAR - PCI Inbound Translation Address Register
- */
-#define PITAR_TA_MASK	0x000fffff
-
-/* PIBAR - PCI Inbound Base/Extended Address Register
- */
-#define PIBAR_MASK	0xffffffff
-#define PIEBAR_EBA_MASK	0x000fffff
-
-/* PIWAR - PCI Inbound Windows Attributes Register
- */
-#define PIWAR_EN	0x80000000
-#define PIWAR_SBS	0x40000000
-#define PIWAR_PF	0x20000000
-#define PIWAR_RTT_MASK	0x000f0000
-#define PIWAR_RTT_NO_SNOOP 0x00040000
-#define PIWAR_RTT_SNOOP	0x00050000
-#define PIWAR_WTT_MASK	0x0000f000
-#define PIWAR_WTT_NO_SNOOP 0x00004000
-#define PIWAR_WTT_SNOOP	0x00005000
-
-/*
- * MSCAN
- */
-typedef struct mscan512x {
-	u8 fixme[0x100];
-} mscan512x_t;
-
-/*
- * BDLC
- */
-typedef struct bdlc512x {
-	u8 fixme[0x100];
-} bdlc512x_t;
-
-/*
- * SDHC
- */
-typedef struct sdhc512x {
-	u8 fixme[0x100];
-} sdhc512x_t;
-
-/*
- * SPDIF
- */
-typedef struct spdif512x {
-	u8 fixme[0x100];
-} spdif512x_t;
-
-/*
- * I2C
- */
-typedef struct i2c512x_dev {
-	volatile u32 madr;		/* I2Cn + 0x00 */
-	volatile u32 mfdr;		/* I2Cn + 0x04 */
-	volatile u32 mcr;		/* I2Cn + 0x08 */
-	volatile u32 msr;		/* I2Cn + 0x0C */
-	volatile u32 mdr;		/* I2Cn + 0x10 */
-	u8 res0[0x0C];
-} i2c512x_dev_t;
-
-/* Number of I2C buses */
-#define I2C_BUS_CNT	3
-
-typedef struct i2c512x {
-	i2c512x_dev_t dev[I2C_BUS_CNT];
-	volatile u32 icr;
-	volatile u32 mifr;
-	u8 res0[0x98];
-} i2c512x_t;
-
-/* I2Cn control register bits */
-#define I2C_EN		0x80
-#define I2C_IEN		0x40
-#define I2C_STA		0x20
-#define I2C_TX		0x10
-#define I2C_TXAK	0x08
-#define I2C_RSTA	0x04
-#define I2C_INIT_MASK	(I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
-
-/* I2Cn status register bits */
-#define I2C_CF		0x80
-#define I2C_AAS		0x40
-#define I2C_BB		0x20
-#define I2C_AL		0x10
-#define I2C_SRW		0x04
-#define I2C_IF		0x02
-#define I2C_RXAK	0x01
-
-/*
- * AXE
- */
-typedef struct axe512x {
-	u8 fixme[0x100];
-} axe512x_t;
-
-/*
- * DIU
- */
-typedef struct diu512x {
-	u8 fixme[0x100];
-} diu512x_t;
-
-/*
- * CFM
- */
-typedef struct cfm512x {
-	u8 fixme[0x100];
-} cfm512x_t;
-
-/*
- * FEC
- */
-typedef struct fec512x {
-	u32	fec_id;		/* FEC_ID register */
-	u32	ievent;		/* Interrupt event register */
-	u32	imask;		/* Interrupt mask register */
-	u32	reserved_01;
-	u32	r_des_active;	/* Receive ring updated flag */
-	u32	x_des_active;	/* Transmit ring updated flag */
-	u32	reserved_02[3];
-	u32	ecntrl;		/* Ethernet control register */
-	u32	reserved_03[6];
-	u32	mii_data;	/* MII data register */
-	u32	mii_speed;	/* MII speed register */
-	u32	reserved_04[7];
-	u32	mib_control;	/* MIB control/status register */
-	u32	reserved_05[7];
-	u32	r_cntrl;	/* Receive control register */
-	u32	r_hash;		/* Receive hash */
-	u32	reserved_06[14];
-	u32	x_cntrl;	/* Transmit control register */
-	u32	reserved_07[7];
-	u32	paddr1;		/* Physical address low */
-	u32	paddr2;		/* Physical address high + type field */
-	u32	op_pause;	/* Opcode + pause duration */
-	u32	reserved_08[10];
-	u32	iaddr1;		/* Upper 32 bits of individual hash table */
-	u32	iaddr2;		/* Lower 32 bits of individual hash table */
-	u32	gaddr1;		/* Upper 32 bits of group hash table */
-	u32	gaddr2;		/* Lower 32 bits of group hash table */
-	u32	reserved_09[7];
-	u32	x_wmrk;		/* Transmit FIFO watermark */
-	u32	reserved_10;
-	u32	r_bound;	/* End of RAM */
-	u32	r_fstart;	/* Receive FIFO start address */
-	u32	reserved_11[11];
-	u32	r_des_start;	/* Beginning of receive descriptor ring */
-	u32	x_des_start;	/* Pointer to beginning of transmit descriptor ring */
-	u32	r_buff_size;	/* Receive buffer size */
-	u32	reserved_12[26];
-	u32	dma_control;	/* DMA control for IP bus, AMBA IF + DMA revision */
-	u32	reserved_13[2];
-
-	u32	mib[128];	/* MIB Block Counters */
-
-	u32	fifo[256];	/*  used by FEC, can only be accessed by DMA */
-} fec512x_t;
-
-/*
- * ULPI
- */
-typedef struct ulpi512x {
-	u8 fixme[0x600];
-} ulpi512x_t;
-
-/*
- * UTMI
- */
-typedef struct utmi512x {
-	u8 fixme[0x3000];
-} utmi512x_t;
-
-/*
- * PCI DMA
- */
-typedef struct pcidma512x {
-	u8 fixme[0x300];
-} pcidma512x_t;
-
-/*
- * IO Control
- */
-typedef struct ioctrl512x {
-	u32	io_control_mem;			/* MEM pad ctrl reg */
-	u32	io_control_gp;			/* GP pad ctrl reg */
-	u32	io_control_lpc_clk;		/* LPC_CLK pad ctrl reg */
-	u32	io_control_lpc_oe;		/* LPC_OE pad ctrl reg */
-	u32	io_control_lpc_rw;		/* LPC_R/W pad ctrl reg */
-	u32	io_control_lpc_ack;		/* LPC_ACK pad ctrl reg */
-	u32	io_control_lpc_cs0;		/* LPC_CS0 pad ctrl reg */
-	u32	io_control_nfc_ce0;		/* NFC_CE0 pad ctrl reg */
-	u32	io_control_lpc_cs1;		/* LPC_CS1 pad ctrl reg */
-	u32	io_control_lpc_cs2;		/* LPC_CS2 pad ctrl reg */
-	u32	io_control_lpc_ax03;		/* LPC_AX03 pad ctrl reg */
-	u32	io_control_emb_ax02;		/* EMB_AX02 pad ctrl reg */
-	u32	io_control_emb_ax01;		/* EMB_AX01 pad ctrl reg */
-	u32	io_control_emb_ax00;		/* EMB_AX00 pad ctrl reg */
-	u32	io_control_emb_ad31;		/* EMB_AD31 pad ctrl reg */
-	u32	io_control_emb_ad30;		/* EMB_AD30 pad ctrl reg */
-	u32	io_control_emb_ad29;		/* EMB_AD29 pad ctrl reg */
-	u32	io_control_emb_ad28;		/* EMB_AD28 pad ctrl reg */
-	u32	io_control_emb_ad27;		/* EMB_AD27 pad ctrl reg */
-	u32	io_control_emb_ad26;		/* EMB_AD26 pad ctrl reg */
-	u32	io_control_emb_ad25;		/* EMB_AD25 pad ctrl reg */
-	u32	io_control_emb_ad24;		/* EMB_AD24 pad ctrl reg */
-	u32	io_control_emb_ad23;		/* EMB_AD23 pad ctrl reg */
-	u32	io_control_emb_ad22;		/* EMB_AD22 pad ctrl reg */
-	u32	io_control_emb_ad21;		/* EMB_AD21 pad ctrl reg */
-	u32	io_control_emb_ad20;		/* EMB_AD20 pad ctrl reg */
-	u32	io_control_emb_ad19;		/* EMB_AD19 pad ctrl reg */
-	u32	io_control_emb_ad18;		/* EMB_AD18 pad ctrl reg */
-	u32	io_control_emb_ad17;		/* EMB_AD17 pad ctrl reg */
-	u32	io_control_emb_ad16;		/* EMB_AD16 pad ctrl reg */
-	u32	io_control_emb_ad15;		/* EMB_AD15 pad ctrl reg */
-	u32	io_control_emb_ad14;		/* EMB_AD14 pad ctrl reg */
-	u32	io_control_emb_ad13;		/* EMB_AD13 pad ctrl reg */
-	u32	io_control_emb_ad12;		/* EMB_AD12 pad ctrl reg */
-	u32	io_control_emb_ad11;		/* EMB_AD11 pad ctrl reg */
-	u32	io_control_emb_ad10;		/* EMB_AD10 pad ctrl reg */
-	u32	io_control_emb_ad09;		/* EMB_AD09 pad ctrl reg */
-	u32	io_control_emb_ad08;		/* EMB_AD08 pad ctrl reg */
-	u32	io_control_emb_ad07;		/* EMB_AD07 pad ctrl reg */
-	u32	io_control_emb_ad06;		/* EMB_AD06 pad ctrl reg */
-	u32	io_control_emb_ad05;		/* EMB_AD05 pad ctrl reg */
-	u32	io_control_emb_ad04;		/* EMB_AD04 pad ctrl reg */
-	u32	io_control_emb_ad03;		/* EMB_AD03 pad ctrl reg */
-	u32	io_control_emb_ad02;		/* EMB_AD02 pad ctrl reg */
-	u32	io_control_emb_ad01;		/* EMB_AD01 pad ctrl reg */
-	u32	io_control_emb_ad00;		/* EMB_AD00 pad ctrl reg */
-	u32	io_control_pata_ce1;		/* PATA_CE1 pad ctrl reg */
-	u32	io_control_pata_ce2;		/* PATA_CE2 pad ctrl reg */
-	u32	io_control_pata_isolate;	/* PATA_ISOLATE pad ctrl reg */
-	u32	io_control_pata_ior;		/* PATA_IOR pad ctrl reg */
-	u32	io_control_pata_iow;		/* PATA_IOW pad ctrl reg */
-	u32	io_control_pata_iochrdy;	/* PATA_IOCHRDY pad ctrl reg */
-	u32	io_control_pata_intrq;		/* PATA_INTRQ pad ctrl reg */
-	u32	io_control_pata_drq;		/* PATA_DRQ pad ctrl reg */
-	u32	io_control_pata_dack;		/* PATA_DACK pad ctrl reg */
-	u32	io_control_nfc_wp;		/* NFC_WP pad ctrl reg */
-	u32	io_control_nfc_rb;		/* NFC_RB pad ctrl reg */
-	u32	io_control_nfc_ale;		/* NFC_ALE pad ctrl reg */
-	u32	io_control_nfc_cle;		/* NFC_CLE pad ctrl reg */
-	u32	io_control_nfc_we;		/* NFC_WE pad ctrl reg */
-	u32	io_control_nfc_re;		/* NFC_RE pad ctrl reg */
-	u32	io_control_pci_ad31;		/* PCI_AD31 pad ctrl reg */
-	u32	io_control_pci_ad30;		/* PCI_AD30 pad ctrl reg */
-	u32	io_control_pci_ad29;		/* PCI_AD29 pad ctrl reg */
-	u32	io_control_pci_ad28;		/* PCI_AD28 pad ctrl reg */
-	u32	io_control_pci_ad27;		/* PCI_AD27 pad ctrl reg */
-	u32	io_control_pci_ad26;		/* PCI_AD26 pad ctrl reg */
-	u32	io_control_pci_ad25;		/* PCI_AD25 pad ctrl reg */
-	u32	io_control_pci_ad24;		/* PCI_AD24 pad ctrl reg */
-	u32	io_control_pci_ad23;		/* PCI_AD23 pad ctrl reg */
-	u32	io_control_pci_ad22;		/* PCI_AD22 pad ctrl reg */
-	u32	io_control_pci_ad21;		/* PCI_AD21 pad ctrl reg */
-	u32	io_control_pci_ad20;		/* PCI_AD20 pad ctrl reg */
-	u32	io_control_pci_ad19;		/* PCI_AD19 pad ctrl reg */
-	u32	io_control_pci_ad18;		/* PCI_AD18 pad ctrl reg */
-	u32	io_control_pci_ad17;		/* PCI_AD17 pad ctrl reg */
-	u32	io_control_pci_ad16;		/* PCI_AD16 pad ctrl reg */
-	u32	io_control_pci_ad15;		/* PCI_AD15 pad ctrl reg */
-	u32	io_control_pci_ad14;		/* PCI_AD14 pad ctrl reg */
-	u32	io_control_pci_ad13;		/* PCI_AD13 pad ctrl reg */
-	u32	io_control_pci_ad12;		/* PCI_AD12 pad ctrl reg */
-	u32	io_control_pci_ad11;		/* PCI_AD11 pad ctrl reg */
-	u32	io_control_pci_ad10;		/* PCI_AD10 pad ctrl reg */
-	u32	io_control_pci_ad09;		/* PCI_AD09 pad ctrl reg */
-	u32	io_control_pci_ad08;		/* PCI_AD08 pad ctrl reg */
-	u32	io_control_pci_ad07;		/* PCI_AD07 pad ctrl reg */
-	u32	io_control_pci_ad06;		/* PCI_AD06 pad ctrl reg */
-	u32	io_control_pci_ad05;		/* PCI_AD05 pad ctrl reg */
-	u32	io_control_pci_ad04;		/* PCI_AD04 pad ctrl reg */
-	u32	io_control_pci_ad03;		/* PCI_AD03 pad ctrl reg */
-	u32	io_control_pci_ad02;		/* PCI_AD02 pad ctrl reg */
-	u32	io_control_pci_ad01;		/* PCI_AD01 pad ctrl reg */
-	u32	io_control_pci_ad00;		/* PCI_AD00 pad ctrl reg */
-	u32	io_control_pci_cbe0;		/* PCI_CBE0 pad ctrl reg */
-	u32	io_control_pci_cbe1;		/* PCI_CBE1 pad ctrl reg */
-	u32	io_control_pci_cbe2;		/* PCI_CBE2 pad ctrl reg */
-	u32	io_control_pci_cbe3;		/* PCI_CBE3 pad ctrl reg */
-	u32	io_control_pci_grant2;		/* PCI_GRANT2 pad ctrl reg */
-	u32	io_control_pci_req2;		/* PCI_REQ2 pad ctrl reg */
-	u32	io_control_pci_grant1;		/* PCI_GRANT1 pad ctrl reg */
-	u32	io_control_pci_req1;		/* PCI_REQ1 pad ctrl reg */
-	u32	io_control_pci_grant0;		/* PCI_GRANT0 pad ctrl reg */
-	u32	io_control_pci_req0;		/* PCI_REQ0 pad ctrl reg */
-	u32	io_control_pci_inta;		/* PCI_INTA pad ctrl reg */
-	u32	io_control_pci_clk;		/* PCI_CLK pad ctrl reg */
-	u32	io_control_pci_rst;		/* PCI_RST- pad ctrl reg */
-	u32	io_control_pci_frame;		/* PCI_FRAME pad ctrl reg */
-	u32	io_control_pci_idsel;		/* PCI_IDSEL pad ctrl reg */
-	u32	io_control_pci_devsel;		/* PCI_DEVSEL pad ctrl reg */
-	u32	io_control_pci_irdy;		/* PCI_IRDY pad ctrl reg */
-	u32	io_control_pci_trdy;		/* PCI_TRDY pad ctrl reg */
-	u32	io_control_pci_stop;		/* PCI_STOP pad ctrl reg */
-	u32	io_control_pci_par;		/* PCI_PAR pad ctrl reg */
-	u32	io_control_pci_perr;		/* PCI_PERR pad ctrl reg */
-	u32	io_control_pci_serr;		/* PCI_SERR pad ctrl reg */
-	u32	io_control_spdif_txclk;		/* SPDIF_TXCLK pad ctrl reg */
-	u32	io_control_spdif_tx;		/* SPDIF_TX pad ctrl reg */
-	u32	io_control_spdif_rx;		/* SPDIF_RX pad ctrl reg */
-	u32	io_control_i2c0_scl;		/* I2C0_SCL pad ctrl reg */
-	u32	io_control_i2c0_sda;		/* I2C0_SDA pad ctrl reg */
-	u32	io_control_i2c1_scl;		/* I2C1_SCL pad ctrl reg */
-	u32	io_control_i2c1_sda;		/* I2C1_SDA pad ctrl reg */
-	u32	io_control_i2c2_scl;		/* I2C2_SCL pad ctrl reg */
-	u32	io_control_i2c2_sda;		/* I2C2_SDA pad ctrl reg */
-	u32	io_control_irq0;		/* IRQ0 pad ctrl reg */
-	u32	io_control_irq1;		/* IRQ1 pad ctrl reg */
-	u32	io_control_can1_tx;		/* CAN1_TX pad ctrl reg */
-	u32	io_control_can2_tx;		/* CAN2_TX pad ctrl reg */
-	u32	io_control_j1850_tx;		/* J1850_TX pad ctrl reg */
-	u32	io_control_j1850_rx;		/* J1850_RX pad ctrl reg */
-	u32	io_control_psc_mclk_in;		/* PSC_MCLK_IN pad ctrl reg */
-	u32	io_control_psc0_0;		/* PSC0_0 pad ctrl reg */
-	u32	io_control_psc0_1;		/* PSC0_1 pad ctrl reg */
-	u32	io_control_psc0_2;		/* PSC0_2 pad ctrl reg */
-	u32	io_control_psc0_3;		/* PSC0_3 pad ctrl reg */
-	u32	io_control_psc0_4;		/* PSC0_4 pad ctrl reg */
-	u32	io_control_psc1_0;		/* PSC1_0 pad ctrl reg */
-	u32	io_control_psc1_1;		/* PSC1_1 pad ctrl reg */
-	u32	io_control_psc1_2;		/* PSC1_2 pad ctrl reg */
-	u32	io_control_psc1_3;		/* PSC1_3 pad ctrl reg */
-	u32	io_control_psc1_4;		/* PSC1_4 pad ctrl reg */
-	u32	io_control_psc2_0;		/* PSC2_0 pad ctrl reg */
-	u32	io_control_psc2_1;		/* PSC2_1 pad ctrl reg */
-	u32	io_control_psc2_2;		/* PSC2_2 pad ctrl reg */
-	u32	io_control_psc2_3;		/* PSC2_3 pad ctrl reg */
-	u32	io_control_psc2_4;		/* PSC2_4 pad ctrl reg */
-	u32	io_control_psc3_0;		/* PSC3_0 pad ctrl reg */
-	u32	io_control_psc3_1;		/* PSC3_1 pad ctrl reg */
-	u32	io_control_psc3_2;		/* PSC3_2 pad ctrl reg */
-	u32	io_control_psc3_3;		/* PSC3_3 pad ctrl reg */
-	u32	io_control_psc3_4;		/* PSC3_4 pad ctrl reg */
-	u32	io_control_psc4_0;		/* PSC4_0 pad ctrl reg */
-	u32	io_control_psc4_1;		/* PSC4_1 pad ctrl reg */
-	u32	io_control_psc4_2;		/* PSC4_2 pad ctrl reg */
-	u32	io_control_psc4_3;		/* PSC4_3 pad ctrl reg */
-	u32	io_control_psc4_4;		/* PSC4_4 pad ctrl reg */
-	u32	io_control_psc5_0;		/* PSC5_0 pad ctrl reg */
-	u32	io_control_psc5_1;		/* PSC5_1 pad ctrl reg */
-	u32	io_control_psc5_2;		/* PSC5_2 pad ctrl reg */
-	u32	io_control_psc5_3;		/* PSC5_3 pad ctrl reg */
-	u32	io_control_psc5_4;		/* PSC5_4 pad ctrl reg */
-	u32	io_control_psc6_0;		/* PSC6_0 pad ctrl reg */
-	u32	io_control_psc6_1;		/* PSC6_1 pad ctrl reg */
-	u32	io_control_psc6_2;		/* PSC6_2 pad ctrl reg */
-	u32	io_control_psc6_3;		/* PSC6_3 pad ctrl reg */
-	u32	io_control_psc6_4;		/* PSC6_4 pad ctrl reg */
-	u32	io_control_psc7_0;		/* PSC7_0 pad ctrl reg */
-	u32	io_control_psc7_1;		/* PSC7_1 pad ctrl reg */
-	u32	io_control_psc7_2;		/* PSC7_2 pad ctrl reg */
-	u32	io_control_psc7_3;		/* PSC7_3 pad ctrl reg */
-	u32	io_control_psc7_4;		/* PSC7_4 pad ctrl reg */
-	u32	io_control_psc8_0;		/* PSC8_0 pad ctrl reg */
-	u32	io_control_psc8_1;		/* PSC8_1 pad ctrl reg */
-	u32	io_control_psc8_2;		/* PSC8_2 pad ctrl reg */
-	u32	io_control_psc8_3;		/* PSC8_3 pad ctrl reg */
-	u32	io_control_psc8_4;		/* PSC8_4 pad ctrl reg */
-	u32	io_control_psc9_0;		/* PSC9_0 pad ctrl reg */
-	u32	io_control_psc9_1;		/* PSC9_1 pad ctrl reg */
-	u32	io_control_psc9_2;		/* PSC9_2 pad ctrl reg */
-	u32	io_control_psc9_3;		/* PSC9_3 pad ctrl reg */
-	u32	io_control_psc9_4;		/* PSC9_4 pad ctrl reg */
-	u32	io_control_psc10_0;		/* PSC10_0 pad ctrl reg */
-	u32	io_control_psc10_1;		/* PSC10_1 pad ctrl reg */
-	u32	io_control_psc10_2;		/* PSC10_2 pad ctrl reg */
-	u32	io_control_psc10_3;		/* PSC10_3 pad ctrl reg */
-	u32	io_control_psc10_4;		/* PSC10_4 pad ctrl reg */
-	u32	io_control_psc11_0;		/* PSC11_0 pad ctrl reg */
-	u32	io_control_psc11_1;		/* PSC11_1 pad ctrl reg */
-	u32	io_control_psc11_2;		/* PSC11_2 pad ctrl reg */
-	u32	io_control_psc11_3;		/* PSC11_3 pad ctrl reg */
-	u32	io_control_psc11_4;		/* PSC11_4 pad ctrl reg */
-	u32	io_control_ckstp_out;		/* CKSTP_OUT pad ctrl reg */
-	u32	io_control_usb_phy_drvvbus;	/* USB2_DRVVBUS pad ctrl reg */
-	u8	reserved[0x0cfc];		/* fill to 4096 bytes size */
-} ioctrl512x_t;
-
-/* IO pin fields */
-#define IO_PIN_FMUX(v)	((v) << 7)	/* pin function */
-#define IO_PIN_HOLD(v)	((v) << 5)	/* hold time, pci only */
-#define IO_PIN_PUD(v)	((v) << 4)	/* if PUE, 0=pull-down, 1=pull-up */
-#define IO_PIN_PUE(v)	((v) << 3)	/* pull up/down enable */
-#define IO_PIN_ST(v)	((v) << 2)	/* schmitt trigger */
-#define IO_PIN_DS(v)	((v))		/* slew rate */
-
-typedef struct iopin_t {
-	int p_offset;		/* offset from IOCTL_MEM_OFFSET */
-	int nr_pins;		/* number of pins to set this way */
-	int bit_or;		/* or in the value instead of overwrite */
-	u_long val;		/* value to write or or */
-}iopin_t;
-
-void iopin_initialize(iopin_t *,int);
-
-/*
- * support to adjust individual parts of the IO pin setup
- */
-
-#define IO_PIN_OVER_EACH	(1 << 0) /* for compatibility */
-#define IO_PIN_OVER_FMUX	(1 << 1)
-#define IO_PIN_OVER_HOLD	(1 << 2)
-#define IO_PIN_OVER_PULL	(1 << 3)
-#define IO_PIN_OVER_STRIG	(1 << 4)
-#define IO_PIN_OVER_DRVSTR	(1 << 5)
-
-void iopin_initialize_bits(iopin_t *, int);
-
-/*
- * IIM
- */
-typedef struct iim512x {
-	u32 stat;		/* IIM status register */
-	u32 statm;		/* IIM status IRQ mask */
-	u32 err;		/* IIM errors register */
-	u32 emask;		/* IIM error IRQ mask  */
-	u32 fctl;		/* IIM fuse control register */
-	u32 ua;			/* IIM upper address register */
-	u32 la;			/* IIM lower address register */
-	u32 sdat;		/* IIM explicit sense data */
-	u8 res0[0x08];
-	u32 prg_p;		/* IIM program protection register */
-	u8 res1[0x10];
-	u32 divide;		/* IIM divide factor register */
-	u8 res2[0x7c0];
-	u32 fbac0;		/* IIM fuse bank 0 prot (for Freescale use) */
-	u32 fb0w0[0x1f];	/* IIM fuse bank 0 data (for Freescale use) */
-	u8 res3[0x380];
-	u32 fbac1;		/* IIM fuse bank 1 protection */
-	u32 fb1w1[0x01f];	/* IIM fuse bank 1 data */
-	u8 res4[0x380];
-} iim512x_t;
-
-/*
- * LPC
- */
-typedef struct lpc512x {
-	u32	cs_cfg[8];	/* Chip Select N Configuration Registers
-				   No dedicated entry for CS Boot as == CS0 */
-	u32	cs_cr;		/* Chip Select Control Register */
-	u32	cs_sr;		/* Chip Select Status Register */
-	u32	cs_bcr;		/* Chip Select Burst Control Register */
-	u32	cs_dccr;	/* Chip Select Deadcycle Control Register */
-	u32	cs_hccr;	/* Chip Select Holdcycle Control Register */
-	u32	altr;		/* Address Latch Timing Register */
-	u8	res0[0xc8];
-	u32	sclpc_psr;	/* SCLPC Packet Size Register */
-	u32	sclpc_sar;	/* SCLPC Start Address Register */
-	u32	sclpc_cr;	/* SCLPC Control Register */
-	u32	sclpc_er;	/* SCLPC Enable Register */
-	u32	sclpc_nar;	/* SCLPC NextAddress Register */
-	u32	sclpc_sr;	/* SCLPC Status Register */
-	u32	sclpc_bdr;	/* SCLPC Bytes Done Register */
-	u32	emb_scr;	/* EMB Share Counter Register */
-	u32	emb_pcr;	/* EMB Pause Control Register */
-	u8	res1[0x1c];
-	u32	lpc_fdwr;	/* LPC RX/TX FIFO Data Word Register */
-	u32	lpc_fsr;	/* LPC RX/TX FIFO Status Register */
-	u32	lpc_cr;		/* LPC RX/TX FIFO Control Register */
-	u32	lpc_ar;		/* LPC RX/TX FIFO Alarm Register */
-	u8	res2[0xb0];
-} lpc512x_t;
-
-/*
- * PATA
- */
-typedef struct pata512x {
-	/* LOCAL Registers */
-	u32 pata_time1;		/* Time register 1: PIO and tx timing parameter */
-	u32 pata_time2;		/* Time register 2: PIO timing parameter */
-	u32 pata_time3;		/* Time register 3: PIO and MDMA timing parameter */
-	u32 pata_time4;		/* Time register 4: MDMA and UDMA timing parameter */
-	u32 pata_time5;		/* Time register 5: UDMA timing parameter */
-	u32 pata_time6;		/* Time register 6: UDMA timing parameter */
-	u32 pata_fifo_data32;   /* 32bit wide dataport to/from FIFO */
-	u32 pata_fifo_data16;   /* 16bit wide dataport to/from FIFO */
-	u32 pata_fifo_fill;	/* FIFO filling in halfwords (READONLY)*/
-	u32 pata_ata_control;   /* ATA Interface control register */
-	u32 pata_irq_pending;   /* Interrupt pending register (READONLY) */
-	u32 pata_irq_enable;	/* Interrupt enable register */
-	u32 pata_irq_clear;	/* Interrupt clear register (WRITEONLY)*/
-	u32 pata_fifo_alarm;	/* fifo alarm threshold */
-	u32 res1[0x1A];
-	/* DRIVE Registers */
-	u32 pata_drive_data;	/* drive data register*/
-	u32 pata_drive_features;/* drive features register */
-	u32 pata_drive_sectcnt; /* drive sector count register */
-	u32 pata_drive_sectnum; /* drive sector number register */
-	u32 pata_drive_cyllow;  /* drive cylinder low register */
-	u32 pata_drive_cylhigh; /* drive cylinder high register */
-	u32 pata_drive_dev_head;/* drive device head register */
-	u32 pata_drive_command; /* write = drive command, read = drive status reg */
-	u32 res2[0x06];
-	u32 pata_drive_alt_stat;/* write = drive control, read = drive alt status reg */
-	u32 res3[0x09];
-} pata512x_t;
-
-/*
- * PSC
- */
-typedef struct psc512x {
-	volatile u8	mode;		/* PSC + 0x00 */
-	volatile u8	res0[3];
-	union {				/* PSC + 0x04 */
-		volatile u16	status;
-		volatile u16	clock_select;
-	} sr_csr;
-#define psc_status	sr_csr.status
-#define psc_clock_select sr_csr.clock_select
-	volatile u16	res1;
-	volatile u8	command;	/* PSC + 0x08 */
-	volatile u8	res2[3];
-	union {				/* PSC + 0x0c */
-		volatile u8	buffer_8;
-		volatile u16	buffer_16;
-		volatile u32	buffer_32;
-	} buffer;
-#define psc_buffer_8	buffer.buffer_8
-#define psc_buffer_16	buffer.buffer_16
-#define psc_buffer_32	buffer.buffer_32
-	union {				/* PSC + 0x10 */
-		volatile u8	ipcr;
-		volatile u8	acr;
-	} ipcr_acr;
-#define psc_ipcr	ipcr_acr.ipcr
-#define psc_acr		ipcr_acr.acr
-	volatile u8	res3[3];
-	union {				/* PSC + 0x14 */
-		volatile u16	isr;
-		volatile u16	imr;
-	} isr_imr;
-#define psc_isr		isr_imr.isr
-#define psc_imr		isr_imr.imr
-	volatile u16	res4;
-	volatile u8	ctur;		/* PSC + 0x18 */
-	volatile u8	res5[3];
-	volatile u8	ctlr;		/* PSC + 0x1c */
-	volatile u8	res6[3];
-	volatile u32	ccr;		/* PSC + 0x20 */
-	volatile u8	res7[12];
-	volatile u8	ivr;		/* PSC + 0x30 */
-	volatile u8	res8[3];
-	volatile u8	ip;		/* PSC + 0x34 */
-	volatile u8	res9[3];
-	volatile u8	op1;		/* PSC + 0x38 */
-	volatile u8	res10[3];
-	volatile u8	op0;		/* PSC + 0x3c */
-	volatile u8	res11[3];
-	volatile u32	sicr;		/* PSC + 0x40 */
-	volatile u8	res12[60];
-	volatile u32	tfcmd;		/* PSC + 0x80 */
-	volatile u32	tfalarm;	/* PSC + 0x84 */
-	volatile u32	tfstat;		/* PSC + 0x88 */
-	volatile u32	tfintstat;	/* PSC + 0x8C */
-	volatile u32	tfintmask;	/* PSC + 0x90 */
-	volatile u32	tfcount;	/* PSC + 0x94 */
-	volatile u16	tfwptr;		/* PSC + 0x98 */
-	volatile u16	tfrptr;		/* PSC + 0x9A */
-	volatile u32	tfsize;		/* PSC + 0x9C */
-	volatile u8	res13[28];
-	union {				/* PSC + 0xBC */
-		volatile u8	buffer_8;
-		volatile u16	buffer_16;
-		volatile u32	buffer_32;
-	} tfdata_buffer;
-#define tfdata_8	tfdata_buffer.buffer_8
-#define tfdata_16	tfdata_buffer.buffer_16
-#define tfdata_32	tfdata_buffer.buffer_32
-
-	volatile u32	rfcmd;		/* PSC + 0xC0 */
-	volatile u32	rfalarm;	/* PSC + 0xC4 */
-	volatile u32	rfstat;		/* PSC + 0xC8 */
-	volatile u32	rfintstat;	/* PSC + 0xCC */
-	volatile u32	rfintmask;	/* PSC + 0xD0 */
-	volatile u32	rfcount;	/* PSC + 0xD4 */
-	volatile u16	rfwptr;		/* PSC + 0xD8 */
-	volatile u16	rfrptr;		/* PSC + 0xDA */
-	volatile u32	rfsize;		/* PSC + 0xDC */
-	volatile u8	res18[28];
-	union {				/* PSC + 0xFC */
-		volatile u8	buffer_8;
-		volatile u16	buffer_16;
-		volatile u32	buffer_32;
-	} rfdata_buffer;
-#define rfdata_8	rfdata_buffer.buffer_8
-#define rfdata_16	rfdata_buffer.buffer_16
-#define rfdata_32	rfdata_buffer.buffer_32
-} psc512x_t;
-
-/* PSC FIFO Command values */
-#define PSC_FIFO_RESET_SLICE		0x80
-#define PSC_FIFO_ENABLE_SLICE		0x01
-
-/* PSC FIFO Controller Command values */
-#define FIFOC_ENABLE_CLOCK_GATE		0x01
-#define FIFOC_DISABLE_CLOCK_GATE	0x00
-
-/* PSC FIFO status */
-#define PSC_FIFO_EMPTY			0x01
-
-/* PSC Command values */
-#define PSC_RX_ENABLE		0x01
-#define PSC_RX_DISABLE		0x02
-#define PSC_TX_ENABLE		0x04
-#define PSC_TX_DISABLE		0x08
-#define PSC_SEL_MODE_REG_1	0x10
-#define PSC_RST_RX		0x20
-#define PSC_RST_TX		0x30
-#define PSC_RST_ERR_STAT	0x40
-#define PSC_RST_BRK_CHG_INT	0x50
-#define PSC_START_BRK		0x60
-#define PSC_STOP_BRK		0x70
-
-/* PSC status register bits */
-#define PSC_SR_CDE		0x0080
-#define PSC_SR_TXEMP		0x0800
-#define PSC_SR_OE		0x1000
-#define PSC_SR_PE		0x2000
-#define PSC_SR_FE		0x4000
-#define PSC_SR_RB		0x8000
-
-/* PSC mode fields */
-#define PSC_MODE_5_BITS		0x00
-#define PSC_MODE_6_BITS		0x01
-#define PSC_MODE_7_BITS		0x02
-#define PSC_MODE_8_BITS		0x03
-#define PSC_MODE_PAREVEN	0x00
-#define PSC_MODE_PARODD		0x04
-#define PSC_MODE_PARFORCE	0x08
-#define PSC_MODE_PARNONE	0x10
-#define PSC_MODE_ENTIMEOUT	0x20
-#define PSC_MODE_RXRTS		0x80
-#define PSC_MODE_1_STOPBIT	0x07
-
-/*
- * FIFOC
- */
-typedef struct fifoc512x {
-	u32 fifoc_cmd;
-	u32 fifoc_int;
-	u32 fifoc_dma;
-	u32 fifoc_axe;
-	u32 fifoc_debug;
-	u8 fixme[0xEC];
-} fifoc512x_t;
-
-/*
- * Centralized FIFO Controller has internal memory for all 12 PSCs FIFOs
- *
- * NOTE: individual PSC units are free to use whatever area (and size) of the
- * FIFOC internal memory, so make sure memory areas for FIFO slices used by
- * different PSCs do not overlap!
- *
- * Overall size of FIFOC memory is not documented in the MPC5121e RM, but
- * tests indicate that it is 1024 words total.
- *
- * *_TX_SIZE and *_RX_SIZE is the number of 4-byte words for FIFO slice.
- */
-#define FIFOC_PSC0_TX_SIZE	0x04
-#define FIFOC_PSC0_TX_ADDR	0x0
-#define FIFOC_PSC0_RX_SIZE	0x04
-#define FIFOC_PSC0_RX_ADDR	0x10
-
-#define FIFOC_PSC1_TX_SIZE	0x04
-#define FIFOC_PSC1_TX_ADDR	0x20
-#define FIFOC_PSC1_RX_SIZE	0x04
-#define FIFOC_PSC1_RX_ADDR	0x30
-
-#define FIFOC_PSC2_TX_SIZE	0x04
-#define FIFOC_PSC2_TX_ADDR	0x40
-#define FIFOC_PSC2_RX_SIZE	0x04
-#define FIFOC_PSC2_RX_ADDR	0x50
-
-#define FIFOC_PSC3_TX_SIZE	0x04
-#define FIFOC_PSC3_TX_ADDR	0x60
-#define FIFOC_PSC3_RX_SIZE	0x04
-#define FIFOC_PSC3_RX_ADDR	0x70
-
-#define FIFOC_PSC4_TX_SIZE	0x04
-#define FIFOC_PSC4_TX_ADDR	0x80
-#define FIFOC_PSC4_RX_SIZE	0x04
-#define FIFOC_PSC4_RX_ADDR	0x90
-
-#define FIFOC_PSC5_TX_SIZE	0x04
-#define FIFOC_PSC5_TX_ADDR	0xa0
-#define FIFOC_PSC5_RX_SIZE	0x04
-#define FIFOC_PSC5_RX_ADDR	0xb0
-
-#define FIFOC_PSC6_TX_SIZE	0x04
-#define FIFOC_PSC6_TX_ADDR	0xc0
-#define FIFOC_PSC6_RX_SIZE	0x04
-#define FIFOC_PSC6_RX_ADDR	0xd0
-
-#define FIFOC_PSC7_TX_SIZE	0x04
-#define FIFOC_PSC7_TX_ADDR	0xe0
-#define FIFOC_PSC7_RX_SIZE	0x04
-#define FIFOC_PSC7_RX_ADDR	0xf0
-
-#define FIFOC_PSC8_TX_SIZE	0x04
-#define FIFOC_PSC8_TX_ADDR	0x100
-#define FIFOC_PSC8_RX_SIZE	0x04
-#define FIFOC_PSC8_RX_ADDR	0x110
-
-#define FIFOC_PSC9_TX_SIZE	0x04
-#define FIFOC_PSC9_TX_ADDR	0x120
-#define FIFOC_PSC9_RX_SIZE	0x04
-#define FIFOC_PSC9_RX_ADDR	0x130
-
-#define FIFOC_PSC10_TX_SIZE	0x04
-#define FIFOC_PSC10_TX_ADDR	0x140
-#define FIFOC_PSC10_RX_SIZE	0x04
-#define FIFOC_PSC10_RX_ADDR	0x150
-
-#define FIFOC_PSC11_TX_SIZE	0x04
-#define FIFOC_PSC11_TX_ADDR	0x160
-#define FIFOC_PSC11_RX_SIZE	0x04
-#define FIFOC_PSC11_RX_ADDR	0x170
-
-/*
- * SATA
- */
-typedef struct sata512x {
-	u8 fixme[0x2000];
-} sata512x_t;
-
-typedef struct immap {
-	sysconf512x_t		sysconf;	/* System configuration */
-	u8			res0[0x700];
-	wdt512x_t		wdt;		/* Watch Dog Timer (WDT) */
-	rtclk512x_t		rtc;		/* Real Time Clock Module */
-	gpt512x_t		gpt;		/* General Purpose Timer */
-	ipic512x_t		ipic;		/* Integrated Programmable Interrupt Controller */
-	arbiter512x_t		arbiter;	/* CSB Arbiter */
-	reset512x_t		reset;		/* Reset Module */
-	clk512x_t		clk;		/* Clock Module */
-	pmc512x_t		pmc;		/* Power Management Control Module */
-	gpio512x_t		gpio;		/* General purpose I/O module */
-	u8			res1[0x100];
-	mscan512x_t		mscan;		/* MSCAN */
-	bdlc512x_t		bdlc;		/* BDLC */
-	sdhc512x_t		sdhc;		/* SDHC */
-	spdif512x_t		spdif;		/* SPDIF */
-	i2c512x_t		i2c;		/* I2C Controllers */
-	u8			res2[0x800];
-	axe512x_t		axe;		/* AXE */
-	diu512x_t		diu;		/* Display Interface Unit */
-	cfm512x_t		cfm;		/* Clock Frequency Measurement */
-	u8			res3[0x500];
-	fec512x_t		fec;		/* Fast Ethernet Controller */
-	ulpi512x_t		ulpi;		/* USB ULPI */
-	u8			res4[0xa00];
-	utmi512x_t		utmi;		/* USB UTMI */
-	u8			res5[0x1000];
-	pcidma512x_t		pci_dma;	/* PCI DMA */
-	pciconf512x_t		pci_conf;	/* PCI Configuration */
-	u8			res6[0x80];
-	ios512x_t		ios;		/* PCI Sequencer */
-	pcictrl512x_t		pci_ctrl;	/* PCI Controller Control and Status */
-	u8			res7[0xa00];
-	ddr512x_t		mddrc;		/* Multi-port DDR Memory Controller */
-	ioctrl512x_t		io_ctrl;	/* IO Control */
-	iim512x_t		iim;		/* IC Identification module */
-	u8			res8[0x4000];
-	lpc512x_t		lpc;		/* LocalPlus Controller */
-	pata512x_t		pata;		/* Parallel ATA */
-	u8			res9[0xd00];
-	psc512x_t		psc[12];	/* PSCs */
-	u8			res10[0x300];
-	fifoc512x_t		fifoc;		/* FIFO Controller */
-	u8			res11[0x2000];
-	dma512x_t		dma;		/* DMA */
-	u8			res12[0xa800];
-	sata512x_t		sata;		/* Serial ATA */
-	u8			res13[0xde000];
-} immap_t;
-
-/* provide interface to get PATA base address */
-static inline u32 get_pata_base (void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	return (u32)(&im->pata);
-}
-#endif	/* __ASSEMBLY__ */
-
-#define CONFIG_SYS_MPC512x_USB1_OFFSET   0x4000
-#define CONFIG_SYS_MPC512x_USB1_ADDR \
-			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB1_OFFSET)
-
-#define IIM_BASE_ADDR	(CONFIG_SYS_IMMR + offsetof(immap_t, iim))
-
-#endif /* __IMMAP_512x__ */
diff --git a/arch/powerpc/include/asm/mpc512x.h b/arch/powerpc/include/asm/mpc512x.h
deleted file mode 100644
index 9167a57544..0000000000
--- a/arch/powerpc/include/asm/mpc512x.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * include/asm-ppc/mpc512x.h
- *
- * Prototypes, etc. for the Freescale MPC512x embedded cpu chips
- *
- * 2009 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASMPPC_MPC512X_H
-#define __ASMPPC_MPC512X_H
-
-/*
- * macros for manipulating CSx_START/STOP
- */
-#define CSAW_START(start)	((start) & 0xFFFF0000)
-#define CSAW_STOP(start, size)	(((start) + (size) - 1) >> 16)
-
-/*
- * Inlines
- */
-
-/*
- * According to MPC5121e RM, configuring local access windows should
- * be followed by a dummy read of the config register that was
- * modified last and an isync.
- */
-static inline void sync_law(volatile void *addr)
-{
-	in_be32(addr);
-	__asm__ __volatile__ ("isync");
-}
-
-/*
- * Prototypes
- */
-extern long int fixed_sdram(ddr512x_config_t *mddrc_config,
-				u32 *dram_init_seq, int seq_sz);
-extern int mpc5121_diu_init(void);
-extern void ide_set_reset(int idereset);
-
-#endif /* __ASMPPC_MPC512X_H */
diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h
index f34e859720..31fa7dbd2f 100644
--- a/arch/powerpc/include/asm/ppc.h
+++ b/arch/powerpc/include/asm/ppc.h
@@ -25,11 +25,6 @@
 	defined(CONFIG_MPC866_FAMILY) || defined(CONFIG_MPC885_FAMILY)
 # define CONFIG_MPC86x 1
 #endif
-#elif defined(CONFIG_MPC5xxx)
-#include <mpc5xxx.h>
-#elif defined(CONFIG_MPC512X)
-#include <asm/immap_512x.h>
-#endif
 #ifdef CONFIG_MPC86xx
 #include <mpc86xx.h>
 #include <asm/immap_86xx.h>
@@ -58,9 +53,6 @@
 #if defined(CONFIG_8xx)
 uint get_immr(uint);
 #endif
-#if defined(CONFIG_MPC5xxx)
-uint get_svr(void);
-#endif
 uint get_pvr(void);
 uint get_svr(void);
 uint rd_ic_cst(void);
@@ -71,7 +63,6 @@ void wr_dc_cst(uint);
 void wr_dc_adr(uint);
 
 #if defined(CONFIG_4xx)	|| \
-	defined(CONFIG_MPC5xxx)	|| \
 	defined(CONFIG_MPC85xx)	|| \
 	defined(CONFIG_MPC86xx)	|| \
 	defined(CONFIG_MPC83xx)
@@ -100,10 +91,6 @@ void ddr_enable_ecc(unsigned int dram_size);
 #endif
 #endif
 
-#if defined(CONFIG_MPC5xxx)
-int	prt_mpc5xxx_clks(void);
-#endif
-
 #if defined(CONFIG_MPC85xx)
 typedef MPC85xx_SYS_INFO sys_info_t;
 void get_sys_info(sys_info_t *);
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 88adb26e2e..6bbb8ca14d 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -38,24 +38,6 @@ obj-$(CONFIG_CMD_KGDB) += kgdb.o
 obj-$(CONFIG_IDE) += ide.o
 obj-y	+= stack.o
 obj-y	+= time.o
-
-# Don't include the MPC5xxx special memcpy into the
-# SPL U-Boot image. memcpy is used in the SPL NOR
-# flash driver. And we need the real, fast memcpy
-# here. We have no problems with unaligned access.
-ifndef CONFIG_SPL_BUILD
-# Workaround for local bus unaligned access problems
-# on MPC512x and MPC5200
-ifdef CONFIG_MPC512X
-AFLAGS_ppcstring.o += -Dmemcpy=__memcpy
-obj-y += memcpy_mpc5200.o
-endif
-ifdef CONFIG_MPC5200
-AFLAGS_ppcstring.o += -Dmemcpy=__memcpy
-obj-y += memcpy_mpc5200.o
-endif
-endif
-
 endif # not minimal
 
 ifdef CONFIG_SPL_BUILD
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index 17c5ed173c..42a6afbc31 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -283,10 +283,6 @@ static void set_clocks_in_mhz (bd_t *kbd)
 		kbd->bi_sccfreq /= 1000000L;
 		kbd->bi_vco	/= 1000000L;
 #endif
-#if defined(CONFIG_MPC5xxx)
-		kbd->bi_ipbfreq /= 1000000L;
-		kbd->bi_pcifreq /= 1000000L;
-#endif /* CONFIG_MPC5xxx */
 	}
 }
 
diff --git a/arch/powerpc/lib/memcpy_mpc5200.c b/arch/powerpc/lib/memcpy_mpc5200.c
deleted file mode 100644
index 7e5a005789..0000000000
--- a/arch/powerpc/lib/memcpy_mpc5200.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * (C) Copyright 2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * This is a workaround for issues on the MPC5200, where unaligned
- * 32-bit-accesses to the local bus will deliver corrupted data. This
- * happens for example when trying to use memcpy() from an odd NOR
- * flash address; the behaviour can be also seen when using "md" on an
- * odd NOR flash address (but there it is not a bug in U-Boot, which
- * only shows the behaviour of this processor).
- *
- * For memcpy(), we test if either the source or the target address
- * are not 32 bit aligned, and - if so - if the source address is in
- * NOR flash: in this case we perform a byte-wise (slow) then; for
- * aligned operations of non-flash areas we use the optimized (fast)
- * real __memcpy().  This way we minimize the performance impact of
- * this workaround.
- *
- */
-
-#include <common.h>
-#include <flash.h>
-#include <linux/types.h>
-
-void *memcpy(void *trg, const void *src, size_t len)
-{
-	extern void* __memcpy(void *, const void *, size_t);
-	char *s = (char *)src;
-	char *t = (char *)trg;
-	void *dest = (void *)trg;
-
-	/*
-	 * Check is source address is in flash:
-	 * If not, we use the fast assembler code
-	 */
-	if (((((unsigned long)s & 3) == 0)	/* source aligned  */
-		&&				/*	AND	   */
-	     (((unsigned long)t & 3) == 0))	/* target aligned, */
-		||				/*	or	   */
-	    (addr2info((ulong)s) == NULL)) {	/* source not in flash */
-		return __memcpy(trg, src, len);
-	}
-
-	/*
-	 * Copying from flash, perform byte by byte copy.
-	 */
-	while (len-- > 0)
-		*t++ = *s++;
-
-	return dest;
-}
diff --git a/board/a3m071/Kconfig b/board/a3m071/Kconfig
deleted file mode 100644
index 444c450d8a..0000000000
--- a/board/a3m071/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_A3M071
-
-config SYS_BOARD
-	default "a3m071"
-
-config SYS_CONFIG_NAME
-	default "a3m071"
-
-endif
diff --git a/board/a3m071/MAINTAINERS b/board/a3m071/MAINTAINERS
deleted file mode 100644
index 975107d2c0..0000000000
--- a/board/a3m071/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-A3M071 BOARD
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	board/a3m071/
-F:	include/configs/a3m071.h
-F:	configs/a3m071_defconfig
-F:	configs/a4m2k_defconfig
diff --git a/board/a3m071/Makefile b/board/a3m071/Makefile
deleted file mode 100644
index 4e31e33936..0000000000
--- a/board/a3m071/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= a3m071.o
diff --git a/board/a3m071/README b/board/a3m071/README
deleted file mode 100644
index 112c47b60d..0000000000
--- a/board/a3m071/README
+++ /dev/null
@@ -1,80 +0,0 @@
-------------------------------------------------------------------------
-A3M071 board support
-------------------------------------------------------------------------
-
-
-SPL NOR flash support:
-----------------------
-To boot fast into the OS (Linux), this board port integrates the SPL
-framework. This means, that a special, stripped-down version of
-U-Boot runs in the beginning. In the case of the A3M071 board, this
-SPL U-Boot version is less than 16 KiB big. This SPL U-Boot can either
-boot the OS (Linux) or a "real", full-blown U-Boot. This detection
-on whether to boot Linux or U-Boot is done by using the "boot_os"
-environment variable. If "boot_os" is set to "yes", Linux will be
-loaded and booted from the SPL U-Boot version. Otherwise, the
-full-blown U-Boot version will be loaded and run.
-
-Enabling Linux booting:
------------------------
-From U-Boot:
-=> setenv boot_os yes
-=> saveenv
-
-From Linux:
-$ fw_setenv boot_os yes
-
-Enabling U-Boot booting:
-------------------------
-From U-Boot:
-=> setenv boot_os no
-=> saveenv
-
-From Linux:
-$ fw_setenv boot_os no
-
-
-Preparing Linux image(s) for booting from SPL U-Boot:
------------------------------------------------------
-To boot the Linux kernel from the SPL, the DT blob (fdt) needs to get
-prepard/patched first. U-Boot usually inserts some dynamic values into
-the DT binary (blob), e.g. autodetected memory size, MAC addresses,
-clocks speeds etc. To generate this patched DT blob, you can use
-the following command:
-
-1. Load fdt blob to SDRAM:
-=> tftp 1800000 a3m071/a3m071.dtb
-
-2. Set bootargs as desired for Linux booting (e.g. flash_mtd):
-=> run mtdargs addip2 addtty
-
-3. Use "fdt" commands to patch the DT blob:
-=> fdt addr 1800000
-=> fdt boardsetup
-=> fdt chosen
-
-4. Display patched DT blob (optional):
-=> fdt print
-
-5. Save fdt to NOR flash:
-=> erase fc180000 fc07ffff
-=> cp.b 1800000 fc180000 10000
-
-All this can be integrated into an environment command:
-=> setenv upd_fdt 'tftp 1800000 a3m071/a3m071.dtb;run mtdargs addip addtty; \
-	fdt addr 1800000;fdt boardsetup;fdt chosen;erase fc180000 fc07ffff; \
-	cp.b 1800000 fc180000 10000'
-=> saveenv
-
-After this, only "run upd_fdt" needs to get called to load, patch
-and save the DT blob into NOR flash.
-
-Additionally, the Linux kernel image has to be saved uncompressed in
-its uImage file (and not gzip compressed). This can be done with this
-command:
-
-$ mkimage -A ppc -O linux -T kernel -C none -a 0 -e 0 \
-	-n "Linux Kernel Image" -d vmlinux.bin uImage.uncompressed
-
-------------------------------------------------------------------------
-Stefan Roese, 2012-08-23
diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c
deleted file mode 100644
index 7e16aaf4b2..0000000000
--- a/board/a3m071/a3m071.c
+++ /dev/null
@@ -1,479 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2006
- * MicroSys GmbH
- *
- * Copyright 2012-2013 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <miiphy.h>
-#include <linux/compiler.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_A4M2K
-#include "is46r16320d.h"
-#else
-#include "mt46v16m16-75.h"
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if !defined(CONFIG_SYS_RAMBOOT) && \
-	(defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
-static void sdram_start(int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-	long control = SDRAM_CONTROL | hi_addr_bit;
-
-	/* unlock mode register */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
-
-	/* precharge all banks */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
-
-#ifdef SDRAM_DDR
-	/* set mode register: extended mode */
-	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
-
-	/* set mode register: reset DLL */
-	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
-#endif
-
-	/* precharge all banks */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
-
-	/* auto refresh */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
-
-	/* set mode register */
-	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
-
-	/* normal operation */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
-
-	/*
-	 * Wait a short while for the DLL to lock before accessing
-	 * the SDRAM
-	 */
-	udelay(100);
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced dram_init does NOT make real use
- * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
- * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
- */
-int dram_init(void)
-{
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-	uint svr, pvr;
-#if !defined(CONFIG_SYS_RAMBOOT) && \
-	(defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);	/* 2GB at 0x0 */
-	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000);	/* disabled */
-
-	/* setup config registers */
-	out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
-	out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
-
-#ifdef SDRAM_DDR
-	/* set tap delay */
-	out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
-			 0x13 + __builtin_ffs(dramsize >> 20) - 1);
-	} else {
-		out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0);	/* disabled */
-	}
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
-	if (dramsize >= 0x13)
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	else
-		dramsize = 0;
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
-	if (dramsize2 >= 0x13)
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	else
-		dramsize2 = 0;
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	svr = get_svr();
-	pvr = get_pvr();
-	if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
-		out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
-
-	gd->ram_size = dramsize + dramsize2;
-
-	return 0;
-}
-
-static void get_revisions(int *failsavelevel, int *digiboardversion,
-	int *fpgaversion)
-{
-	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
-	u8 val;
-
-	/* read digitalboard-version from TMR[2..4] */
-	val = 0;
-	val |= (gpt->gpt2.sr & (1 << (31 - 23))) ? (1) : 0;
-	val |= (gpt->gpt3.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
-	val |= (gpt->gpt4.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
-	*digiboardversion = val;
-
-	/*
-	 * A4M2K only supports digiboardversion. No failsavelevel and
-	 * fpgaversion here.
-	 */
-#if !defined(CONFIG_A4M2K)
-	/*
-	 * Figure out failsavelevel
-	 * see ticket dsvk#59
-	 */
-	*failsavelevel = 0;	/* 0=failsave, 1=board ok, 2=fpga ok */
-
-	if (*digiboardversion == 0) {
-		*failsavelevel = 1;	/* digiboard-version ok */
-
-		/* read fpga-version from TMR[5..7] */
-		val = 0;
-		val |= (gpt->gpt5.sr & (1 << (31 - 23))) ? (1) : 0;
-		val |= (gpt->gpt6.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
-		val |= (gpt->gpt7.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
-		*fpgaversion = val;
-
-		if (*fpgaversion == 1)
-			*failsavelevel = 2;	/* fpga-version ok */
-	}
-#endif
-}
-
-/*
- * This function is called from the SPL U-Boot version for
- * early init stuff, that needs to be done for OS (e.g. Linux)
- * booting. Doing it later in the real U-Boot would not work
- * in case that the SPL U-Boot boots Linux directly.
- */
-void spl_board_init(void)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-	struct mpc5xxx_mmap_ctl *mm =
-		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
-
-#if defined(CONFIG_A4M2K)
-	/* enable CS3 and CS5 (FPGA) */
-	setbits_be32(&mm->ipbi_ws_ctrl, (1 << 19) | (1 << 21));
-#else
-	int digiboardversion;
-	int failsavelevel;
-	int fpgaversion;
-	u32 val;
-
-	get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
-
-	val = in_be32(&mm->ipbi_ws_ctrl);
-
-	/* first clear bits 19..21 (CS3...5) */
-	val &= ~((1 << 19) | (1 << 20) | (1 << 21));
-	if (failsavelevel == 2) {
-		/* FPGA ok */
-		val |= (1 << 19) | (1 << 21);
-	}
-
-	if (failsavelevel >= 1) {
-		/* at least digiboard-version ok */
-		val |= (1 << 20);
-	}
-
-	/* And write new value back to register */
-	out_be32(&mm->ipbi_ws_ctrl, val);
-
-
-	/* Setup pin multiplexing */
-	if (failsavelevel == 2) {
-		/* fpga-version ok */
-#if defined(CONFIG_SYS_GPS_PORT_CONFIG_2)
-		out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG_2);
-#endif
-	} else if (failsavelevel == 1) {
-		/* digiboard-version ok - fpga not */
-#if defined(CONFIG_SYS_GPS_PORT_CONFIG_1)
-		out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG_1);
-#endif
-	} else {
-		/* full failsave-mode */
-#if defined(CONFIG_SYS_GPS_PORT_CONFIG)
-		out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
-#endif
-	}
-#endif
-
-	/*
-	 * Setup gpio_wkup_7 as watchdog AS INPUT to disable it - see
-	 * ticket #60
-	 *
-	 * MPC5XXX_WU_GPIO_DIR direction is already 0 (INPUT)
-	 * set bit 0(msb) to 1
-	 */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_WDOG_GPIO_PIN);
-
-#if defined(CONFIG_A4M2K)
-	/* Setup USB[x] as MPCDiag[0..3] GPIO outputs */
-
-	/* set USB0,6,7,8 (MPCDiag[0..3]) direction to output */
-	gpio->simple_ddr |= 1 << (31 - 15);
-	gpio->simple_ddr |= 1 << (31 - 14);
-	gpio->simple_ddr |= 1 << (31 - 13);
-	gpio->simple_ddr |= 1 << (31 - 12);
-
-	/* enable USB0,6,7,8 (MPCDiag[0..3]) as GPIO */
-	gpio->simple_gpioe |= 1 << (31 - 15);
-	gpio->simple_gpioe |= 1 << (31 - 14);
-	gpio->simple_gpioe |= 1 << (31 - 13);
-	gpio->simple_gpioe |= 1 << (31 - 12);
-
-	/* Setup PSC2[0..2] as STSLED[0..2] GPIO outputs */
-
-	/* set PSC2[0..2] (STSLED[0..2]) direction to output */
-	gpio->simple_ddr |= 1 << (31 - 27);
-	gpio->simple_ddr |= 1 << (31 - 26);
-	gpio->simple_ddr |= 1 << (31 - 25);
-
-	/* enable PSC2[0..2] (STSLED[0..2]) as GPIO */
-	gpio->simple_gpioe |= 1 << (31 - 27);
-	gpio->simple_gpioe |= 1 << (31 - 26);
-	gpio->simple_gpioe |= 1 << (31 - 25);
-
-	/* Setup PSC6[2] as MRST2 self reset GPIO output */
-
-	/* set PSC6[2]/IRDA_TX (MRST2) direction to output */
-	gpio->simple_ddr |= 1 << (31 - 3);
-
-	/* set PSC6[2]/IRDA_TX (MRST2) output as open drain */
-	gpio->simple_ode |= 1 << (31 - 3);
-
-	/* set PSC6[2]/IRDA_TX (MRST2) output as default high */
-	gpio->simple_dvo |= 1 << (31 - 3);
-
-	/* enable PSC6[2]/IRDA_TX (MRST2) as GPIO */
-	gpio->simple_gpioe |= 1 << (31 - 3);
-
-	/* Setup PSC6[3] as HARNSSCD harness code GPIO input */
-
-	/* set PSC6[3]/IR_USB_CLK (HARNSSCD) direction to input */
-	gpio->simple_ddr |= 0 << (31 - 2);
-
-	/* enable PSC6[3]/IR_USB_CLK (HARNSSCD) as GPIO */
-	gpio->simple_gpioe |= 1 << (31 - 2);
-#else
-	/* setup GPIOs for status-leds if needed - see ticket #57 */
-	if (failsavelevel > 0) {
-		/* digiboard-version is OK */
-		/* LED is LOW ACTIVE - so deactivate by set output to 1 */
-		gpio->simple_dvo |= 1 << (31 - 12);
-		gpio->simple_dvo |= 1 << (31 - 13);
-		/* set GPIO direction to output */
-		gpio->simple_ddr |= 1 << (31 - 12);
-		gpio->simple_ddr |= 1 << (31 - 13);
-		/* open drain config is set to "normal output" at reset */
-		/* gpio->simple_ode &=~ ( 1 << (31-12) ); */
-		/* gpio->simple_ode &=~ ( 1 << (31-13) ); */
-		/* enable as GPIO */
-		gpio->simple_gpioe |= 1 << (31 - 12);
-		gpio->simple_gpioe |= 1 << (31 - 13);
-	}
-
-	/* setup fpga irq - see ticket #65 */
-	if (failsavelevel > 1) {
-		/*
-		 * The main irq initialisation is done in interrupts.c
-		 * mpc5xxx_init_irq
-		 */
-		struct mpc5xxx_intr *intr =
-		    (struct mpc5xxx_intr *)(MPC5XXX_ICTL);
-
-		setbits_be32(&intr->ctrl, 0x08C01801);
-
-		/*
-		 * The MBAR+0x0524 Bit 21:23 CSe are ignored here due to the
-		 * already cleared (intr_ctrl) MBAR+0x0510 ECLR[0] bit above
-		 */
-	}
-#endif
-}
-
-int checkboard(void)
-{
-	int digiboardversion;
-	int failsavelevel;
-	int fpgaversion;
-
-	get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
-
-#ifdef CONFIG_A4M2K
-	puts("Board: A4M2K\n");
-	printf("       digiboard IO version %u\n", digiboardversion);
-#else
-	puts("Board: A3M071\n");
-	printf("Rev:   failsave level       %u\n", failsavelevel);
-	printf("       digiboard IO version %u\n", digiboardversion);
-	if (failsavelevel > 0)	/* only if fpga-version red */
-		printf("       fpga IO version      %u\n", fpgaversion);
-#endif
-
-	return 0;
-}
-
-/* miscellaneous platform dependent initialisations */
-int misc_init_r(void)
-{
-	/* adjust flash start and offset to detected values */
-	gd->bd->bi_flashstart = flash_info[0].start[0];
-	gd->bd->bi_flashoffset = 0;
-
-	/* adjust mapping */
-	out_be32((void *)MPC5XXX_BOOTCS_START,
-		 START_REG(gd->bd->bi_flashstart));
-	out_be32((void *)MPC5XXX_CS0_START, START_REG(gd->bd->bi_flashstart));
-	out_be32((void *)MPC5XXX_BOOTCS_STOP,
-		 STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
-	out_be32((void *)MPC5XXX_CS0_STOP,
-		 STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
-
-	return 0;
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-#ifdef CONFIG_SPL_OS_BOOT
-/*
- * A3M071 specific implementation of spl_start_uboot()
- *
- * RETURN
- * 0 if booting into OS is selected (default)
- * 1 if booting into U-Boot is selected
- */
-int spl_start_uboot(void)
-{
-	char s[8];
-
-	env_init();
-	getenv_f("boot_os", s, sizeof(s));
-	if ((s != NULL) && (*s == '1' || *s == 'y' || *s == 'Y' ||
-			    *s == 't' || *s == 'T'))
-		return 0;
-
-	return 1;
-}
-#endif
-
-#if defined(CONFIG_HW_WATCHDOG)
-static int watchdog_toggle;
-
-void hw_watchdog_reset(void)
-{
-	int val;
-
-	/*
-	 * Check if watchdog is enabled via user command
-	 */
-	if ((gd->flags & GD_FLG_RELOC) && watchdog_toggle) {
-		/* Set direction to output */
-		setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_WDOG_GPIO_PIN);
-
-		/*
-		 * Toggle watchdog output
-		 */
-		val = (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
-		       CONFIG_WDOG_GPIO_PIN);
-		if (val) {
-			clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O,
-				     CONFIG_WDOG_GPIO_PIN);
-		} else {
-			setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O,
-				     CONFIG_WDOG_GPIO_PIN);
-		}
-	}
-}
-
-int do_wdog_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	if (argc != 2)
-		goto usage;
-
-	if (strncmp(argv[1], "on", 2) == 0)
-		watchdog_toggle = 1;
-	else if (strncmp(argv[1], "off", 3) == 0)
-		watchdog_toggle = 0;
-	else
-		goto usage;
-
-	return 0;
-usage:
-	printf("Usage: wdogtoggle %s\n", cmdtp->usage);
-	return 1;
-}
-
-U_BOOT_CMD(
-	wdogtoggle, CONFIG_SYS_MAXARGS, 2, do_wdog_toggle,
-	"toggle GPIO pin to service watchdog",
-	"[on/off] - Switch watchdog toggling via GPIO pin on/off"
-);
-#endif
diff --git a/board/a3m071/is46r16320d.h b/board/a3m071/is46r16320d.h
deleted file mode 100644
index 981359f22b..0000000000
--- a/board/a3m071/is46r16320d.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR		/* is DDR */
-
-#if defined(CONFIG_MPC5200)
-/* Settings for XLB = 132 MHz */
-/* see is46r16320d datasheet and MPC5200UM chap. 8.6.1. */
-
-/* SDRAM Config Standard timing */
-#define SDRAM_MODE	0x008d0000
-#define SDRAM_EMODE	0x40010000
-#define SDRAM_CONTROL	0x70430f00
-#define SDRAM_CONFIG1	0x33622930
-#define SDRAM_CONFIG2	0x46670000
-#define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/a3m071/mt46v16m16-75.h b/board/a3m071/mt46v16m16-75.h
deleted file mode 100644
index 8f428306fe..0000000000
--- a/board/a3m071/mt46v16m16-75.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR		/* is DDR */
-
-#if defined(CONFIG_MPC5200)
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x704f0f00
-#define SDRAM_CONFIG1	0x73722930
-#define SDRAM_CONFIG2	0x47770000
-#define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/a4m072/Kconfig b/board/a4m072/Kconfig
deleted file mode 100644
index ba5447fb9a..0000000000
--- a/board/a4m072/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_A4M072
-
-config SYS_BOARD
-	default "a4m072"
-
-config SYS_CONFIG_NAME
-	default "a4m072"
-
-endif
diff --git a/board/a4m072/MAINTAINERS b/board/a4m072/MAINTAINERS
deleted file mode 100644
index 83dc59e87f..0000000000
--- a/board/a4m072/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-A4M072 BOARD
-M:	Sergei Poselenov <sposelenov@emcraft.com>
-S:	Maintained
-F:	board/a4m072/
-F:	include/configs/a4m072.h
-F:	configs/a4m072_defconfig
diff --git a/board/a4m072/Makefile b/board/a4m072/Makefile
deleted file mode 100644
index 2a40e5799e..0000000000
--- a/board/a4m072/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= a4m072.o
diff --git a/board/a4m072/a4m072.c b/board/a4m072/a4m072.c
deleted file mode 100644
index 6f0d4489a2..0000000000
--- a/board/a4m072/a4m072.c
+++ /dev/null
@@ -1,479 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2010
- * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <libfdt.h>
-#include <netdev.h>
-#include <led-display.h>
-#include <linux/err.h>
-
-#include "mt46v32m16.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-	long control = SDRAM_CONTROL | hi_addr_bit;
-
-	/* unlock mode register */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set mode register: extended mode */
-	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
-	__asm__ volatile ("sync");
-
-	/* set mode register: reset DLL */
-	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
-	__asm__ volatile ("sync");
-#endif
-
-	/* precharge all banks */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
-	__asm__ volatile ("sync");
-
-	/* auto refresh */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
-	__asm__ volatile ("sync");
-
-	/* set mode register */
-	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
-	__asm__ volatile ("sync");
-
-	/* normal operation */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
-	__asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced dram_init does NOT make real use
- *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- *            is something else than 0x00000000.
- */
-
-int dram_init(void)
-{
-	ulong dramsize = 0;
-	uint svr, pvr;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
-	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
-	out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set tap delay */
-	out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
-	__asm__ volatile ("sync");
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20)) {
-		dramsize = 0;
-	}
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
-				 0x13 + __builtin_ffs(dramsize >> 20) - 1);
-	} else {
-		out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
-	if (dramsize >= 0x13) {
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	} else {
-		dramsize = 0;
-	}
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	svr = get_svr();
-	pvr = get_pvr();
-	if ((SVR_MJREV(svr) >= 2) &&
-	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
-
-		out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
-		__asm__ volatile ("sync");
-	}
-
-	gd->ram_size = dramsize;
-
-	return 0;
-}
-
-int checkboard (void)
-{
-	puts ("Board: A4M072\n");
-	return 0;
-}
-
-#ifdef	CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-int board_eth_init(bd_t *bis)
-{
-	int rv, num_if = 0;
-
-	/* Initialize TSECs first */
-	if ((rv = cpu_eth_init(bis)) >= 0)
-		num_if += rv;
-	else
-		printf("ERROR: failed to initialize FEC.\n");
-
-	if ((rv = pci_eth_init(bis)) >= 0)
-		num_if += rv;
-	else
-		printf("ERROR: failed to initialize PCI Ethernet.\n");
-
-	return num_if;
-}
-/*
- * Miscellaneous late-boot configurations
- *
- * Initialize EEPROM write-protect GPIO pin.
- */
-int misc_init_r(void)
-{
-#if defined(CONFIG_SYS_EEPROM_WREN)
-	/* Enable GPIO pin */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_SYS_EEPROM_WP);
-	/* Set direction, output */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_SYS_EEPROM_WP);
-	/* De-assert write enable */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
-#endif
-	return 0;
-}
-#if defined(CONFIG_SYS_EEPROM_WREN)
-/* Input: <dev_addr>  I2C address of EEPROM device to enable.
- *         <state>     -1: deliver current state
- *	               0: disable write
- *		       1: enable write
- *  Returns:           -1: wrong device address
- *                      0: dis-/en- able done
- *		     0/1: current state if <state> was -1.
- */
-int eeprom_write_enable (unsigned dev_addr, int state)
-{
-	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
-		return -1;
-	} else {
-		switch (state) {
-		case 1:
-			/* Enable write access */
-			clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
-			state = 0;
-			break;
-		case 0:
-			/* Disable write access */
-			setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
-			state = 0;
-			break;
-		default:
-			/* Read current status back. */
-			state = (0 == (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
-						   CONFIG_SYS_EEPROM_WP));
-			break;
-		}
-	}
-	return state;
-}
-#endif
-
-#ifdef CONFIG_CMD_DISPLAY
-#define DISPLAY_BUF_SIZE	2
-static u8 display_buf[DISPLAY_BUF_SIZE];
-static u8 display_putc_pos;
-static u8 display_out_pos;
-
-void display_set(int cmd) {
-
-	if (cmd & DISPLAY_CLEAR) {
-		display_buf[0] = display_buf[1] = 0;
-	}
-
-	if (cmd & DISPLAY_HOME) {
-		display_putc_pos = 0;
-	}
-}
-
-#define SEG_A    (1<<0)
-#define SEG_B    (1<<1)
-#define SEG_C    (1<<2)
-#define SEG_D    (1<<3)
-#define SEG_E    (1<<4)
-#define SEG_F    (1<<5)
-#define SEG_G    (1<<6)
-#define SEG_P    (1<<7)
-#define SEG__    0
-
-/*
- * +- A -+
- * |     |
- * F     B
- * |     |
- * +- G -+
- * |     |
- * E     C
- * |     |
- * +- D -+  P
- *
- * 0..9		index 0..9
- * A..Z		index 10..35
- * -		index 36
- * _		index 37
- * .		index 38
- */
-
-#define SYMBOL_DASH		(36)
-#define SYMBOL_UNDERLINE	(37)
-#define SYMBOL_DOT		(38)
-
-static u8 display_char2seg7_tbl[]=
-{
-	SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F,		/* 0 */
-	SEG_B | SEG_C,						/* 1 */
-	SEG_A | SEG_B | SEG_D | SEG_E | SEG_G,			/* 2 */
-	SEG_A | SEG_B | SEG_C | SEG_D | SEG_G,			/* 3 */
-	SEG_B | SEG_C | SEG_F | SEG_G,				/* 4 */
-	SEG_A | SEG_C | SEG_D | SEG_F | SEG_G,			/* 5 */
-	SEG_A | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G,		/* 6 */
-	SEG_A | SEG_B | SEG_C,					/* 7 */
-	SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G,	/* 8 */
-	SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G,		/* 9 */
-	SEG_A | SEG_B | SEG_C | SEG_E | SEG_F | SEG_G,		/* A */
-	SEG_C | SEG_D | SEG_E | SEG_F | SEG_G,			/* b */
-	SEG_A | SEG_D | SEG_E | SEG_F,				/* C */
-	SEG_B | SEG_C | SEG_D | SEG_E | SEG_G,			/* d */
-	SEG_A | SEG_D | SEG_E | SEG_F | SEG_G,			/* E */
-	SEG_A | SEG_E | SEG_F | SEG_G,				/* F */
-	0,					/* g - not displayed */
-	SEG_B | SEG_C | SEG_E | SEG_F | SEG_G,			/* H */
-	SEG_B | SEG_C,						/* I */
-	0,					/* J - not displayed */
-	0,					/* K - not displayed */
-	SEG_D | SEG_E | SEG_F,					/* L */
-	0,					/* m - not displayed */
-	0,					/* n - not displayed */
-	SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F,		/* O */
-	SEG_A | SEG_B | SEG_E | SEG_F | SEG_G,			/* P */
-	0,					/* q - not displayed */
-	0,					/* r - not displayed */
-	SEG_A | SEG_C | SEG_D | SEG_F | SEG_G,			/* S */
-	SEG_D | SEG_E | SEG_F | SEG_G,				/* t */
-	SEG_B | SEG_C | SEG_D | SEG_E | SEG_F,			/* U */
-	0,					/* V - not displayed */
-	0,					/* w - not displayed */
-	0,					/* X - not displayed */
-	SEG_B | SEG_C | SEG_D | SEG_F | SEG_G,			/* Y */
-	0,					/* Z - not displayed */
-	SEG_G,							/* - */
-	SEG_D,							/* _ */
-	SEG_P							/* . */
-};
-
-/* Convert char to the LED segments representation */
-static u8 display_char2seg7(char c)
-{
-	u8 val = 0;
-
-	if (c >= '0' && c <= '9')
-		c -= '0';
-	else if (c >= 'a' && c <= 'z')
-		c -= 'a' - 10;
-	else if (c >= 'A' && c <= 'Z')
-		c -= 'A' - 10;
-	else if (c == '-')
-		c = SYMBOL_DASH;
-	else if (c == '_')
-		c = SYMBOL_UNDERLINE;
-	else if (c == '.')
-		c = SYMBOL_DOT;
-	else
-		c = ' ';	/* display unsupported symbols as space */
-
-	if (c != ' ')
-		val = display_char2seg7_tbl[(int)c];
-
-	return val;
-}
-
-int display_putc(char c)
-{
-	if (display_putc_pos >= DISPLAY_BUF_SIZE)
-		return -1;
-
-	display_buf[display_putc_pos++] = display_char2seg7(c);
-	/* one-symbol message should be steady */
-	if (display_putc_pos == 1)
-		display_buf[display_putc_pos] = display_char2seg7(c);
-
-	return c;
-}
-
-/*
- * Flush current symbol to the LED display hardware
- */
-static inline void display_flush(void)
-{
-	u32 val = display_buf[display_out_pos];
-
-	val |= (val << 8) | (val << 16) | (val << 24);
-	out_be32((void *)CONFIG_SYS_DISP_CHR_RAM, val);
-}
-
-/*
- * Output contents of the software display buffer to the LED display every 0.5s
- */
-void board_show_activity(ulong timestamp)
-{
-	static ulong last;
-	static u8 once;
-
-	if (!once || (timestamp - last >= (CONFIG_SYS_HZ / 2))) {
-		display_flush();
-		display_out_pos ^= 1;
-		last = timestamp;
-		once = 1;
-	}
-}
-
-/*
- * Empty fake function
- */
-void show_activity(int arg)
-{
-}
-#endif
-#if defined (CONFIG_SHOW_BOOT_PROGRESS)
-static int a4m072_status2code(int status, char *buf)
-{
-	char c = 0;
-
-	if (((status > 0) && (status <= 8)) ||
-				((status >= 100) && (status <= 108)) ||
-				((status < 0) && (status >= -9)) ||
-				(status == -100) || (status == -101) ||
-				((status <= -103) && (status >= -113))) {
-		c = '5';
-	} else if (((status >= 9) && (status <= 14)) ||
-			((status >= 120) && (status <= 123)) ||
-			((status >= 125) && (status <= 129)) ||
-			((status >= -13) && (status <= -10)) ||
-			(status == -120) || (status == -122) ||
-			((status <= -124) && (status >= -127)) ||
-			(status == -129)) {
-		c = '8';
-	} else if (status == 15) {
-		c = '9';
-	} else if ((status <= -30) && (status >= -32)) {
-		c = 'A';
-	} else if (((status <= -35) && (status >= -40)) ||
-			((status <= -42) && (status >= -51)) ||
-			((status <= -53) && (status >= -58)) ||
-			(status == -64) ||
-			((status <= -80) && (status >= -83)) ||
-			(status == -130) || (status == -140) ||
-			(status == -150)) {
-		c = 'B';
-	}
-
-	if (c == 0)
-		return -EINVAL;
-
-	buf[0] = (status < 0) ? '-' : c;
-	buf[1] = c;
-
-	return 0;
-}
-
-void show_boot_progress(int status)
-{
-	char buf[2];
-
-	if (a4m072_status2code(status, buf) < 0)
-		return;
-
-	display_putc(buf[0]);
-	display_putc(buf[1]);
-	display_set(DISPLAY_HOME);
-	display_out_pos = 0;	/* reset output position */
-
-	/* we want to flush status 15 now */
-	if (status == BOOTSTAGE_ID_RUN_OS)
-		display_flush();
-}
-#endif
diff --git a/board/a4m072/mt46v32m16.h b/board/a4m072/mt46v32m16.h
deleted file mode 100644
index c0a08a8452..0000000000
--- a/board/a4m072/mt46v32m16.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	1		/* is DDR */
-
-#if defined(CONFIG_MPC5200)
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40010000
-#define SDRAM_CONTROL	0x704f0f00
-#define SDRAM_CONFIG1	0x73722930
-#define SDRAM_CONFIG2	0x47770000
-#define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/canmb/Kconfig b/board/canmb/Kconfig
deleted file mode 100644
index b5cf2057f4..0000000000
--- a/board/canmb/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CANMB
-
-config SYS_BOARD
-	default "canmb"
-
-config SYS_CONFIG_NAME
-	default "canmb"
-
-endif
diff --git a/board/canmb/MAINTAINERS b/board/canmb/MAINTAINERS
deleted file mode 100644
index 71750ead47..0000000000
--- a/board/canmb/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CANMB BOARD
-#M:	-
-S:	Maintained
-F:	board/canmb/
-F:	include/configs/canmb.h
-F:	configs/canmb_defconfig
diff --git a/board/canmb/Makefile b/board/canmb/Makefile
deleted file mode 100644
index 4286a9123c..0000000000
--- a/board/canmb/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2005-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= canmb.o
-
diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c
deleted file mode 100644
index 54de0e2673..0000000000
--- a/board/canmb/canmb.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * (C) Copyright 2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-
-#if defined(CONFIG_MPC5200_DDR)
-#include "mt46v16m16-75.h"
-#else
-#include "mt48lc16m32s2-75.h"
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set mode register: extended mode */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
-	__asm__ volatile ("sync");
-
-	/* set mode register: reset DLL */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
-	__asm__ volatile ("sync");
-#endif
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* set mode register */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-	__asm__ volatile ("sync");
-
-	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-	__asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced dram_init does NOT make real use
- *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- *            is something else than 0x00000000.
- */
-
-int dram_init(void)
-{
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set tap delay */
-	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
-	__asm__ volatile ("sync");
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20)) {
-		dramsize = 0;
-	}
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-	}
-
-	/* let SDRAM CS1 start right after CS0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
-
-	/* find RAM size using SDRAM CS1 only */
-	if (!dramsize)
-		sdram_start(0);
-	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	if (!dramsize) {
-		sdram_start(1);
-		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	}
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize2 = test1;
-	} else {
-		dramsize2 = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize2 < (1 << 20)) {
-		dramsize2 = 0;
-	}
-
-	/* set SDRAM CS1 size according to the amount of RAM found */
-	if (dramsize2 > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
-			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
-	if (dramsize >= 0x13) {
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	} else {
-		dramsize = 0;
-	}
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
-	if (dramsize2 >= 0x13) {
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	} else {
-		dramsize2 = 0;
-	}
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	gd->ram_size = dramsize + dramsize2;
-
-	return 0;
-}
-
-int checkboard (void)
-{
-	puts ("Board: CANMB\n");
-	return 0;
-}
-
-int board_early_init_r (void)
-{
-	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-	*(vu_long *)MPC5XXX_BOOTCS_START =
-	*(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
-	*(vu_long *)MPC5XXX_BOOTCS_STOP =
-	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
-	return 0;
-}
diff --git a/board/canmb/mt48lc16m32s2-75.h b/board/canmb/mt48lc16m32s2-75.h
deleted file mode 100644
index 0133eaa2ca..0000000000
--- a/board/canmb/mt48lc16m32s2-75.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	0		/* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x00CD0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xD2322800
-#define SDRAM_CONFIG2	0x8AD70000
diff --git a/board/cm5200/Kconfig b/board/cm5200/Kconfig
deleted file mode 100644
index ccea5c96e4..0000000000
--- a/board/cm5200/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CM5200
-
-config SYS_BOARD
-	default "cm5200"
-
-config SYS_CONFIG_NAME
-	default "cm5200"
-
-endif
diff --git a/board/cm5200/MAINTAINERS b/board/cm5200/MAINTAINERS
deleted file mode 100644
index 1e1df3f6dc..0000000000
--- a/board/cm5200/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM5200 BOARD
-#M:	-
-S:	Maintained
-F:	board/cm5200/
-F:	include/configs/cm5200.h
-F:	configs/cm5200_defconfig
diff --git a/board/cm5200/Makefile b/board/cm5200/Makefile
deleted file mode 100644
index 76f8b9fc05..0000000000
--- a/board/cm5200/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= cm5200.o cmd_cm5200.o fwupdate.o
diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c
deleted file mode 100644
index 0c647bbd3d..0000000000
--- a/board/cm5200/cm5200.c
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- * (C) Copyright 2003-2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2004-2005
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * Adapted to U-Boot 1.2 by:
- *   Bartlomiej Sieka <tur@semihalf.com>:
- *      - HW ID readout from EEPROM
- *      - module detection
- *   Grzegorz Bernacki <gjb@semihalf.com>:
- *      - run-time SDRAM controller configuration
- *      - LIBFDT support
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <i2c.h>
-#include <linux/ctype.h>
-
-#ifdef CONFIG_OF_LIBFDT
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif /* CONFIG_OF_LIBFDT */
-
-
-#include "cm5200.h"
-#include "fwupdate.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static hw_id_t hw_id;
-
-
-#ifndef CONFIG_SYS_RAMBOOT
-/*
- * Helper function to initialize SDRAM controller.
- */
-static void sdram_start(int hi_addr, mem_conf_t *mem_conf)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000000 |
-						hi_addr_bit;
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000002 |
-						hi_addr_bit;
-
-	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 |
-						hi_addr_bit;
-
-	/* auto refresh, second time */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 |
-						hi_addr_bit;
-
-	/* set mode register */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = mem_conf->mode;
-
-	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | hi_addr_bit;
-}
-#endif /* CONFIG_SYS_RAMBOOT */
-
-
-/*
- * Retrieve memory configuration for a given module. board_type is the index
- * in hw_id_list[] corresponding to the module we are executing on; we return
- * SDRAM controller settings approprate for this module.
- */
-static mem_conf_t* get_mem_config(int board_type)
-{
-	switch(board_type){
-		case CM1_QA:
-			return memory_config[0];
-		case CM11_QA:
-		case CMU1_QA:
-			return memory_config[1];
-		default:
-			printf("ERROR: Unknown module, using a default SDRAM "
-				"configuration - things may not work!!!.\n");
-			return memory_config[0];
-	}
-}
-
-
-/*
- * Initalize SDRAM - configure SDRAM controller, detect memory size.
- */
-int dram_init(void)
-{
-	ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-	mem_conf_t *mem_conf;
-
-	mem_conf = get_mem_config(gd->board_type);
-
-	/* configure SDRAM start/end for detection */
-	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = mem_conf->config1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = mem_conf->config2;
-
-	sdram_start(0, mem_conf);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1, mem_conf);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0, mem_conf);
-		dramsize = test1;
-	} else
-		dramsize = test2;
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
-			__builtin_ffs(dramsize >> 20) - 1;
-	} else
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-#else /* CONFIG_SYS_RAMBOOT */
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
-	if (dramsize >= 0x13)
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	else
-		dramsize = 0;
-#endif /* !CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller.  Refer to chapter 8.7.5 SDelay--MBAR + 0x0190 of
-	 * the MPC5200B User's Manual.
-	 */
-	*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
-	__asm__ volatile ("sync");
-
-	gd->ram_size = dramsize;
-
-	return 0;
-}
-
-
-/*
- * Read module hardware identification data from the I2C EEPROM.
- */
-static void read_hw_id(hw_id_t hw_id)
-{
-	printf("ERROR: can't read HW ID from EEPROM\n");
-}
-
-
-/*
- * Identify module we are running on, set gd->board_type to the index in
- * hw_id_list[] corresponding to the module identifed, or to
- * CM5200_UNKNOWN_MODULE if we can't identify the module.
- */
-static void identify_module(hw_id_t hw_id)
-{
-	int i, j, element;
-	char match;
-	gd->board_type = CM5200_UNKNOWN_MODULE;
-	for (i = 0; i < sizeof (hw_id_list) / sizeof (char **); ++i) {
-		match = 1;
-		for (j = 0; j < sizeof (hw_id_identify) / sizeof (int); ++j) {
-			element = hw_id_identify[j];
-			if (strncmp(hw_id_list[i][element],
-					&hw_id[element][0],
-					hw_id_format[element].length) != 0) {
-				match = 0;
-				break;
-			}
-		}
-		if (match) {
-			gd->board_type = i;
-			break;
-		}
-	}
-}
-
-
-/*
- * Compose string with module name.
- * buf is assumed to have enough space, and be null-terminated.
- */
-static void compose_module_name(hw_id_t hw_id, char *buf)
-{
-	char tmp[MODULE_NAME_MAXLEN];
-	strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length);
-	strncat(buf, ".", 1);
-	strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length);
-	strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length);
-	strncat(buf, " (", 2);
-	strncat(buf, &hw_id[IDENTIFICATION_NUMBER][0],
-		hw_id_format[IDENTIFICATION_NUMBER].length);
-	sprintf(tmp, " / %u.%u)",
-		hw_id[MAJOR_SW_VERSION][0],
-		hw_id[MINOR_SW_VERSION][0]);
-	strcat(buf, tmp);
-}
-
-#if defined(CONFIG_SYS_I2C_SOFT)
-/*
- * Compose string with hostname.
- * buf is assumed to have enough space, and be null-terminated.
- */
-static void compose_hostname(hw_id_t hw_id, char *buf)
-{
-	char *p;
-	strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length);
-	strncat(buf, "_", 1);
-	strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length);
-	strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length);
-	for (p = buf; *p; ++p)
-		*p = tolower(*p);
-
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-/*
- * Update 'model' and 'memory' properties in the blob according to the module
- * that we are running on.
- */
-static void ft_blob_update(void *blob, bd_t *bd)
-{
-	int len, ret, nodeoffset = 0;
-	char module_name[MODULE_NAME_MAXLEN] = {0};
-
-	compose_module_name(hw_id, module_name);
-	len = strlen(module_name) + 1;
-
-	ret = fdt_setprop(blob, nodeoffset, "model", module_name, len);
-	if (ret < 0)
-	printf("ft_blob_update(): cannot set /model property err:%s\n",
-		fdt_strerror(ret));
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-
-/*
- * Read HW ID from I2C EEPROM and detect the modue we are running on. Note
- * that we need to use local variable for readout, because global data is not
- * writable yet (and we'll have to redo the readout later on).
- */
-int checkboard(void)
-{
-	hw_id_t hw_id_tmp;
-	char module_name_tmp[MODULE_NAME_MAXLEN] = "";
-
-	read_hw_id(hw_id_tmp);
-	identify_module(hw_id_tmp);	/* this sets gd->board_type */
-	compose_module_name(hw_id_tmp, module_name_tmp);
-
-	if (gd->board_type != CM5200_UNKNOWN_MODULE)
-		printf("Board: %s\n", module_name_tmp);
-	else
-		printf("Board: unrecognized cm5200 module (%s)\n",
-			module_name_tmp);
-
-	return 0;
-}
-
-
-int board_early_init_r(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write access for detection
-	 * process. Note that CS_BOOT cannot be cleared when executing in
-	 * flash.
-	 */
-	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-
-	/* Now that we can write to global data, read HW ID again. */
-	read_hw_id(hw_id);
-	return 0;
-}
-
-
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
-{
-#if defined(CONFIG_SYS_I2C_SOFT)
-	uchar buf[6];
-	char str[18];
-	char hostname[MODULE_NAME_MAXLEN];
-
-	/* Read ethaddr from EEPROM */
-	if (i2c_read(CONFIG_SYS_I2C_EEPROM, CONFIG_MAC_OFFSET, 2, buf, 6) == 0) {
-		sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X",
-			buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
-		/* Check if MAC addr is owned by Schindler */
-		if (strstr(str, "00:06:C3") != str)
-			printf(LOG_PREFIX "Warning - Illegal MAC address (%s)"
-				" in EEPROM.\n", str);
-		else {
-			printf(LOG_PREFIX "Using MAC (%s) from I2C EEPROM\n",
-				str);
-			setenv("ethaddr", str);
-		}
-	} else {
-		printf(LOG_PREFIX "Warning - Unable to read MAC from I2C"
-			" device at address %02X:%04X\n", CONFIG_SYS_I2C_EEPROM,
-			CONFIG_MAC_OFFSET);
-	}
-	hostname[0] = 0x00;
-	/* set the hostname appropriate to the module we're running on */
-	compose_hostname(hw_id, hostname);
-	setenv("hostname", hostname);
-
-#endif /* defined(CONFIG_SYS_I2C_SOFT) */
-	if (!getenv("ethaddr"))
-		printf(LOG_PREFIX "MAC address not set, networking is not "
-					"operational\n");
-
-	return 0;
-}
-#endif /* CONFIG_MISC_INIT_R */
-
-
-#ifdef CONFIG_LAST_STAGE_INIT
-int last_stage_init(void)
-{
-#ifdef CONFIG_USB_STORAGE
-	cm5200_fwupdate();
-#endif /* CONFIG_USB_STORAGE */
-	return 0;
-}
-#endif /* CONFIG_LAST_STAGE_INIT */
-
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-	ft_blob_update(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/cm5200/cm5200.h b/board/cm5200/cm5200.h
deleted file mode 100644
index c2573f3bf6..0000000000
--- a/board/cm5200/cm5200.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * (C) Copyright 2007 DENX Software Engineering
- *
- * Author: Bartlomiej Sieka <tur@semihalf.com>
- * Author: Grzegorz Bernacki <gjb@semihalf.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _CM5200_H
-#define _CM5200_H
-
-
-/*
- * Definitions and declarations for the modules of the cm5200 platform. Mostly
- * related to reading the hardware identification data (HW ID) from the I2C
- * EEPROM, detection of the particular module we are executing on, and
- * appropriate SDRAM controller initialization.
- */
-
-
-#define CM5200_UNKNOWN_MODULE	0xffffffff
-
-enum {
-	DEVICE_NAME,		/* 0 */
-	GENERATION,		/* 1 */
-	PCB_NAME,		/* 2 */
-	FORM,			/* 3 */
-	VERSION,		/* 4 */
-	IDENTIFICATION_NUMBER,	/* 5 */
-	MAJOR_SW_VERSION,	/* 6 */
-	MINOR_SW_VERSION,	/* 7 */
-	/* add new alements above this line */
-	HW_ID_ELEM_COUNT	/* count */
-};
-
-/*
- * Sect. 4.1 "CM1.Q/CMU1.Q Supervisory Microcontroller Interface Definition"
- */
-
-#define DEVICE_NAME_OFFSET		0x02
-#define GENERATION_OFFSET		0x0b
-#define PCB_NAME_OFFSET			0x0c
-#define FORM_OFFSET			0x15
-#define VERSION_OFFSET			0x16
-#define IDENTIFICATION_NUMBER_OFFSET	0x19
-#define MAJOR_SW_VERSION_OFFSET		0x0480
-#define MINOR_SW_VERSION_OFFSET		0x0481
-
-
-#define DEVICE_NAME_LEN			0x09
-#define GENERATION_LEN			0x01
-#define PCB_NAME_LEN			0x09
-#define FORM_LEN			0x01
-#define VERSION_LEN			0x03
-#define IDENTIFICATION_NUMBER_LEN	0x09
-#define MAJOR_SW_VERSION_LEN		0x01
-#define MINOR_SW_VERSION_LEN		0x01
-
-#define HW_ID_ELEM_MAXLEN		0x09	/* MAX(XXX_LEN) */
-
-/* entire HW ID in EEPROM is 64 bytes, so longer module name is unlikely */
-#define MODULE_NAME_MAXLEN		64
-
-
-/* storage for HW ID read from EEPROM */
-typedef char hw_id_t[HW_ID_ELEM_COUNT][HW_ID_ELEM_MAXLEN];
-
-
-/* HW ID layout in EEPROM */
-static struct {
-	unsigned int offset;
-	unsigned int length;
-} hw_id_format[HW_ID_ELEM_COUNT] = {
-	{DEVICE_NAME_OFFSET,		DEVICE_NAME_LEN},
-	{GENERATION_OFFSET,		GENERATION_LEN},
-	{PCB_NAME_OFFSET,		PCB_NAME_LEN},
-	{FORM_OFFSET,			FORM_LEN},
-	{VERSION_OFFSET,		VERSION_LEN},
-	{IDENTIFICATION_NUMBER_OFFSET,	IDENTIFICATION_NUMBER_LEN},
-	{MAJOR_SW_VERSION_OFFSET,	MAJOR_SW_VERSION_LEN},
-	{MINOR_SW_VERSION_OFFSET,	MINOR_SW_VERSION_LEN},
-};
-
-
-/* HW ID data found in EEPROM on supported modules */
-static char *cm1_qa_hw_id[HW_ID_ELEM_COUNT] = {
-	"CM",		/* DEVICE_NAME */
-	"1",		/* GENERATION */
-	"CM1",		/* PCB_NAME */
-	"Q",		/* FORM */
-	"A",		/* VERSION */
-	"591881",	/* IDENTIFICATION_NUMBER */
-	"",		/* MAJOR_SW_VERSION */
-	"",		/* MINOR_SW_VERSION */
-};
-
-static char *cm11_qa_hw_id[HW_ID_ELEM_COUNT] = {
-	"CM",		/* DEVICE_NAME */
-	"1",		/* GENERATION */
-	"CM11",		/* PCB_NAME */
-	"Q",		/* FORM */
-	"A",		/* VERSION */
-	"594200",	/* IDENTIFICATION_NUMBER */
-	"",		/* MAJOR_SW_VERSION */
-	"",		/* MINOR_SW_VERSION */
-};
-
-static char *cmu1_qa_hw_id[HW_ID_ELEM_COUNT] = {
-	"CMU",		/* DEVICE_NAME */
-	"1",		/* GENERATION */
-	"CMU1",		/* PCB_NAME */
-	"Q",		/* FORM */
-	"A",		/* VERSION */
-	"594128",	/* IDENTIFICATION_NUMBER */
-	"",		/* MAJOR_SW_VERSION */
-	"",		/* MINOR_SW_VERSION */
-};
-
-
-/* list of known modules */
-static char **hw_id_list[] = {
-	cm1_qa_hw_id,
-	cm11_qa_hw_id,
-	cmu1_qa_hw_id,
-};
-
-/* indices to the above list - keep in sync */
-enum {
-	CM1_QA,
-	CM11_QA,
-	CMU1_QA,
-};
-
-
-/* identify modules based on these hw id elements */
-static int hw_id_identify[] = {
-	PCB_NAME,
-	FORM,
-	VERSION,
-};
-
-
-/* Registers' settings for SDRAM controller intialization */
-typedef struct {
-	ulong mode;
-	ulong control;
-	ulong config1;
-	ulong config2;
-} mem_conf_t;
-
-static mem_conf_t k4s561632E = {
-	0x00CD0000,      /* CASL 3, burst length 8 */
-	0x514F0000,
-	0xE2333900,
-	0x8EE70000
-};
-
-static mem_conf_t mt48lc32m16a2 = {
-	0x00CD0000,      /* CASL 3, burst length 8 */
-	0x514F0000,
-	0xD2322800,
-	0x8AD70000
-};
-
-static mem_conf_t* memory_config[] = {
-	&k4s561632E,
-	&mt48lc32m16a2
-};
-
-#endif /* _CM5200_H */
diff --git a/board/cm5200/cmd_cm5200.c b/board/cm5200/cmd_cm5200.c
deleted file mode 100644
index 60097dc8c7..0000000000
--- a/board/cm5200/cmd_cm5200.c
+++ /dev/null
@@ -1,402 +0,0 @@
-/*
- * (C) Copyright 2007 Markus Kappeler <markus.kappeler@objectxp.com>
- *
- * Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <i2c.h>
-#include <usb.h>
-
-#ifdef CONFIG_CMD_BSP
-
-static int do_usb_test(char * const argv[])
-{
-	int i;
-	static int usb_stor_curr_dev = -1; /* current device */
-
-	printf("Starting USB Test\n"
-		"Please insert USB Memmory Stick\n\n"
-		"Please press any key to start\n\n");
-	getc();
-
-	usb_stop();
-	printf("(Re)start USB...\n");
-	i = usb_init();
-#ifdef CONFIG_USB_STORAGE
-		/* try to recognize storage devices immediately */
-		if (i >= 0)
-			usb_stor_curr_dev = usb_stor_scan(1);
-#endif /* CONFIG_USB_STORAGE */
-	if (usb_stor_curr_dev >= 0)
-		printf("Found USB Storage Dev continue with Test...\n");
-	else {
-		printf("No USB Storage Device detected.. Stop Test\n");
-		return 1;
-	}
-
-	usb_stor_info();
-
-	printf("stopping USB..\n");
-	usb_stop();
-
-	return 0;
-}
-
-static int do_led_test(char * const argv[])
-{
-	int i = 0;
-	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
-
-	printf("Starting LED Test\n"
-		"Please set Switch S500 all off\n\n"
-		"Please press any key to start\n\n");
-	getc();
-
-	/* configure timer 2-3 for simple GPIO output High */
-	gpt->gpt2.emsr |= 0x00000034;
-	gpt->gpt3.emsr |= 0x00000034;
-
-	(*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x80000000;
-	(*(vu_long *)MPC5XXX_WU_GPIO_DIR) |= 0x80000000;
-	printf("Please press any key to stop\n\n");
-	while (!tstc()) {
-		if (i == 1) {
-			(*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000;
-			gpt->gpt2.emsr &= ~0x00000010;
-			gpt->gpt3.emsr &= ~0x00000010;
-		} else if (i == 2) {
-			(*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000;
-			gpt->gpt2.emsr &= ~0x00000010;
-			gpt->gpt3.emsr |= 0x00000010;
-		} else if (i >= 3) {
-			(*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000;
-			gpt->gpt3.emsr &= ~0x00000010;
-			gpt->gpt2.emsr |= 0x00000010;
-			i = 0;
-		}
-		i++;
-		udelay(200000);
-	}
-	getc();
-
-	(*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000;
-	gpt->gpt2.emsr |= 0x00000010;
-	gpt->gpt3.emsr |= 0x00000010;
-
-	return 0;
-}
-
-static int do_rs232_test(char * const argv[])
-{
-	int error_status = 0;
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-	struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
-
-	/* Configure PSC 2-3-6 as GPIO */
-	gpio->port_config &= 0xFF0FF80F;
-
-	switch (simple_strtoul(argv[2], NULL, 10)) {
-	case 1:
-		/* check RTS <-> CTS loop */
-		/* set rts to 0 */
-		printf("Uart 1 test: RX TX tested by using U-Boot\n"
-			"Please connect RTS with CTS on Uart1 plug\n\n"
-			"Press any key to start\n\n");
-		getc();
-
-		psc1->op1 |= 0x01;
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		/* check status at cts */
-		if ((psc1->ip & 0x01) != 0) {
-			error_status = 3;
-			printf("%s: failure at rs232_1, cts status is %d "
-				"(should be 0)\n",
-				__FUNCTION__, (psc1->ip & 0x01));
-		}
-
-		/* set rts to 1 */
-		psc1->op0 |= 0x01;
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		/* check status at cts */
-		if ((psc1->ip & 0x01) != 1) {
-			error_status = 3;
-			printf("%s: failure at rs232_1, cts status is %d "
-				"(should be 1)\n",
-				__FUNCTION__, (psc1->ip & 0x01));
-		}
-		break;
-	case 2:
-		/* set PSC2_0, PSC2_2 as output and PSC2_1, PSC2_3 as input */
-		printf("Uart 2 test: Please use RS232 Loopback plug on UART2\n"
-			"\nPress any key to start\n\n");
-		getc();
-
-		gpio->simple_gpioe &= ~(0x000000F0);
-		gpio->simple_gpioe |= 0x000000F0;
-		gpio->simple_ddr &= ~(0x000000F0);
-		gpio->simple_ddr |= 0x00000050;
-
-		/* check TXD <-> RXD loop */
-		/* set TXD to 1 */
-		gpio->simple_dvo |= (1 << 4);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000020) != 0x00000020) {
-			error_status = 2;
-			printf("%s: failure at rs232_2, rxd status is %d "
-				"(should be 1)\n", __FUNCTION__,
-				(gpio->simple_ival & 0x00000020) >> 5);
-		}
-
-		/* set TXD to 0 */
-		gpio->simple_dvo &= ~(1 << 4);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000020) != 0x00000000) {
-			error_status = 2;
-			printf("%s: failure at rs232_2, rxd status is %d "
-				"(should be 0)\n", __FUNCTION__,
-				(gpio->simple_ival & 0x00000020) >> 5);
-		}
-
-		/* check RTS <-> CTS loop */
-		/* set RTS to 1 */
-		gpio->simple_dvo |= (1 << 6);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000080) != 0x00000080) {
-			error_status = 3;
-			printf("%s: failure at rs232_2, cts status is %d "
-				"(should be 1)\n", __FUNCTION__,
-				(gpio->simple_ival & 0x00000080) >> 7);
-		}
-
-		/* set RTS to 0 */
-		gpio->simple_dvo &= ~(1 << 6);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000080) != 0x00000000) {
-			error_status = 3;
-			printf("%s: failure at rs232_2, cts status is %d "
-				"(should be 0)\n", __FUNCTION__,
-				(gpio->simple_ival & 0x00000080) >> 7);
-		}
-		break;
-	case 3:
-		/* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */
-		printf("Uart 3 test: Please use RS232 Loopback plug on UART2\n"
-			"\nPress any key to start\n\n");
-		getc();
-
-		gpio->simple_gpioe &= ~(0x00000F00);
-		gpio->simple_gpioe |= 0x00000F00;
-
-		gpio->simple_ddr &= ~(0x00000F00);
-		gpio->simple_ddr |= 0x00000500;
-
-		/* check TXD <-> RXD loop */
-		/* set TXD to 1 */
-		gpio->simple_dvo |= (1 << 8);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000200) != 0x00000200) {
-			error_status = 2;
-			printf("%s: failure at rs232_3, rxd status is %d "
-				"(should be 1)\n", __FUNCTION__,
-				(gpio->simple_ival & 0x00000200) >> 9);
-		}
-
-		/* set TXD to 0 */
-		gpio->simple_dvo &= ~(1 << 8);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000200) != 0x00000000) {
-			error_status = 2;
-			printf("%s: failure at rs232_3, rxd status is %d "
-				"(should be 0)\n", __FUNCTION__,
-				(gpio->simple_ival & 0x00000200) >> 9);
-		}
-
-		/* check RTS <-> CTS loop */
-		/* set RTS to 1 */
-		gpio->simple_dvo |= (1 << 10);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000800) != 0x00000800) {
-			error_status = 3;
-			printf("%s: failure at rs232_3, cts status is %d "
-				"(should be 1)\n", __FUNCTION__,
-				(gpio->simple_ival & 0x00000800) >> 11);
-		}
-
-		/* set RTS to 0 */
-		gpio->simple_dvo &= ~(1 << 10);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000800) != 0x00000000) {
-			error_status = 3;
-			printf("%s: failure at rs232_3, cts status is %d "
-				"(should be 0)\n", __FUNCTION__,
-				(gpio->simple_ival & 0x00000800) >> 11);
-		}
-		break;
-	case 4:
-		/* set PSC6_2, PSC6_3 as output and PSC6_0, PSC6_1 as input */
-		printf("Uart 4 test: Please use RS232 Loopback plug on UART2\n"
-			"\nPress any key to start\n\n");
-		getc();
-
-		gpio->simple_gpioe &= ~(0xF0000000);
-		gpio->simple_gpioe |= 0x30000000;
-
-		gpio->simple_ddr &= ~(0xf0000000);
-		gpio->simple_ddr |= 0x30000000;
-
-		(*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x30000000;
-		(*(vu_long *)MPC5XXX_WU_GPIO_DIR) &= ~(0x30000000);
-
-		/* check TXD <-> RXD loop */
-		/* set TXD to 1 */
-		gpio->simple_dvo |= (1 << 28);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) !=
-				0x10000000) {
-			error_status = 2;
-			printf("%s: failure at rs232_4, rxd status is %lu "
-				"(should be 1)\n", __FUNCTION__,
-				((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
-					0x10000000) >> 28);
-		}
-
-		/* set TXD to 0 */
-		gpio->simple_dvo &= ~(1 << 28);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) !=
-				0x00000000) {
-			error_status = 2;
-			printf("%s: failure at rs232_4, rxd status is %lu "
-				"(should be 0)\n", __FUNCTION__,
-				((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
-					0x10000000) >> 28);
-		}
-
-		/* check RTS <-> CTS loop */
-		/* set RTS to 1 */
-		gpio->simple_dvo |= (1 << 29);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) !=
-				0x20000000) {
-			error_status = 3;
-			printf("%s: failure at rs232_4, cts status is %lu "
-				"(should be 1)\n", __FUNCTION__,
-				((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
-					0x20000000) >> 29);
-		}
-
-		/* set RTS to 0 */
-		gpio->simple_dvo &= ~(1 << 29);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) !=
-				0x00000000) {
-			error_status = 3;
-			printf("%s: failure at rs232_4, cts status is %lu "
-				"(should be 0)\n", __FUNCTION__,
-				((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
-					0x20000000) >> 29);
-		}
-		break;
-	default:
-		printf("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]);
-		error_status = 1;
-		break;
-	}
-	gpio->port_config |= (CONFIG_SYS_GPS_PORT_CONFIG & 0xFF0FF80F);
-
-	return error_status;
-}
-
-static int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int rcode = -1;
-
-	switch (argc) {
-	case 2:
-		if (strncmp(argv[1], "led", 3) == 0)
-			rcode = do_led_test(argv);
-		else if (strncmp(argv[1], "usb", 3) == 0)
-			rcode = do_usb_test(argv);
-		break;
-	case 3:
-		if (strncmp(argv[1], "rs232", 3) == 0)
-			rcode = do_rs232_test(argv);
-		break;
-	}
-
-	switch (rcode) {
-	case -1:
-		printf("Usage:\n"
-			"fkt { i2c | led | usb }\n"
-			"fkt rs232 number\n");
-		rcode = 1;
-		break;
-	case 0:
-		printf("Test passed\n");
-		break;
-	default:
-		printf("Test failed with code: %d\n", rcode);
-	}
-
-	return rcode;
-}
-
-U_BOOT_CMD(
-	fkt,	4,	1,	cmd_fkt,
-	"Function test routines",
-	"i2c\n"
-	"     - Test I2C communication\n"
-	"fkt led\n"
-	"     - Test LEDs\n"
-	"fkt rs232 number\n"
-	"     - Test RS232 (loopback plug(s) for RS232 required)\n"
-	"fkt usb\n"
-	"     - Test USB communication"
-);
-#endif /* CONFIG_CMD_BSP */
diff --git a/board/cm5200/fwupdate.c b/board/cm5200/fwupdate.c
deleted file mode 100644
index 4740c8394c..0000000000
--- a/board/cm5200/fwupdate.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * (C) Copyright 2007 Schindler Lift Inc.
- * (C) Copyright 2007 DENX Software Engineering
- *
- * Author: Michel Marti <mma@objectxp.com>
- * Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com>:
- *   - code clean-up
- *   - bugfix for overwriting bootargs by user
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <fat.h>
-#include <malloc.h>
-#include <image.h>
-#include <usb.h>
-#include <fat.h>
-
-#include "fwupdate.h"
-
-static int load_rescue_image(ulong);
-
-void cm5200_fwupdate(void)
-{
-	cmd_tbl_t *bcmd;
-	char *rsargs;
-	char *tmp = NULL;
-	char ka[16];
-	char * const argv[3] = { "bootm", ka, NULL };
-
-	/* Check if rescue system is disabled... */
-	if (getenv("norescue")) {
-		printf(LOG_PREFIX "Rescue System disabled.\n");
-		return;
-	}
-
-	/* Check if we have a USB storage device and load image */
-	if (load_rescue_image(LOAD_ADDR))
-		return;
-
-	bcmd = find_cmd("bootm");
-	if (!bcmd)
-		return;
-
-	sprintf(ka, "%lx", (ulong)LOAD_ADDR);
-
-	/* prepare our bootargs */
-	rsargs = getenv("rs-args");
-	if (!rsargs)
-		rsargs = RS_BOOTARGS;
-	else {
-		tmp = malloc(strlen(rsargs+1));
-		if (!tmp) {
-			printf(LOG_PREFIX "Memory allocation failed\n");
-			return;
-		}
-		strcpy(tmp, rsargs);
-		rsargs = tmp;
-	}
-
-	setenv("bootargs", rsargs);
-
-	if (rsargs == tmp)
-		free(rsargs);
-
-	printf(LOG_PREFIX "Starting update system (bootargs=%s)...\n", rsargs);
-	do_bootm(bcmd, 0, 2, argv);
-}
-
-static int load_rescue_image(ulong addr)
-{
-	disk_partition_t info;
-	int devno;
-	int partno;
-	int i;
-	char fwdir[64];
-	char nxri[128];
-	char *tmp;
-	char dev[7];
-	char addr_str[16];
-	char * const argv[6] = { "fatload", "usb", dev, addr_str, nxri, NULL };
-	struct blk_desc *stor_dev = NULL;
-	cmd_tbl_t *bcmd;
-
-	/* Get name of firmware directory */
-	tmp = getenv("fw-dir");
-
-	/* Copy it into fwdir */
-	strncpy(fwdir, tmp ? tmp : FW_DIR, sizeof(fwdir));
-	fwdir[sizeof(fwdir) - 1] = 0; /* Terminate string */
-
-	printf(LOG_PREFIX "Checking for firmware image directory '%s' on USB"
-		" storage...\n", fwdir);
-	usb_stop();
-	if (usb_init() != 0)
-		return 1;
-
-	/* Check for storage device */
-	if (usb_stor_scan(1) != 0) {
-		usb_stop();
-		return 1;
-	}
-
-	/* Detect storage device */
-	for (devno = 0; devno < USB_MAX_STOR_DEV; devno++) {
-		stor_dev = blk_get_devnum_by_type(IF_TYPE_USB, devno);
-		if (stor_dev->type != DEV_TYPE_UNKNOWN)
-			break;
-	}
-	if (!stor_dev || stor_dev->type == DEV_TYPE_UNKNOWN) {
-		printf(LOG_PREFIX "No valid storage device found...\n");
-		usb_stop();
-		return 1;
-	}
-
-	/* Detect partition */
-	for (partno = -1, i = 0; i < 6; i++) {
-		if (part_get_info(stor_dev, i, &info) == 0) {
-			if (fat_register_device(stor_dev, i) == 0) {
-				/* Check if rescue image is present */
-				FW_DEBUG("Looking for firmware directory '%s'"
-					" on partition %d\n", fwdir, i);
-				if (!fat_exists(fwdir)) {
-					FW_DEBUG("No NX rescue image on "
-						"partition %d.\n", i);
-					partno = -2;
-				} else {
-					partno = i;
-					FW_DEBUG("Partition %d contains "
-						"firmware directory\n", partno);
-					break;
-				}
-			}
-		}
-	}
-
-	if (partno < 0) {
-		switch (partno) {
-		case -1:
-			printf(LOG_PREFIX "Error: No valid (FAT) partition "
-				"detected\n");
-			break;
-		case -2:
-			printf(LOG_PREFIX "Error: No NX rescue image on FAT "
-				"partition\n");
-			break;
-		default:
-			printf(LOG_PREFIX "Error: Failed with code %d\n",
-				partno);
-		}
-		usb_stop();
-		return 1;
-	}
-
-	/* Load the rescue image */
-	bcmd = find_cmd("fatload");
-	if (!bcmd) {
-		printf(LOG_PREFIX "Error - 'fatload' command not present.\n");
-		usb_stop();
-		return 1;
-	}
-
-	tmp = getenv("nx-rescue-image");
-	sprintf(nxri, "%s/%s", fwdir, tmp ? tmp : RESCUE_IMAGE);
-	sprintf(dev, "%d:%d", devno, partno);
-	sprintf(addr_str, "%lx", addr);
-
-	FW_DEBUG("fat_fsload device='%s', addr='%s', file: %s\n",
-		dev, addr_str, nxri);
-
-	if (do_fat_fsload(bcmd, 0, 5, argv) != 0) {
-		usb_stop();
-		return 1;
-	}
-
-	/* Stop USB */
-	usb_stop();
-	return 0;
-}
diff --git a/board/cm5200/fwupdate.h b/board/cm5200/fwupdate.h
deleted file mode 100644
index 6ddf0bac35..0000000000
--- a/board/cm5200/fwupdate.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * (C) Copyright 2007 Schindler Lift Inc.
- *
- * Author: Michel Marti <mma@objectxp.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __FW_UPDATE_H
-#define __FW_UPDATE_H
-
-/* Default prefix for output messages */
-#define LOG_PREFIX	"CM5200:"
-
-/* Extra debug macro */
-#ifdef CONFIG_FWUPDATE_DEBUG
-#define FW_DEBUG(fmt...) printf(LOG_PREFIX fmt)
-#else
-#define FW_DEBUG(fmt...)
-#endif
-
-/* Name of the directory holding firmware images */
-#define FW_DIR		"nx-fw"
-#define RESCUE_IMAGE	"nxrs.img"
-#define LOAD_ADDR	0x400000
-#define RS_BOOTARGS	"ramdisk_size=8192K"
-
-/* Main function for fwupdate */
-void cm5200_fwupdate(void);
-
-#endif /* __FW_UPDATE_H */
diff --git a/board/davedenx/aria/Kconfig b/board/davedenx/aria/Kconfig
deleted file mode 100644
index 54a86b9e13..0000000000
--- a/board/davedenx/aria/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_ARIA
-
-config SYS_BOARD
-	default "aria"
-
-config SYS_VENDOR
-	default "davedenx"
-
-config SYS_CONFIG_NAME
-	default "aria"
-
-endif
diff --git a/board/davedenx/aria/MAINTAINERS b/board/davedenx/aria/MAINTAINERS
deleted file mode 100644
index a6152c985a..0000000000
--- a/board/davedenx/aria/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ARIA BOARD
-M:	Wolfgang Denk <wd@denx.de>
-S:	Maintained
-F:	board/davedenx/aria/
-F:	include/configs/aria.h
-F:	configs/aria_defconfig
diff --git a/board/davedenx/aria/Makefile b/board/davedenx/aria/Makefile
deleted file mode 100644
index dd38b7f389..0000000000
--- a/board/davedenx/aria/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= aria.o
diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c
deleted file mode 100644
index e389819e9d..0000000000
--- a/board/davedenx/aria/aria.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
- * (C) Copyright 2009 Dave Srl www.dave.eu
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/bitops.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/mpc512x.h>
-#include <fdt_support.h>
-#ifdef CONFIG_MISC_INIT_R
-#include <i2c.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
-	gd->ram_size = fixed_sdram(NULL, NULL, 0);
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	u32 tmp;
-
-	tmp = in_be32((u32*)CONFIG_SYS_ARIA_FPGA_BASE);
-	printf("FPGA:  %u-%u.%u.%u\n",
-		(tmp & 0xFF000000) >> 24,
-		(tmp & 0x00FF0000) >> 16,
-		(tmp & 0x0000FF00) >>  8,
-		 tmp & 0x000000FF
-	);
-
-	return 0;
-}
-
-static  iopin_t ioregs_init[] = {
-	/*
-	 * FEC
-	 */
-
-	/* FEC on PSCx_x*/
-	{
-		offsetof(struct ioctrl512x, io_control_psc0_0), 5, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	{
-		offsetof(struct ioctrl512x, io_control_psc1_0), 10, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	{
-		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-
-	/*
-	 * DIU
-	 */
-	/* FUNC2=DIU CLK */
-	{
-		offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
-	},
-	/* FUNC2=DIU_HSYNC */
-	{
-		offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
-	{
-		offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/*
-	 * On board SRAM
-	 */
-	/* FUNC2=/LPC CS6 */
-	{
-		offsetof(struct ioctrl512x, io_control_j1850_rx), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(1) | IO_PIN_ST(1) | IO_PIN_DS(3)
-	},
-};
-
-int checkboard (void)
-{
-	puts("Board: ARIA\n");
-
-	/* initialize function mux & slew rate IO inter alia on IO Pins  */
-
-	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
-
-	return 0;
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/esd/mecp5123/Kconfig b/board/esd/mecp5123/Kconfig
deleted file mode 100644
index 3f2a411196..0000000000
--- a/board/esd/mecp5123/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MECP5123
-
-config SYS_BOARD
-	default "mecp5123"
-
-config SYS_VENDOR
-	default "esd"
-
-config SYS_CONFIG_NAME
-	default "mecp5123"
-
-endif
diff --git a/board/esd/mecp5123/MAINTAINERS b/board/esd/mecp5123/MAINTAINERS
deleted file mode 100644
index ae5fcead90..0000000000
--- a/board/esd/mecp5123/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MECP5123 BOARD
-M:	Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-S:	Maintained
-F:	board/esd/mecp5123/
-F:	include/configs/mecp5123.h
-F:	configs/mecp5123_defconfig
diff --git a/board/esd/mecp5123/Makefile b/board/esd/mecp5123/Makefile
deleted file mode 100644
index f5ebb0144f..0000000000
--- a/board/esd/mecp5123/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= mecp5123.o
diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c
deleted file mode 100644
index 78a6b66110..0000000000
--- a/board/esd/mecp5123/mecp5123.c
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
- * (C) Copyright 2009 Dave Srl www.dave.eu
- * (C) Copyright 2009 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/bitops.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/mpc512x.h>
-#include <fdt_support.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int eeprom_write_enable(unsigned dev_addr, int state)
-{
-	return -ENOSYS;
-}
-
-int board_early_init_f(void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	int i;
-
-	/*
-	 * Initialize Local Window for boot access
-	 */
-	out_be32(&im->sysconf.lpbaw,
-		 CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000));
-	sync_law(&im->sysconf.lpbaw);
-
-	/*
-	 * Configure MSCAN clocks
-	 */
-	for (i=0; i<4; ++i) {
-		out_be32(&im->clk.msccr[i], 0x00300000);
-		out_be32(&im->clk.msccr[i], 0x00310000);
-	}
-
-	/*
-	 * Configure GPIO's
-	 */
-	clrbits_be32(&im->gpio.gpodr, 0x000000e0);
-	clrbits_be32(&im->gpio.gpdir, 0x00ef0000);
-	setbits_be32(&im->gpio.gpdir, 0x001000e0);
-	setbits_be32(&im->gpio.gpdat, 0x00100000);
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size(0, fixed_sdram(NULL, NULL, 0));
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 val;
-
-	/*
-	 * Optimize access to profibus chip (VPC3) on the local bus
-	 */
-
-	/*
-	 * Select 1:1 for LPC_DIV
-	 */
-	val = in_be32(&im->clk.scfr[0]) & ~SCFR1_LPC_DIV_MASK;
-	out_be32(&im->clk.scfr[0], val | (0x1 << SCFR1_LPC_DIV_SHIFT));
-
-	/*
-	 * Configure LPC Chips Select Deadcycle Control Register
-	 * CS0 - device can drive data 2 clock cycle(s) after CS deassertion
-	 * CS1 - device can drive data 1 clock cycle(s) after CS deassertion
-	 */
-	clrbits_be32(&im->lpc.cs_dccr, 0x000000ff);
-	setbits_be32(&im->lpc.cs_dccr, (0x00 << 4) | (0x01 << 0));
-
-	/*
-	 * Configure LPC Chips Select Holdcycle Control Register
-	 * CS0 - data is valid 2 clock cycle(s) after CS deassertion
-	 * CS1 - data is valid 1 clock cycle(s) after CS deassertion
-	 */
-	clrbits_be32(&im->lpc.cs_hccr, 0x000000ff);
-	setbits_be32(&im->lpc.cs_hccr, (0x00 << 4) | (0x01 << 0));
-
-	return 0;
-}
-
-static iopin_t ioregs_init[] = {
-	/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
-	{
-		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
-	{
-		offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=SELECT LPC_CS1 */
-	{
-		offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
-		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=SELECT PSC5_2 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc5_2), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=SELECT PSC5_3 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc5_3), 1, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=SELECT PSC7_3 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc7_3), 1, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=SELECT PSC9_0 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc9_0), 3, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=SELECT PSC10_0 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc10_0), 3, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=SELECT PSC10_3 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc10_3), 1, 0,
-		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=SELECT PSC11_0 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc11_0), 4, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC0=SELECT IRQ0 */
-	{
-		offsetof(struct ioctrl512x, io_control_irq0), 4, 0,
-		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	}
-};
-
-static iopin_t rev2_silicon_pci_ioregs_init[] = {
-	/* FUNC0=PCI Sets next 54 to PCI pads */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
-		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
-	}
-};
-
-int checkboard(void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 spridr;
-
-	puts("Board: MECP_5123\n");
-
-	/*
-	 * Initialize function mux & slew rate IO inter alia on IO
-	 * Pins
-	 */
-	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
-
-	spridr = in_be32(&im->sysconf.spridr);
-	if (SVR_MJREV(spridr) >= 2)
-		iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
-
-	return 0;
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/freescale/mpc5121ads/Kconfig b/board/freescale/mpc5121ads/Kconfig
deleted file mode 100644
index f125f9e596..0000000000
--- a/board/freescale/mpc5121ads/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC5121ADS
-
-config SYS_BOARD
-	default "mpc5121ads"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "mpc5121ads"
-
-endif
diff --git a/board/freescale/mpc5121ads/MAINTAINERS b/board/freescale/mpc5121ads/MAINTAINERS
deleted file mode 100644
index d4aab8fb51..0000000000
--- a/board/freescale/mpc5121ads/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MPC5121ADS BOARD
-#M:	-
-S:	Maintained
-F:	board/freescale/mpc5121ads/
-F:	include/configs/mpc5121ads.h
-F:	configs/mpc5121ads_defconfig
-F:	configs/mpc5121ads_rev2_defconfig
diff --git a/board/freescale/mpc5121ads/Makefile b/board/freescale/mpc5121ads/Makefile
deleted file mode 100644
index 67cf55546b..0000000000
--- a/board/freescale/mpc5121ads/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= mpc5121ads.o
diff --git a/board/freescale/mpc5121ads/README b/board/freescale/mpc5121ads/README
deleted file mode 100644
index 741bc40382..0000000000
--- a/board/freescale/mpc5121ads/README
+++ /dev/null
@@ -1,7 +0,0 @@
-To configure for the current (Rev 3.x) ADS5121
-	make mpc5121ads_config
-This will automatically include PCI, the Real Time CLock, add backup flash
-ability and set the correct frequency and memory configuration.
-
-To configure for the older Rev 2 ADS5121 type (this will not have PCI)
-	make mpc5121ads_rev2_config
diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c
deleted file mode 100644
index d729056fd0..0000000000
--- a/board/freescale/mpc5121ads/mpc5121ads.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * (C) Copyright 2007-2009 DENX Software Engineering
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/bitops.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/mpc512x.h>
-#include <fdt_support.h>
-#ifdef CONFIG_MISC_INIT_R
-#include <i2c.h>
-#endif
-#include <net.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
-
-/* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
-extern int mpc5121_nfc_chip;
-
-/* Control chips select signal on MPC5121ADS board */
-void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
-{
-	unsigned char *csreg = (u8 *)CONFIG_SYS_CPLD_BASE + 0x09;
-	u8 v;
-
-	v = in_8(csreg);
-	v |= 0x0F;
-
-	if (chip >= 0) {
-		__mpc5121_nfc_select_chip(mtd, 0);
-		v &= ~(1 << mpc5121_nfc_chip);
-	} else {
-		__mpc5121_nfc_select_chip(mtd, -1);
-	}
-
-	out_8(csreg, v);
-}
-
-int board_early_init_f(void)
-{
-	/*
-	 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
-	 *
-	 * Without this the flash identification routine fails, as it needs to issue
-	 * write commands in order to establish the device ID.
-	 */
-
-#ifdef CONFIG_MPC5121ADS_REV2
-	out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
-#else
-	if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
-		out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
-	} else {
-		/* running from Backup flash */
-		out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
-	}
-#endif
-	return 0;
-}
-
-int is_micron(void){
-
-	ushort brd_rev = *(vu_short *)(CONFIG_SYS_CPLD_BASE + 0x00);
-	uchar macaddr[6];
-	u32 brddate, macchk, ismicron;
-
-	/*
-	 * MAC address has serial number with date of manufacture
-	 * Boards made before Nov-08 #1180 use Micron memory;
-	 * 001e59 is the STx vendor #
-	 * Default is Elpida since it works for both but is slightly slower
-	 */
-	ismicron = 0;
-	if (brd_rev >= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr)) {
-		brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5];
-		macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2];
-		debug("brddate = %d\n\t", brddate);
-
-		if (macchk == 0x001e59 && brddate <= 8111180)
-			ismicron = 1;
-	} else if (brd_rev < 0x400) {
-		ismicron = 1;
-	}
-	debug("Using %s Memory settings\n\t",
-		ismicron ? "Micron" : "Elpida");
-	return(ismicron);
-}
-
-int dram_init(void)
-{
-	u32 msize = 0;
-	/*
-	 * Elpida MDDRC and initialization settings are an alternative
-	 * to the Default Micron ones for all but the earliest Rev 4 boards
-	 */
-	ddr512x_config_t elpida_mddrc_config = {
-		.ddr_sys_config   = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
-		.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
-		.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
-		.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA,
-	};
-
-	u32 elpida_init_sequence[] = {
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_PCHG_ALL,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_EM2,
-		CONFIG_SYS_DDRCMD_EM3,
-		CONFIG_SYS_DDRCMD_EN_DLL,
-		CONFIG_SYS_ELPIDA_RES_DLL,
-		CONFIG_SYS_DDRCMD_PCHG_ALL,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_ELPIDA_INIT_DEV_OP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_OCD_DEFAULT,
-		CONFIG_SYS_ELPIDA_OCD_EXIT,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP
-	};
-
-	if (is_micron()) {
-		msize = fixed_sdram(NULL, NULL, 0);
-	} else {
-		msize = fixed_sdram(&elpida_mddrc_config,
-				elpida_init_sequence,
-				sizeof(elpida_init_sequence)/sizeof(u32));
-	}
-
-	gd->ram_size = msize;
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	return 0;
-}
-
-static  iopin_t ioregs_init[] = {
-	/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
-	{
-		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* Set highest Slew on 9 PATA pins */
-	{
-		offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1,
-		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
-	{
-		offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=SPDIF_TXCLK */
-	{
-		offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
-	},
-	/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
-	{
-		offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
-	},
-	/* FUNC2=DIU CLK */
-	{
-		offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
-	},
-	/* FUNC2=DIU_HSYNC */
-	{
-		offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
-	{
-		offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	}
-};
-
-static  iopin_t rev2_silicon_pci_ioregs_init[] = {
-	/* FUNC0=PCI Sets next 54 to PCI pads */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
-		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
-	}
-};
-
-int checkboard (void)
-{
-	ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
-	uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 spridr = in_be32(&im->sysconf.spridr);
-
-	printf ("Board: MPC5121ADS rev. 0x%04x (CPLD rev. 0x%02x)\n",
-		brd_rev, cpld_rev);
-
-	/* initialize function mux & slew rate IO inter alia on IO Pins  */
-	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
-
-	if (SVR_MJREV (spridr) >= 2)
-		iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
-
-	return 0;
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/ifm/ac14xx/Kconfig b/board/ifm/ac14xx/Kconfig
deleted file mode 100644
index 97e80d5ddd..0000000000
--- a/board/ifm/ac14xx/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_AC14XX
-
-config SYS_BOARD
-	default "ac14xx"
-
-config SYS_VENDOR
-	default "ifm"
-
-config SYS_CONFIG_NAME
-	default "ac14xx"
-
-endif
diff --git a/board/ifm/ac14xx/MAINTAINERS b/board/ifm/ac14xx/MAINTAINERS
deleted file mode 100644
index 8fd74e516e..0000000000
--- a/board/ifm/ac14xx/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-AC14XX BOARD
-M:	Anatolij Gustschin <agust@denx.de>
-S:	Maintained
-F:	board/ifm/ac14xx/
-F:	include/configs/ac14xx.h
-F:	configs/ac14xx_defconfig
diff --git a/board/ifm/ac14xx/Makefile b/board/ifm/ac14xx/Makefile
deleted file mode 100644
index 55def60417..0000000000
--- a/board/ifm/ac14xx/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= ac14xx.o
diff --git a/board/ifm/ac14xx/ac14xx.c b/board/ifm/ac14xx/ac14xx.c
deleted file mode 100644
index cd79e804a0..0000000000
--- a/board/ifm/ac14xx/ac14xx.c
+++ /dev/null
@@ -1,569 +0,0 @@
-/*
- * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
- * (C) Copyright 2009 Dave Srl www.dave.eu
- * (C) Copyright 2010 ifm ecomatic GmbH
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/bitops.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/mpc512x.h>
-#include <fdt_support.h>
-#ifdef CONFIG_MISC_INIT_R
-#include <i2c.h>
-#endif
-
-static int mac_diag;
-static int gpio_diag;
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void gpio_configure(void)
-{
-	immap_t *im;
-	gpio512x_t *gpioregs;
-
-	im = (immap_t *) CONFIG_SYS_IMMR;
-	gpioregs = &im->gpio;
-	out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */
-	out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */
-
-	/*
-	 * out_be32(&gpioregs->gpdir, 0xC2293020);
-	 * workaround for a hardware effect: configure direction in pieces,
-	 * setting all outputs at once drops the reset line too low and
-	 * makes us lose the MII connection (breaks ethernet for us)
-	 */
-	out_be32(&gpioregs->gpdir, 0x02003060); /* direction */
-	setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */
-	udelay(10);
-	setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */
-	udelay(10);
-	setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */
-	udelay(10);
-	setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */
-
-	/* to turn from red to yellow when U-Boot runs */
-	setbits_be32(&gpioregs->gpdat, 0x00002020);
-	out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */
-	out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */
-	out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */
-	out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */
-}
-
-/* the physical location of the pins */
-#define GPIOKEY_ROW_BITMASK	0x40000000
-#define GPIOKEY_ROW_UPPER	0
-#define GPIOKEY_ROW_LOWER	1
-
-#define GPIOKEY_COL0_BITMASK	0x20000000
-#define GPIOKEY_COL1_BITMASK	0x10000000
-#define GPIOKEY_COL2_BITMASK	0x08000000
-
-/* the logical presentation of pressed keys */
-#define GPIOKEY_BIT_FNLEFT	(1 << 5)
-#define GPIOKEY_BIT_FNRIGHT	(1 << 4)
-#define GPIOKEY_BIT_DIRUP	(1 << 3)
-#define GPIOKEY_BIT_DIRLEFT	(1 << 2)
-#define GPIOKEY_BIT_DIRRIGHT	(1 << 1)
-#define GPIOKEY_BIT_DIRDOWN	(1 << 0)
-
-/* the hotkey combination which starts recovery */
-#define GPIOKEY_BITS_RECOVERY	(GPIOKEY_BIT_FNLEFT | GPIOKEY_BIT_DIRUP | \
-				 GPIOKEY_BIT_DIRDOWN)
-
-static void gpio_selectrow(gpio512x_t *gpioregs, u32 row)
-{
-
-	if (row)
-		setbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
-	else
-		clrbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
-	udelay(10);
-}
-
-static u32 gpio_querykbd(void)
-{
-	immap_t *im;
-	gpio512x_t *gpioregs;
-	u32 keybits;
-	u32 input;
-
-	im = (immap_t *)CONFIG_SYS_IMMR;
-	gpioregs = &im->gpio;
-	keybits = 0;
-
-	/* query upper row */
-	gpio_selectrow(gpioregs, GPIOKEY_ROW_UPPER);
-	input = in_be32(&gpioregs->gpdat);
-	if ((input & GPIOKEY_COL0_BITMASK) == 0)
-		keybits |= GPIOKEY_BIT_FNLEFT;
-	if ((input & GPIOKEY_COL1_BITMASK) == 0)
-		keybits |= GPIOKEY_BIT_DIRUP;
-	if ((input & GPIOKEY_COL2_BITMASK) == 0)
-		keybits |= GPIOKEY_BIT_FNRIGHT;
-
-	/* query lower row */
-	gpio_selectrow(gpioregs, GPIOKEY_ROW_LOWER);
-	input = in_be32(&gpioregs->gpdat);
-	if ((input & GPIOKEY_COL0_BITMASK) == 0)
-		keybits |= GPIOKEY_BIT_DIRLEFT;
-	if ((input & GPIOKEY_COL1_BITMASK) == 0)
-		keybits |= GPIOKEY_BIT_DIRRIGHT;
-	if ((input & GPIOKEY_COL2_BITMASK) == 0)
-		keybits |= GPIOKEY_BIT_DIRDOWN;
-
-	/* return bit pattern for keys */
-	return keybits;
-}
-
-/* excerpt from the recovery's hw_info.h */
-
-struct __attribute__ ((__packed__)) eeprom_layout {
-	char	magic[3];	/** 'ifm' */
-	u8	len[2];		/** content length without magic/len fields */
-	u8	version[3];	/** structure version */
-	u8	type;		/** type of PCB */
-	u8	reserved[0x37];	/** padding up to offset 0x40 */
-	u8	macaddress[6];	/** ethernet MAC (for the mainboard) @0x40 */
-};
-
-#define HW_COMP_MAINCPU 2
-
-static struct eeprom_layout eeprom_content;
-static int eeprom_is_valid;
-static int eeprom_version;
-
-#define get_eeprom_field_int(name) ({ \
-	int value; \
-	int idx; \
-	value = 0; \
-	for (idx = 0; idx < sizeof(name); idx++) { \
-		value <<= 8; \
-		value |= name[idx]; \
-	} \
-	value; \
-})
-
-static int read_eeprom(void)
-{
-	return -ENOSYS;
-}
-
-int mac_read_from_eeprom(void)
-{
-	const u8 *mac;
-	const char *mac_txt;
-
-	if (read_eeprom()) {
-		printf("I2C EEPROM read failed.\n");
-		return -1;
-	}
-
-	if (!eeprom_is_valid) {
-		printf("I2C EEPROM content not valid\n");
-		return -1;
-	}
-
-	mac = NULL;
-	switch (eeprom_version) {
-	case 1:
-	case 2:
-		mac = (const u8 *)&eeprom_content.macaddress;
-		break;
-	}
-
-	if (mac && is_valid_ethaddr(mac)) {
-		eth_setenv_enetaddr("ethaddr", mac);
-		if (mac_diag) {
-			mac_txt = getenv("ethaddr");
-			if (mac_txt)
-				printf("DIAG: MAC value [%s]\n", mac_txt);
-			else
-				printf("DIAG: failed to setup MAC env\n");
-		}
-	}
-
-	return 0;
-}
-
-/*
- * BEWARE!
- * this board uses DDR1(!) Micron SDRAM, *NOT* the DDR2
- * which the ADS, Aria or PDM360NG boards are using
- * (the steps outlined here refer to the Micron datasheet)
- */
-u32 sdram_init_seq[] = {
-	/* item 6, at least one NOP after CKE went high */
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	/* item 7, precharge all; item 8, tRP (20ns) */
-	CONFIG_SYS_DDRCMD_PCHG_ALL,
-	CONFIG_SYS_DDRCMD_NOP,
-	/* item 9, extended mode register; item 10, tMRD 10ns) */
-	CONFIG_SYS_MICRON_EMODE | CONFIG_SYS_MICRON_EMODE_PARAM,
-	CONFIG_SYS_DDRCMD_NOP,
-	/*
-	 * item 11, (base) mode register _with_ reset DLL;
-	 * item 12, tMRD (10ns)
-	 */
-	CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_RSTDLL |
-	CONFIG_SYS_MICRON_BMODE_PARAM,
-	CONFIG_SYS_DDRCMD_NOP,
-	/* item 13, precharge all; item 14, tRP (20ns) */
-	CONFIG_SYS_DDRCMD_PCHG_ALL,
-	CONFIG_SYS_DDRCMD_NOP,
-	/*
-	 * item 15, auto refresh (i.e. refresh with CKE held high);
-	 * item 16, tRFC (70ns)
-	 */
-	CONFIG_SYS_DDRCMD_RFSH,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	/*
-	 * item 17, auto refresh (i.e. refresh with CKE held high);
-	 * item 18, tRFC (70ns)
-	 */
-	CONFIG_SYS_DDRCMD_RFSH,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	/* item 19, optional, unassert DLL reset; item 20, tMRD (20ns) */
-	CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_PARAM,
-	CONFIG_SYS_DDRCMD_NOP,
-	/*
-	 * item 21, "actually done", but make sure 200 DRAM clock cycles
-	 * have passed after DLL reset before READ requests are issued
-	 * (200 cycles at 160MHz -> 1.25 usec)
-	 */
-	/* EMPTY, optional, we don't do it */
-};
-
-int dram_init(void)
-{
-	gd->ram_size = fixed_sdram(NULL, sdram_init_seq,
-				   ARRAY_SIZE(sdram_init_seq));
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	u32 keys;
-	char *s;
-	int want_recovery;
-
-	/* setup GPIO directions and initial values */
-	gpio_configure();
-
-	/*
-	 * enforce the start of the recovery system when
-	 * - the appropriate keys were pressed
-	 * - "some" external software told us to
-	 * - a previous installation was aborted or has failed
-	 */
-	want_recovery = 0;
-	keys = gpio_querykbd();
-	if (gpio_diag)
-		printf("GPIO keyboard status [0x%02X]\n", keys);
-	if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) {
-		printf("detected recovery request (keyboard)\n");
-		want_recovery = 1;
-	}
-	s = getenv("want_recovery");
-	if ((s != NULL) && (*s != '\0')) {
-		printf("detected recovery request (environment)\n");
-		want_recovery = 1;
-	}
-	s = getenv("install_in_progress");
-	if ((s != NULL) && (*s != '\0')) {
-		printf("previous installation has not completed\n");
-		want_recovery = 1;
-	}
-	s = getenv("install_failed");
-	if ((s != NULL) && (*s != '\0')) {
-		printf("previous installation has failed\n");
-		want_recovery = 1;
-	}
-	if (want_recovery) {
-		printf("enforced start of the recovery system\n");
-		setenv("bootcmd", "run recovery");
-	}
-
-	/*
-	 * boot the recovery system without waiting; boot the
-	 * production system without waiting by default, only
-	 * insert a pause (to provide a chance to get a prompt)
-	 * when GPIO keys were pressed during power on
-	 */
-	if (want_recovery)
-		setenv("bootdelay", "0");
-	else if (!keys)
-		setenv("bootdelay", "0");
-	else
-		setenv("bootdelay", "2");
-
-	/* get the ethernet MAC from I2C EEPROM */
-	mac_read_from_eeprom();
-
-	return 0;
-}
-
-/* setup specific IO pad configuration */
-static  iopin_t ioregs_init[] = {
-	{	/* LPC CS3 */
-		offsetof(struct ioctrl512x, io_control_nfc_ce0), 1,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(1) | IO_PIN_DS(2),
-	},
-	{	/* LPC CS1 */
-		offsetof(struct ioctrl512x, io_control_lpc_cs1), 1,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(2),
-	},
-	{	/* LPC CS2 */
-		offsetof(struct ioctrl512x, io_control_lpc_cs2), 1,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(2),
-	},
-	{	/* LPC CS4, CS5 */
-		offsetof(struct ioctrl512x, io_control_pata_ce1), 2,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(1) | IO_PIN_DS(2),
-	},
-	{	/* SDHC CLK, CMD, D0, D1, D2, D3 */
-		offsetof(struct ioctrl512x, io_control_pata_ior), 6,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(1) | IO_PIN_DS(2),
-	},
-	{	/* GPIO keyboard */
-		offsetof(struct ioctrl512x, io_control_pci_ad30), 4,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO DN1 PF, LCD power, DN2 PF */
-		offsetof(struct ioctrl512x, io_control_pci_ad26), 3,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO reset AS-i */
-		offsetof(struct ioctrl512x, io_control_pci_ad21), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO reset safety */
-		offsetof(struct ioctrl512x, io_control_pci_ad19), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO reset netX */
-		offsetof(struct ioctrl512x, io_control_pci_ad16), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO ma2 en */
-		offsetof(struct ioctrl512x, io_control_pci_ad15), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO SD CD, SD WP */
-		offsetof(struct ioctrl512x, io_control_pci_ad08), 2,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* FEC RX DV */
-		offsetof(struct ioctrl512x, io_control_pci_ad06), 1,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(2) | IO_PIN_DS(2),
-	},
-	{	/* GPIO AS-i prog, AS-i done, LCD backlight */
-		offsetof(struct ioctrl512x, io_control_pci_ad05), 3,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO AS-i wdg */
-		offsetof(struct ioctrl512x, io_control_pci_req2), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO safety wdg */
-		offsetof(struct ioctrl512x, io_control_pci_req1), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO netX wdg */
-		offsetof(struct ioctrl512x, io_control_pci_req0), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO IRQ powerfail */
-		offsetof(struct ioctrl512x, io_control_pci_inta), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO AS-i PWRD */
-		offsetof(struct ioctrl512x, io_control_pci_frame), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO LED0, LED1 */
-		offsetof(struct ioctrl512x, io_control_pci_idsel), 2,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO IRQ AS-i 1, IRQ AS-i 2, IRQ safety */
-		offsetof(struct ioctrl512x, io_control_pci_irdy), 3,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* DIU clk */
-		offsetof(struct ioctrl512x, io_control_spdif_txclk), 1,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(2) | IO_PIN_DS(2),
-	},
-	{	/* FEC TX ER, CRS */
-		offsetof(struct ioctrl512x, io_control_spdif_tx), 2,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(1) | IO_PIN_DS(2),
-	},
-	{	/* GPIO/GPT */ /* to *NOT* have the EXT IRQ0 float */
-		offsetof(struct ioctrl512x, io_control_irq0), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/*
-		 * FEC col, tx en, tx clk, txd 0-3, mdc, rx er,
-		 * rdx 3-0, mdio, rx clk
-		 */
-		offsetof(struct ioctrl512x, io_control_psc0_0), 15,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(1) | IO_PIN_DS(2),
-	},
-	/* optional: make sure PSC3 remains the serial console */
-	{	/* LPC CS6 */
-		offsetof(struct ioctrl512x, io_control_psc3_4), 1,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(1) | IO_PIN_DS(2),
-	},
-	/* make sure PSC4 remains available for SPI,
-	    *BUT* PSC4_1 is a GPIO kind of SS! */
-	{	/* enforce drive strength on the SPI pin */
-		offsetof(struct ioctrl512x, io_control_psc4_0), 5,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(2),
-	},
-	{
-		offsetof(struct ioctrl512x, io_control_psc4_1), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	/* optional: make sure PSC5 remains available for SPI */
-	{	/* enforce drive strength on the SPI pin */
-		offsetof(struct ioctrl512x, io_control_psc5_0), 5,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(1),
-	},
-	{	/* LPC TSIZ1 */
-		offsetof(struct ioctrl512x, io_control_psc6_0), 1,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(1) | IO_PIN_DS(2),
-	},
-	{	/* DIU hsync */
-		offsetof(struct ioctrl512x, io_control_psc6_1), 1,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(2) | IO_PIN_DS(1),
-	},
-	{	/* DIU vsync */
-		offsetof(struct ioctrl512x, io_control_psc6_4), 1,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(2) | IO_PIN_DS(1),
-	},
-	{	/* PSC7, part of DIU RGB */
-		offsetof(struct ioctrl512x, io_control_psc7_0), 2,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(2) | IO_PIN_DS(1),
-	},
-	{	/* PSC7, safety UART */
-		offsetof(struct ioctrl512x, io_control_psc7_2), 2,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(0) | IO_PIN_DS(1),
-	},
-	{	/* DIU (part of) RGB[] */
-		offsetof(struct ioctrl512x, io_control_psc8_3), 16,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(2) | IO_PIN_DS(1),
-	},
-	{	/* DIU data enable */
-		offsetof(struct ioctrl512x, io_control_psc11_4), 1,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(2) | IO_PIN_DS(1),
-	},
-	/* reduce LPB drive strength for improved EMI */
-	{	/* LPC OE, LPC RW */
-		offsetof(struct ioctrl512x, io_control_lpc_oe), 2,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(2),
-	},
-	{	/* LPC AX03 through LPC AD00 */
-		offsetof(struct ioctrl512x, io_control_lpc_ax03), 36,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(2),
-	},
-	{	/* LPC CS5 */
-		offsetof(struct ioctrl512x, io_control_pata_ce2), 1,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(2),
-	},
-	{	/* SDHC CLK */
-		offsetof(struct ioctrl512x, io_control_nfc_wp), 1,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(2),
-	},
-	{	/* SDHC DATA */
-		offsetof(struct ioctrl512x, io_control_nfc_ale), 4,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(2),
-	},
-};
-
-int checkboard(void)
-{
-	puts("Board: ifm AC14xx\n");
-
-	/* initialize function mux & slew rate IO inter alia on IO Pins  */
-	iopin_initialize_bits(ioregs_init, ARRAY_SIZE(ioregs_init));
-
-	return 0;
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/ifm/o2dnt2/Kconfig b/board/ifm/o2dnt2/Kconfig
deleted file mode 100644
index e9d32ddc54..0000000000
--- a/board/ifm/o2dnt2/Kconfig
+++ /dev/null
@@ -1,77 +0,0 @@
-if TARGET_O2D
-
-config SYS_BOARD
-	default "o2dnt2"
-
-config SYS_VENDOR
-	default "ifm"
-
-config SYS_CONFIG_NAME
-	default "o2d"
-
-endif
-
-if TARGET_O2D300
-
-config SYS_BOARD
-	default "o2dnt2"
-
-config SYS_VENDOR
-	default "ifm"
-
-config SYS_CONFIG_NAME
-	default "o2d300"
-
-endif
-
-if TARGET_O2DNT2
-
-config SYS_BOARD
-	default "o2dnt2"
-
-config SYS_VENDOR
-	default "ifm"
-
-config SYS_CONFIG_NAME
-	default "o2dnt2"
-
-endif
-
-if TARGET_O2I
-
-config SYS_BOARD
-	default "o2dnt2"
-
-config SYS_VENDOR
-	default "ifm"
-
-config SYS_CONFIG_NAME
-	default "o2i"
-
-endif
-
-if TARGET_O2MNT
-
-config SYS_BOARD
-	default "o2dnt2"
-
-config SYS_VENDOR
-	default "ifm"
-
-config SYS_CONFIG_NAME
-	default "o2mnt"
-
-endif
-
-if TARGET_O3DNT
-
-config SYS_BOARD
-	default "o2dnt2"
-
-config SYS_VENDOR
-	default "ifm"
-
-config SYS_CONFIG_NAME
-	default "o3dnt"
-
-endif
diff --git a/board/ifm/o2dnt2/MAINTAINERS b/board/ifm/o2dnt2/MAINTAINERS
deleted file mode 100644
index 002f89e729..0000000000
--- a/board/ifm/o2dnt2/MAINTAINERS
+++ /dev/null
@@ -1,20 +0,0 @@
-O2DNT2 BOARD
-M:	Anatolij Gustschin <agust@denx.de>
-S:	Maintained
-F:	board/ifm/o2dnt2/
-F:	include/configs/o2d.h
-F:	configs/O2D_defconfig
-F:	include/configs/o2d300.h
-F:	configs/O2D300_defconfig
-F:	include/configs/o2dnt2.h
-F:	configs/O2DNT2_defconfig
-F:	configs/O2DNT2_RAMBOOT_defconfig
-F:	include/configs/o2i.h
-F:	configs/O2I_defconfig
-F:	include/configs/o2mnt.h
-F:	configs/O2MNT_defconfig
-F:	configs/O2MNT_O2M110_defconfig
-F:	configs/O2MNT_O2M112_defconfig
-F:	configs/O2MNT_O2M113_defconfig
-F:	include/configs/o3dnt.h
-F:	configs/O3DNT_defconfig
diff --git a/board/ifm/o2dnt2/Makefile b/board/ifm/o2dnt2/Makefile
deleted file mode 100644
index 64d6ba8c55..0000000000
--- a/board/ifm/o2dnt2/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2005-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= o2dnt2.o
diff --git a/board/ifm/o2dnt2/o2dnt2.c b/board/ifm/o2dnt2/o2dnt2.c
deleted file mode 100644
index 7770806bd2..0000000000
--- a/board/ifm/o2dnt2/o2dnt2.c
+++ /dev/null
@@ -1,388 +0,0 @@
-/*
- * Partially derived from board code for digsyMTC,
- * (C) Copyright 2009
- * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
- *
- * (C) Copyright 2012
- * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <net.h>
-#include <pci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define SDRAM_MODE	0x00CD0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xD2322800
-#define SDRAM_CONFIG2	0x8AD70000
-
-enum ifm_sensor_type {
-	O2DNT		= 0x00,	/* !< O2DNT 32MB */
-	O2DNT2		= 0x01,	/* !< O2DNT2 64MB */
-	O3DNT		= 0x02,	/* !< O3DNT 32MB */
-	O3DNT_MIN	= 0x40,	/* !< O3DNT Minerva 32MB */
-	UNKNOWN		= 0xff,	/* !< Unknow sensor */
-};
-
-static enum ifm_sensor_type gt_ifm_sensor_type;
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start(int hi_addr)
-{
-	struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-	long control = SDRAM_CONTROL | hi_addr_bit;
-
-	/* unlock mode register */
-	out_be32(&sdram->ctrl, control | 0x80000000);
-
-	/* precharge all banks */
-	out_be32(&sdram->ctrl, control | 0x80000002);
-
-	/* auto refresh */
-	out_be32(&sdram->ctrl, control | 0x80000004);
-
-	/* set mode register */
-	out_be32(&sdram->mode, SDRAM_MODE);
-
-	/* normal operation */
-	out_be32(&sdram->ctrl, control);
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced dram_init does NOT make real use
- *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if
- *            CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
- */
-int dram_init(void)
-{
-	struct mpc5xxx_mmap_ctl *mmap_ctl =
-		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
-	struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-	uint svr, pvr;
-
-	if (gt_ifm_sensor_type == O2DNT2) {
-		/* activate SDRAM CS1 */
-		setbits_be32((void *)MPC5XXX_GPS_PORT_CONFIG, 0x80000000);
-	}
-
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	out_be32(&mmap_ctl->sdram0, 0x0000001E); /* 2 GB at 0x0 */
-	out_be32(&mmap_ctl->sdram1, 0x00000000); /* disabled */
-
-	/* setup config registers */
-	out_be32(&sdram->config1, SDRAM_CONFIG1);
-	out_be32(&sdram->config2, SDRAM_CONFIG2);
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		out_be32(&mmap_ctl->sdram0,
-			 (0x13 + __builtin_ffs(dramsize >> 20) - 1));
-	} else {
-		out_be32(&mmap_ctl->sdram0, 0); /* disabled */
-	}
-
-	/* let SDRAM CS1 start right after CS0 */
-	out_be32(&mmap_ctl->sdram1, dramsize + 0x0000001E); /* 2G */
-
-	/* find RAM size using SDRAM CS1 only */
-	if (!dramsize)
-		sdram_start(0);
-
-	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
-					0x80000000);
-	if (!dramsize) {
-		sdram_start(1);
-		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
-					0x80000000);
-	}
-
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize2 = test1;
-	} else {
-		dramsize2 = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize2 < (1 << 20))
-		dramsize2 = 0;
-
-	/* set SDRAM CS1 size according to the amount of RAM found */
-	if (dramsize2 > 0) {
-		out_be32(&mmap_ctl->sdram1, (dramsize |
-			 (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
-	} else {
-		out_be32(&mmap_ctl->sdram1, dramsize); /* disabled */
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = in_be32(&mmap_ctl->sdram0) & 0xFF;
-	if (dramsize >= 0x13)
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	else
-		dramsize = 0;
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = in_be32(&mmap_ctl->sdram1) & 0xFF;
-	if (dramsize2 >= 0x13)
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	else
-		dramsize2 = 0;
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	svr = get_svr();
-	pvr = get_pvr();
-	if ((SVR_MJREV(svr) >= 2) &&
-	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
-		out_be32(&sdram->sdelay, 0x04);
-
-	gd->ram_size = dramsize + dramsize2;
-
-	return 0;
-}
-
-
-#define GPT_GPIO_IN	0x4
-
-int checkboard(void)
-{
-	struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
-	unsigned char board_config = 0;
-	int i;
-
-	/* switch gpt0 - gpt7 to input */
-	for (i = 0; i < 7; i++)
-		out_be32(&gpt[i].emsr, GPT_GPIO_IN);
-
-	/* get configuration byte on timer-port */
-	for (i = 0; i < 7; i++)
-		board_config |= (in_be32(&gpt[i].sr) & 0x100) >> (8 - i);
-
-	puts("Board: ");
-
-	switch (board_config) {
-	case 0:
-		puts("O2DNT\n");
-		gt_ifm_sensor_type = O2DNT;
-		break;
-	case 1:
-		puts("O3DNT\n");
-		gt_ifm_sensor_type = O3DNT;
-		break;
-	case 2:
-		puts("O2DNT2\n");
-		gt_ifm_sensor_type = O2DNT2;
-		break;
-	case 64:
-		puts("O3DNT Minerva\n");
-		gt_ifm_sensor_type = O3DNT_MIN;
-		break;
-	default:
-		puts("Unknown\n");
-		gt_ifm_sensor_type = UNKNOWN;
-		break;
-	}
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	struct mpc5xxx_lpb *lpb_regs = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
-
-	/*
-	 * Now, when we are in RAM, enable flash write access for detection
-	 * process. Note that CS_BOOT cannot be cleared when executing in flash.
-	 */
-	clrbits_be32(&lpb_regs->cs0_cfg, 1); /* clear RO */
-	/* disable CS_BOOT */
-	clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
-	/* enable CS0 */
-	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
-
-	return 0;
-}
-
-#define MIIM_LXT971_LED_CFG_REG		0x14
-#define LXT971_LED_CFG_LINK_STATUS	0x4000
-#define LXT971_LED_CFG_RX_TX_ACTIVITY	0x0700
-#define LXT971_LED_CFG_LINK_ACTIVITY	0x00D0
-#define LXT971_LED_CFG_PULSE_STRETCH	0x0002
-/*
- * Additional PHY intialization after reset in mpc5xxx_fec_init_phy()
- */
-void reset_phy(void)
-{
-	/*
-	 * Set LED configuration bits.
-	 * It can't be done in misc_init_r() since FEC is not
-	 * initialized at this time. Therefore we do it here.
-	 */
-	miiphy_write("FEC", CONFIG_PHY_ADDR, MIIM_LXT971_LED_CFG_REG,
-			LXT971_LED_CFG_LINK_STATUS |
-			LXT971_LED_CFG_RX_TX_ACTIVITY |
-			LXT971_LED_CFG_LINK_ACTIVITY |
-			LXT971_LED_CFG_PULSE_STRETCH);
-}
-
-#if defined(CONFIG_POST)
-/*
- * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
- * is left open, no keypress is detected.
- */
-int post_hotkeys_pressed(void)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *) MPC5XXX_GPIO;
-
-	/*
-	 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
-	 * CODEC or UART mode. Consumer IrDA should still be possible.
-	 */
-	clrbits_be32(&gpio->port_config, 0x07000000);
-	setbits_be32(&gpio->port_config, 0x03000000);
-
-	/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
-	setbits_be32(&gpio->simple_gpioe, 0x20000000);
-
-	/* Configure GPIO_IRDA_1 as input */
-	clrbits_be32(&gpio->simple_ddr, 0x20000000);
-
-	return (in_be32(&gpio->simple_ival) & 0x20000000) ? 0 : 1;
-}
-#endif
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
-static void ft_adapt_flash_base(void *blob)
-{
-	flash_info_t	*dev = &flash_info[0];
-	int off;
-	struct fdt_property *prop;
-	int len;
-	u32 *reg, *reg2;
-
-	off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
-	if (off < 0) {
-		printf("Could not find fsl,mpc5200b-lpb node.\n");
-		return;
-	}
-
-	/* found compatible property */
-	prop = fdt_get_property_w(blob, off, "ranges", &len);
-	if (prop) {
-		reg = reg2 = (u32 *)&prop->data[0];
-
-		reg[2] = dev->start[0];
-		reg[3] = dev->size;
-		fdt_setprop(blob, off, "ranges", reg2, len);
-	} else
-		printf("Could not find ranges\n");
-}
-
-extern ulong flash_get_size(phys_addr_t base, int banknum);
-
-/* Update the flash baseaddr settings */
-int update_flash_size(int flash_size)
-{
-	struct mpc5xxx_mmap_ctl *mm =
-		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
-	flash_info_t *dev;
-	int i;
-	int size = 0;
-	unsigned long base = 0x0;
-	u32 *cs_reg = (u32 *)&mm->cs0_start;
-
-	for (i = 0; i < 2; i++) {
-		dev = &flash_info[i];
-
-		if (dev->size) {
-			/* calculate new base addr for this chipselect */
-			base -= dev->size;
-			out_be32(cs_reg, START_REG(base));
-			cs_reg++;
-			out_be32(cs_reg, STOP_REG(base, dev->size));
-			cs_reg++;
-			/* recalculate the sectoraddr in the cfi driver */
-			size += flash_get_size(base, i);
-		}
-	}
-	flash_protect_default();
-	gd->bd->bi_flashstart = base;
-	return 0;
-}
-#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	int phy_addr = CONFIG_PHY_ADDR;
-	char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
-
-	ft_cpu_setup(blob, bd);
-
-#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
-#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
-	/* Update reg property in all nor flash nodes too */
-	fdt_fixup_nor_flash_size(blob);
-#endif
-	ft_adapt_flash_base(blob);
-#endif
-	/* fix up the phy address */
-	do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/inka4x0/Kconfig b/board/inka4x0/Kconfig
deleted file mode 100644
index 94a41f01a5..0000000000
--- a/board/inka4x0/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_INKA4X0
-
-config SYS_BOARD
-	default "inka4x0"
-
-config SYS_CONFIG_NAME
-	default "inka4x0"
-
-endif
diff --git a/board/inka4x0/MAINTAINERS b/board/inka4x0/MAINTAINERS
deleted file mode 100644
index e8cec73a1a..0000000000
--- a/board/inka4x0/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-INKA4X0 BOARD
-M:	Anatolij Gustschin <agust@denx.de>
-S:	Maintained
-F:	board/inka4x0/
-F:	include/configs/inka4x0.h
-F:	configs/inka4x0_defconfig
diff --git a/board/inka4x0/Makefile b/board/inka4x0/Makefile
deleted file mode 100644
index c9a3540799..0000000000
--- a/board/inka4x0/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2009
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= inka4x0.o inkadiag.o
diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c
deleted file mode 100644
index 88cae59e8f..0000000000
--- a/board/inka4x0/inka4x0.c
+++ /dev/null
@@ -1,254 +0,0 @@
-/*
- * (C) Copyright 2008-2009
- * Andreas Pfefferle, DENX Software Engineering, ap@denx.de.
- *
- * (C) Copyright 2009
- * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2004
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/io.h>
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-
-#if defined(CONFIG_DDR_MT46V16M16)
-#include "mt46v16m16-75.h"
-#elif defined(CONFIG_SDR_MT48LC16M16A2)
-#include "mt48lc16m16a2-75.h"
-#elif defined(CONFIG_DDR_MT46V32M16)
-#include "mt46v32m16.h"
-#elif defined(CONFIG_DDR_HYB25D512160BF)
-#include "hyb25d512160bf.h"
-#elif defined(CONFIG_DDR_K4H511638C)
-#include "k4h511638c.h"
-#else
-#error "INKA4x0 SDRAM: invalid chip type specified!"
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
-	volatile struct mpc5xxx_sdram *sdram =
-		(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);
-
-	/* precharge all banks */
-	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
-
-#if SDRAM_DDR
-	/* set mode register: extended mode */
-	out_be32(&sdram->mode, SDRAM_EMODE);
-
-	/* set mode register: reset DLL */
-	out_be32(&sdram->mode, SDRAM_MODE | 0x04000000);
-#endif
-
-	/* precharge all banks */
-	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
-
-	/* auto refresh */
-	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);
-
-	/* set mode register */
-	out_be32(&sdram->mode, SDRAM_MODE);
-
-	/* normal operation */
-	out_be32(&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced dram_init does NOT make real use
- *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- *	      is something else than 0x00000000.
- */
-
-int dram_init(void)
-{
-	volatile struct mpc5xxx_mmap_ctl *mm =
-		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
-	volatile struct mpc5xxx_cdm     *cdm =
-		(struct mpc5xxx_cdm *)      MPC5XXX_CDM;
-	volatile struct mpc5xxx_sdram *sdram =
-		(struct mpc5xxx_sdram *)    MPC5XXX_SDRAM;
-	ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	long test1, test2;
-
-	/* setup SDRAM chip selects */
-	out_be32(&mm->sdram0, 0x0000001c);	/* 512MB at 0x0 */
-	out_be32(&mm->sdram1, 0x40000000);	/* disabled */
-
-	/* setup config registers */
-	out_be32(&sdram->config1, SDRAM_CONFIG1);
-	out_be32(&sdram->config2, SDRAM_CONFIG2);
-
-#if SDRAM_DDR
-	/* set tap delay */
-	out_be32(&cdm->porcfg, SDRAM_TAPDELAY);
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20)) {
-		dramsize = 0;
-	}
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		out_be32(&mm->sdram0, 0x13 +
-			 __builtin_ffs(dramsize >> 20) - 1);
-	} else {
-		out_be32(&mm->sdram0, 0); /* disabled */
-	}
-
-	out_be32(&mm->sdram1, dramsize); /* disabled */
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = in_be32(&mm->sdram0) & 0xFF;
-	if (dramsize >= 0x13) {
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	} else {
-		dramsize = 0;
-	}
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	gd->ram_size = dramsize;
-
-	return 0;
-}
-
-int checkboard (void)
-{
-	puts ("Board: INKA 4X0\n");
-	return 0;
-}
-
-void flash_preinit(void)
-{
-	volatile struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
-
-	/*
-	 * Now, when we are in RAM, enable flash write
-	 * access for detection process.
-	 * Note that CS_BOOT (CS0) cannot be cleared when
-	 * executing in flash.
-	 */
-	clrbits_be32(&lpb->cs0_cfg, 0x1); /* clear RO */
-}
-
-int misc_init_f (void)
-{
-	volatile struct mpc5xxx_gpio	*gpio    =
-		(struct mpc5xxx_gpio *)   MPC5XXX_GPIO;
-	volatile struct mpc5xxx_wu_gpio	*wu_gpio =
-		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
-	volatile struct mpc5xxx_gpt	*gpt;
-	char tmp[10];
-	int i, br;
-
-	i = getenv_f("brightness", tmp, sizeof(tmp));
-	br = (i > 0)
-		? (int) simple_strtoul (tmp, NULL, 10)
-		: CONFIG_SYS_BRIGHTNESS;
-	if (br > 255)
-		br = 255;
-
-	/* Initialize GPIO output pins.
-	 */
-	/* Configure GPT as GPIO output (and set them as they control low-active LEDs */
-	for (i = 0; i <= 5; i++) {
-		gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (i * 0x10));
-		out_be32(&gpt->emsr, 0x34);
-	}
-
-	/* Configure GPT7 as PWM timer, 1kHz, no ints. */
-	gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (7 * 0x10));
-	out_be32(&gpt->emsr,  0);		/* Disable */
-	out_be32(&gpt->cir,   0x020000fe);
-	out_be32(&gpt->pwmcr, (br << 16));
-	out_be32(&gpt->emsr,  0x3);		/* Enable PWM mode and start */
-
-	/* Configure PSC3_6,7 as GPIO output */
-	setbits_be32(&gpio->simple_gpioe, MPC5XXX_GPIO_SIMPLE_PSC3_6 |
-					  MPC5XXX_GPIO_SIMPLE_PSC3_7);
-	setbits_be32(&gpio->simple_ddr,   MPC5XXX_GPIO_SIMPLE_PSC3_6 |
-					  MPC5XXX_GPIO_SIMPLE_PSC3_7);
-
-	/* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
-	setbits_8(&wu_gpio->enable,  MPC5XXX_GPIO_WKUP_6 |
-				     MPC5XXX_GPIO_WKUP_7 |
-				     MPC5XXX_GPIO_WKUP_PSC3_9);
-	setbits_8(&wu_gpio->ddr,     MPC5XXX_GPIO_WKUP_6 |
-				     MPC5XXX_GPIO_WKUP_7 |
-				     MPC5XXX_GPIO_WKUP_PSC3_9);
-
-	/* Set LR mirror bit because it is low-active */
-	setbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_7);
-
-	/* Reset Coral-P graphics controller */
-	setbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_PSC3_9);
-
-	/* Enable display backlight */
-	clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_8);
-	setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_8);
-	setbits_8(&gpio->sint_ddr,   MPC5XXX_GPIO_SINT_PSC3_8);
-	setbits_8(&gpio->sint_dvo,   MPC5XXX_GPIO_SINT_PSC3_8);
-
-	/*
-	 * Configure three wire serial interface to RTC (PSC1_4,
-	 * PSC2_4, PSC3_4, PSC3_5)
-	 */
-	setbits_8(&wu_gpio->enable,  MPC5XXX_GPIO_WKUP_PSC1_4 |
-				     MPC5XXX_GPIO_WKUP_PSC2_4);
-	setbits_8(&wu_gpio->ddr,     MPC5XXX_GPIO_WKUP_PSC1_4 |
-				     MPC5XXX_GPIO_WKUP_PSC2_4);
-	clrbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_PSC1_4);
-	clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_4 |
-				     MPC5XXX_GPIO_SINT_PSC3_5);
-	setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_4 |
-				     MPC5XXX_GPIO_SINT_PSC3_5);
-	setbits_8(&gpio->sint_ddr,   MPC5XXX_GPIO_SINT_PSC3_5);
-	clrbits_8(&gpio->sint_dvo,   MPC5XXX_GPIO_SINT_PSC3_5);
-
-	return 0;
-}
-
-#ifdef	CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
diff --git a/board/inka4x0/inkadiag.c b/board/inka4x0/inkadiag.c
deleted file mode 100644
index 4c43205129..0000000000
--- a/board/inka4x0/inkadiag.c
+++ /dev/null
@@ -1,465 +0,0 @@
-/*
- * (C) Copyright 2008, 2009 Andreas Pfefferle,
- *     DENX Software Engineering, ap@denx.de.
- * (C) Copyright 2009 Detlev Zundel,
- *     DENX Software Engineering, dzu@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/io.h>
-#include <common.h>
-#include <config.h>
-#include <console.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-
-#include <command.h>
-
-/* This is needed for the includes in ns16550.h */
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#include <ns16550.h>
-
-#define GPIO_BASE		((u_char *)CONFIG_SYS_CS3_START)
-
-#define DIGIN_TOUCHSCR_MASK	0x00003000	/* Inputs 12-13 */
-#define DIGIN_KEYB_MASK		0x00010000	/* Input 16 */
-
-#define DIGIN_DRAWER_SW1	0x00400000	/* Input 22 */
-#define DIGIN_DRAWER_SW2	0x00800000	/* Input 23 */
-
-#define DIGIO_LED0		0x00000001	/* Output 0 */
-#define DIGIO_LED1		0x00000002	/* Output 1 */
-#define DIGIO_LED2		0x00000004	/* Output 2 */
-#define DIGIO_LED3		0x00000008	/* Output 3 */
-#define DIGIO_LED4		0x00000010	/* Output 4 */
-#define DIGIO_LED5		0x00000020	/* Output 5 */
-
-#define DIGIO_DRAWER1		0x00000100	/* Output 8 */
-#define DIGIO_DRAWER2		0x00000200	/* Output 9 */
-
-#define SERIAL_PORT_BASE	((u_char *)CONFIG_SYS_CS2_START)
-
-#define PSC_OP1_RTS	0x01
-#define PSC_OP0_RTS	0x01
-
-/*
- * Table with supported baudrates (defined in inka4x0.h)
- */
-static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE;
-#define	N_BAUDRATES (sizeof(baudrate_table) / sizeof(baudrate_table[0]))
-
-static unsigned int inka_digin_get_input(void)
-{
-	return in_8(GPIO_BASE + 0) << 0 | in_8(GPIO_BASE + 1) << 8 |
-		in_8(GPIO_BASE + 2) << 16 | in_8(GPIO_BASE + 3) << 24;
-}
-
-#define LED_HIGH(NUM)							\
-	do {								\
-		setbits_be32((unsigned *)MPC5XXX_GPT##NUM##_ENABLE, 0x10); \
-	} while (0)
-
-#define LED_LOW(NUM)							\
-	do {								\
-		clrbits_be32((unsigned *)MPC5XXX_GPT##NUM##_ENABLE, 0x10); \
-	} while (0)
-
-#define CHECK_LED(NUM) \
-    do { \
-	    if (state & (1 << NUM)) {		\
-		    LED_HIGH(NUM);		\
-	    } else {				\
-		    LED_LOW(NUM);		\
-	    }					\
-    } while (0)
-
-static void inka_digio_set_output(unsigned int state, int which)
-{
-	volatile struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
-	if (which == 0) {
-		/* other */
-		CHECK_LED(0);
-		CHECK_LED(1);
-		CHECK_LED(2);
-		CHECK_LED(3);
-		CHECK_LED(4);
-		CHECK_LED(5);
-	} else {
-		if (which == 1) {
-			/* drawer1 */
-			if (state) {
-				clrbits_be32(&gpio->simple_dvo, 0x1000);
-				udelay(1);
-				setbits_be32(&gpio->simple_dvo, 0x1000);
-			} else {
-				setbits_be32(&gpio->simple_dvo, 0x1000);
-				udelay(1);
-				clrbits_be32(&gpio->simple_dvo, 0x1000);
-			}
-		}
-		if (which == 2) {
-			/* drawer 2 */
-			if (state) {
-				clrbits_be32(&gpio->simple_dvo, 0x2000);
-				udelay(1);
-				setbits_be32(&gpio->simple_dvo, 0x2000);
-			} else {
-				setbits_be32(&gpio->simple_dvo, 0x2000);
-				udelay(1);
-				clrbits_be32(&gpio->simple_dvo, 0x2000);
-			}
-		}
-	}
-	udelay(1);
-}
-
-static int do_inkadiag_io(cmd_tbl_t *cmdtp, int flag, int argc,
-			  char * const argv[]) {
-	unsigned int state, val;
-
-	switch (argc) {
-	case 3:
-		/* Write a value */
-		val = simple_strtol(argv[2], NULL, 16);
-
-		if (strcmp(argv[1], "drawer1") == 0) {
-			inka_digio_set_output(val, 1);
-		} else if (strcmp(argv[1], "drawer2") == 0) {
-			inka_digio_set_output(val, 2);
-		} else if (strcmp(argv[1], "other") == 0)
-			inka_digio_set_output(val, 0);
-		else {
-			printf("Invalid argument: %s\n", argv[1]);
-			return -1;
-		}
-		/* fall through */
-	case 2:
-		/* Read a value */
-		state = inka_digin_get_input();
-
-		if (strcmp(argv[1], "drawer1") == 0) {
-			val = (state & DIGIN_DRAWER_SW1) >> (ffs(DIGIN_DRAWER_SW1) - 1);
-		} else if (strcmp(argv[1], "drawer2") == 0) {
-			val = (state & DIGIN_DRAWER_SW2) >> (ffs(DIGIN_DRAWER_SW2) - 1);
-		} else if (strcmp(argv[1], "other") == 0) {
-			val = ((state & DIGIN_KEYB_MASK) >> (ffs(DIGIN_KEYB_MASK) - 1))
-				| (state & DIGIN_TOUCHSCR_MASK) >> (ffs(DIGIN_TOUCHSCR_MASK) - 2);
-		} else {
-			printf("Invalid argument: %s\n", argv[1]);
-			return -1;
-		}
-		printf("exit code: 0x%X\n", val);
-		return 0;
-	default:
-		return cmd_usage(cmdtp);
-	}
-
-	return -1;
-}
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int ser_init(volatile struct mpc5xxx_psc *psc, int baudrate)
-{
-	unsigned long baseclk;
-	int div;
-
-	/* reset PSC */
-	out_8(&psc->command, PSC_SEL_MODE_REG_1);
-
-	/* select clock sources */
-
-	out_be16(&psc->psc_clock_select, 0);
-	baseclk = (gd->arch.ipb_clk + 16) / 32;
-
-	/* switch to UART mode */
-	out_be32(&psc->sicr, 0);
-
-	/* configure parity, bit length and so on */
-
-	out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE);
-	out_8(&psc->mode, PSC_MODE_ONE_STOP);
-
-	/* set up UART divisor */
-	div = (baseclk + (baudrate / 2)) / baudrate;
-	out_8(&psc->ctur, (div >> 8) & 0xff);
-	out_8(&psc->ctlr, div & 0xff);
-
-	/* disable all interrupts */
-	out_be16(&psc->psc_imr, 0);
-
-	/* reset and enable Rx/Tx */
-	out_8(&psc->command, PSC_RST_RX);
-	out_8(&psc->command, PSC_RST_TX);
-	out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE);
-
-	return 0;
-}
-
-static void ser_putc(volatile struct mpc5xxx_psc *psc, const char c)
-{
-	/* Wait 1 second for last character to go. */
-	int i = 0;
-
-	while (!(psc->psc_status & PSC_SR_TXEMP) && (i++ < 1000000/10))
-		udelay(10);
-	psc->psc_buffer_8 = c;
-
-}
-
-static int ser_getc(volatile struct mpc5xxx_psc *psc)
-{
-	/* Wait for a character to arrive. */
-	int i = 0;
-
-	while (!(in_be16(&psc->psc_status) & PSC_SR_RXRDY) && (i++ < 1000000/10))
-		udelay(10);
-
-	return in_8(&psc->psc_buffer_8);
-}
-
-static int do_inkadiag_serial(cmd_tbl_t *cmdtp, int flag, int argc,
-			      char * const argv[]) {
-	volatile struct NS16550 *uart;
-	volatile struct mpc5xxx_psc *psc;
-	unsigned int num, mode;
-	int combrd, baudrate, i, j, len;
-	int address;
-
-	if (argc < 5)
-		return cmd_usage(cmdtp);
-
-	argc--;
-	argv++;
-
-	num = simple_strtol(argv[0], NULL, 0);
-	if (num < 0 || num > 11) {
-		printf("invalid argument for num: %d\n", num);
-		return -1;
-	}
-
-	mode = simple_strtol(argv[1], NULL, 0);
-
-	combrd = 0;
-	baudrate = simple_strtoul(argv[2], NULL, 10);
-	for (i=0; i<N_BAUDRATES; ++i) {
-		if (baudrate == baudrate_table[i])
-			break;
-	}
-	if (i == N_BAUDRATES) {
-		printf("## Baudrate %d bps not supported\n",
-		       baudrate);
-		return 1;
-	}
-	combrd = 115200 / baudrate;
-
-	uart = (struct NS16550 *)(SERIAL_PORT_BASE + (num << 3));
-
-	printf("Testing uart %d.\n\n", num);
-
-	if ((num >= 0) && (num <= 7)) {
-		if (mode & 1) {
-			/* turn on 'loopback' mode */
-			out_8(&uart->mcr, UART_MCR_LOOP);
-		} else {
-			/*
-			 * establish the UART's operational parameters
-			 * set DLAB=1, so rbr accesses DLL
-			 */
-			out_8(&uart->lcr, UART_LCR_DLAB);
-			/* set baudrate */
-			out_8(&uart->rbr, combrd);
-			/* set data-format: 8-N-1 */
-			out_8(&uart->lcr, UART_LCR_WLS_8);
-		}
-
-		if (mode & 2) {
-			/* set request to send */
-			out_8(&uart->mcr, UART_MCR_RTS);
-			udelay(10);
-			/* check clear to send */
-			if ((in_8(&uart->msr) & UART_MSR_CTS) == 0x00)
-				return -1;
-		}
-		if (mode & 4) {
-			/* set data terminal ready */
-			out_8(&uart->mcr, UART_MCR_DTR);
-			udelay(10);
-			/* check data set ready and carrier detect */
-			if ((in_8(&uart->msr) & (UART_MSR_DSR | UART_MSR_DCD))
-			    != (UART_MSR_DSR | UART_MSR_DCD))
-				return -1;
-		}
-
-		/* write each message-character, read it back, and display it */
-		for (i = 0, len = strlen(argv[3]); i < len; ++i) {
-			j = 0;
-			while ((in_8(&uart->lsr) & UART_LSR_THRE) ==	0x00) {
-				if (j++ > CONFIG_SYS_HZ)
-					break;
-				udelay(10);
-			}
-			out_8(&uart->rbr, argv[3][i]);
-			j = 0;
-			while ((in_8(&uart->lsr) & UART_LSR_DR) == 0x00) {
-				if (j++ > CONFIG_SYS_HZ)
-					break;
-				udelay(10);
-			}
-			printf("%c", in_8(&uart->rbr));
-		}
-		printf("\n\n");
-		out_8(&uart->mcr, 0x00);
-	} else {
-		address = 0;
-
-		switch (num) {
-		case 8:
-			address = MPC5XXX_PSC6;
-			break;
-		case 9:
-			address = MPC5XXX_PSC3;
-			break;
-		case 10:
-			address = MPC5XXX_PSC2;
-			break;
-		case 11:
-			address = MPC5XXX_PSC1;
-			break;
-		}
-		psc = (struct mpc5xxx_psc *)address;
-		ser_init(psc, simple_strtol(argv[2], NULL, 0));
-		if (mode & 2) {
-			/* set request to send */
-			out_8(&psc->op0, PSC_OP0_RTS);
-			udelay(10);
-			/* check clear to send */
-			if ((in_8(&psc->ip) & PSC_IPCR_CTS) == 0)
-				return -1;
-		}
-		len = strlen(argv[3]);
-		for (i = 0; i < len; ++i) {
-			ser_putc(psc, argv[3][i]);
-			printf("%c", ser_getc(psc));
-		}
-		printf("\n\n");
-	}
-	return 0;
-}
-
-#define BUZZER_GPT	(MPC5XXX_GPT + 0x60)	/* GPT6 */
-static void buzzer_turn_on(unsigned int freq)
-{
-	volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)(BUZZER_GPT);
-
-	const u32 prescale = gd->arch.ipb_clk / freq / 128;
-	const u32 count = 128;
-	const u32 width = 64;
-
-	gpt->cir = (prescale << 16) | count;
-	gpt->pwmcr = width << 16;
-	gpt->emsr = 3;		/* Timer enabled for PWM */
-}
-
-static void buzzer_turn_off(void)
-{
-	volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)(BUZZER_GPT);
-
-	gpt->emsr = 0;
-}
-
-static int do_inkadiag_buzzer(cmd_tbl_t *cmdtp, int flag, int argc,
-			      char * const argv[]) {
-
-	unsigned int period, freq;
-	int prev, i;
-
-	if (argc != 3)
-		return cmd_usage(cmdtp);
-
-	argc--;
-	argv++;
-
-	period = simple_strtol(argv[0], NULL, 0);
-	if (!period)
-		printf("Zero period is senseless\n");
-	argc--;
-	argv++;
-
-	freq = simple_strtol(argv[0], NULL, 0);
-	/* avoid zero prescale in buzzer_turn_on() */
-	if (freq > gd->arch.ipb_clk / 128) {
-		printf("%dHz exceeds maximum (%ldHz)\n", freq,
-		       gd->arch.ipb_clk / 128);
-	} else if (!freq)
-		printf("Zero frequency is senseless\n");
-	else
-		buzzer_turn_on(freq);
-
-	clear_ctrlc();
-	prev = disable_ctrlc(0);
-
-	printf("Buzzing for %d ms. Type ^C to abort!\n\n", period);
-
-	i = 0;
-	while (!ctrlc() && (i++ < CONFIG_SYS_HZ))
-		udelay(period);
-
-	clear_ctrlc();
-	disable_ctrlc(prev);
-
-	buzzer_turn_off();
-
-	return 0;
-}
-
-static int do_inkadiag_help(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
-cmd_tbl_t cmd_inkadiag_sub[] = {
-	U_BOOT_CMD_MKENT(io, 1, 1, do_inkadiag_io, "read digital input",
-	 "<drawer1|drawer2|other> [value] - get or set specified signal"),
-	U_BOOT_CMD_MKENT(serial, 4, 1, do_inkadiag_serial, "test serial port",
-	 "<num> <mode> <baudrate> <msg>  - test uart num [0..11] in mode\n"
-	 "and baudrate with msg"),
-	U_BOOT_CMD_MKENT(buzzer, 2, 1, do_inkadiag_buzzer, "activate buzzer",
-	 "<period> <freq> - turn buzzer on for period ms with freq hz"),
-	U_BOOT_CMD_MKENT(help, 4, 1, do_inkadiag_help, "get help",
-	 "[command] - get help for command"),
-};
-
-static int do_inkadiag_help(cmd_tbl_t *cmdtp, int flag,
-			    int argc, char * const argv[]) {
-	extern int _do_help (cmd_tbl_t *cmd_start, int cmd_items,
-			     cmd_tbl_t *cmdtp, int flag,
-			     int argc, char * const argv[]);
-	/* do_help prints command name - we prepend inkadiag to our subcommands! */
-#ifdef CONFIG_SYS_LONGHELP
-	puts ("inkadiag ");
-#endif
-	return _do_help(&cmd_inkadiag_sub[0],
-		ARRAY_SIZE(cmd_inkadiag_sub), cmdtp, flag, argc, argv);
-}
-
-static int do_inkadiag(cmd_tbl_t *cmdtp, int flag, int argc,
-		       char * const argv[]) {
-	cmd_tbl_t *c;
-
-	c = find_cmd_tbl(argv[1], &cmd_inkadiag_sub[0], ARRAY_SIZE(cmd_inkadiag_sub));
-
-	if (c) {
-		argc--;
-		argv++;
-		return c->cmd(c, flag, argc, argv);
-	} else {
-		/* Unrecognized command */
-		return cmd_usage(cmdtp);
-	}
-}
-
-U_BOOT_CMD(inkadiag, 6, 1, do_inkadiag,
-	   "inkadiag - inka diagnosis\n",
-	   "[inkadiag what ...]\n"
-	   "    - perform a diagnosis on inka hardware\n"
-	   "'inkadiag' performs hardware tests.");
diff --git a/board/inka4x0/k4h511638c.h b/board/inka4x0/k4h511638c.h
deleted file mode 100644
index 054ddafd59..0000000000
--- a/board/inka4x0/k4h511638c.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2007 Semihalf
- * Written by Marian Balakowicz <m8@semihalf.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	1		/* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x714F0F00
-#define SDRAM_CONFIG1	0x73722930
-#define SDRAM_CONFIG2	0x46770000
-#define SDRAM_TAPDELAY	0x10000000
diff --git a/board/inka4x0/mt46v16m16-75.h b/board/inka4x0/mt46v16m16-75.h
deleted file mode 100644
index 23fc6f06be..0000000000
--- a/board/inka4x0/mt46v16m16-75.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	1		/* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x714F0F00
-#define SDRAM_CONFIG1	0x73722930
-#define SDRAM_CONFIG2	0x47770000
-#define SDRAM_TAPDELAY	0x10000000
diff --git a/board/inka4x0/mt46v32m16-75.h b/board/inka4x0/mt46v32m16-75.h
deleted file mode 100644
index f16f450d01..0000000000
--- a/board/inka4x0/mt46v32m16-75.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2007 Semihalf
- * Written by Marian Balakowicz <m8@semihalf.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	1		/* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x714F0F00
-#define SDRAM_CONFIG1	0x73711930
-#define SDRAM_CONFIG2	0x46770000
-#define SDRAM_TAPDELAY	0x10000000
diff --git a/board/inka4x0/mt48lc16m16a2-75.h b/board/inka4x0/mt48lc16m16a2-75.h
deleted file mode 100644
index 0133eaa2ca..0000000000
--- a/board/inka4x0/mt48lc16m16a2-75.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	0		/* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x00CD0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xD2322800
-#define SDRAM_CONFIG2	0x8AD70000
diff --git a/board/intercontrol/digsy_mtc/Kconfig b/board/intercontrol/digsy_mtc/Kconfig
deleted file mode 100644
index 1cf2275d81..0000000000
--- a/board/intercontrol/digsy_mtc/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DIGSY_MTC
-
-config SYS_BOARD
-	default "digsy_mtc"
-
-config SYS_VENDOR
-	default "intercontrol"
-
-config SYS_CONFIG_NAME
-	default "digsy_mtc"
-
-endif
diff --git a/board/intercontrol/digsy_mtc/MAINTAINERS b/board/intercontrol/digsy_mtc/MAINTAINERS
deleted file mode 100644
index c83ebcdab9..0000000000
--- a/board/intercontrol/digsy_mtc/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-DIGSY_MTC BOARD
-M:	Werner Pfister <Pfister_Werner@intercontrol.de>
-S:	Maintained
-F:	board/intercontrol/digsy_mtc/
-F:	include/configs/digsy_mtc.h
-F:	configs/digsy_mtc_defconfig
-F:	configs/digsy_mtc_RAMBOOT_defconfig
-F:	configs/digsy_mtc_rev5_defconfig
-F:	configs/digsy_mtc_rev5_RAMBOOT_defconfig
diff --git a/board/intercontrol/digsy_mtc/Makefile b/board/intercontrol/digsy_mtc/Makefile
deleted file mode 100644
index 4d13eadf5b..0000000000
--- a/board/intercontrol/digsy_mtc/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Author: Grzegorz Bernacki, Semihalf, gjb@semihalf.com
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= digsy_mtc.o
-obj-$(CONFIG_VIDEO) += cmd_disp.o
diff --git a/board/intercontrol/digsy_mtc/cmd_disp.c b/board/intercontrol/digsy_mtc/cmd_disp.c
deleted file mode 100644
index 2ffa8bfe40..0000000000
--- a/board/intercontrol/digsy_mtc/cmd_disp.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * (C) Copyright 2011 DENX Software Engineering,
- * Anatolij Gustschin <agust@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <mpc5xxx.h>
-#include <asm/io.h>
-
-#define GPIO_USB1_0	0x00010000
-
-static int cmd_disp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
-	if (argc < 2) {
-		printf("%s\n",
-		       in_be32(&gpio->simple_dvo) & GPIO_USB1_0 ? "on" : "off");
-		return 0;
-	}
-
-	if (!strncmp(argv[1], "on", 2)) {
-		setbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
-	} else if (!strncmp(argv[1], "off", 3)) {
-		clrbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
-	} else {
-		cmd_usage(cmdtp);
-		return 1;
-	}
-	return 0;
-}
-
-U_BOOT_CMD(disp, 2, 1, cmd_disp,
-		"disp [on/off] - switch display on/off",
-		"\n    - print display on/off status\n"
-		"on\n    - turn on\n"
-		"off\n    - turn off\n"
-);
diff --git a/board/intercontrol/digsy_mtc/digsy_mtc.c b/board/intercontrol/digsy_mtc/digsy_mtc.c
deleted file mode 100644
index 6c33eeb022..0000000000
--- a/board/intercontrol/digsy_mtc/digsy_mtc.c
+++ /dev/null
@@ -1,477 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2005-2009
- * Modified for InterControl digsyMTC MPC5200 board by
- * Frank Bodammer, GCD Hard- & Software GmbH,
- *                 frank.bodammer@gcd-solutions.de
- *
- * (C) Copyright 2009
- * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include "eeprom.h"
-#if defined(CONFIG_DIGSY_REV5)
-#include "is45s16800a2.h"
-#include <mtd/cfi_flash.h>
-#include <flash.h>
-#else
-#include "is42s16800a-7t.h"
-#endif
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <mb862xx.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern int usb_cpu_init(void);
-
-#if defined(CONFIG_DIGSY_REV5)
-/*
- * The M29W128GH needs a special reset command function,
- * details see the doc/README.cfi file
- */
-void flash_cmd_reset(flash_info_t *info)
-{
-	flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
-}
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start(int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-	long control = SDRAM_CONTROL | hi_addr_bit;
-
-	/* unlock mode register */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
-
-	/* precharge all banks */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
-
-	/* auto refresh */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
-
-	/* set mode register */
-	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
-
-	/* normal operation */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced dram_init does NOT make real use
- *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if
- *            CONFIG_SYS_SDRAM_BASE is something other than 0x00000000.
- */
-
-int dram_init(void)
-{
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-	uint svr, pvr;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001C); /* 512MB at 0x0 */
-	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
-
-	/* setup config registers */
-	out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
-	out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
-			(0x13 + __builtin_ffs(dramsize >> 20) - 1));
-	} else {
-		out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
-	}
-
-	/* let SDRAM CS1 start right after CS0 */
-	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C);
-
-	/* find RAM size using SDRAM CS1 only */
-	test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
-			0x08000000);
-		dramsize2 = test1;
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize2 < (1 << 20))
-		dramsize2 = 0;
-
-	/* set SDRAM CS1 size according to the amount of RAM found */
-	if (dramsize2 > 0) {
-		out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize |
-			(0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
-	} else {
-		out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
-	if (dramsize >= 0x13)
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	else
-		dramsize = 0;
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
-	if (dramsize2 >= 0x13)
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	else
-		dramsize2 = 0;
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	svr = get_svr();
-	pvr = get_pvr();
-	if ((SVR_MJREV(svr) >= 2) &&
-	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
-		out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
-
-	gd->ram_size = dramsize + dramsize2;
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	puts ("Board: InterControl digsyMTC");
-#if defined(CONFIG_DIGSY_REV5)
-	puts (" rev5");
-#endif
-	if (i > 0) {
-		puts(", ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return 0;
-}
-
-#if defined(CONFIG_VIDEO)
-
-#define GPIO_USB1_0		0x00010000	/* Power-On pin */
-#define GPIO_USB1_9		0x08		/* PX_~EN pin */
-
-#define GPIO_EE_DO		0x10		/* PSC6_0 (DO) pin */
-#define GPIO_EE_CTS		0x20		/* PSC6_1 (CTS) pin */
-#define GPIO_EE_DI		0x10000000	/* PSC6_2 (DI) pin */
-#define GPIO_EE_CLK		0x20000000	/* PSC6_3 (CLK) pin */
-
-#define GPT_GPIO_ON		0x00000034	/* GPT as simple GPIO, high */
-
-static void exbo_hw_init(void)
-{
-	struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-	struct mpc5xxx_wu_gpio *wu_gpio =
-				(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
-
-	/* configure IrDA pins (PSC6 port) as gpios */
-	gpio->port_config &= 0xFF8FFFFF;
-
-	/* Init for USB1_0, EE_CLK and EE_DI - Low */
-	setbits_be32(&gpio->simple_ddr,
-			GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
-	clrbits_be32(&gpio->simple_ode,
-			GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
-	clrbits_be32(&gpio->simple_dvo,
-			GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
-	setbits_be32(&gpio->simple_gpioe,
-			GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
-
-	/* Init for EE_DO, EE_CTS - Input */
-	clrbits_8(&wu_gpio->ddr, GPIO_EE_DO | GPIO_EE_CTS);
-	setbits_8(&wu_gpio->enable, GPIO_EE_DO | GPIO_EE_CTS);
-
-	/* Init for PX_~EN (USB1_9) - High */
-	clrbits_8(&gpio->sint_ode, GPIO_USB1_9);
-	setbits_8(&gpio->sint_ddr, GPIO_USB1_9);
-	clrbits_8(&gpio->sint_inten, GPIO_USB1_9);
-	setbits_8(&gpio->sint_dvo, GPIO_USB1_9);
-	setbits_8(&gpio->sint_gpioe, GPIO_USB1_9);
-
-	/* Init for ~OE Switch (GPIO3) - Timer_0 GPIO High */
-	out_be32(&gpt[0].emsr, GPT_GPIO_ON);
-	/* Init for S Switch (GPIO4) - Timer_1 GPIO High */
-	out_be32(&gpt[1].emsr, GPT_GPIO_ON);
-
-	/* Power-On camera supply */
-	setbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
-}
-#else
-static inline void exbo_hw_init(void) {}
-#endif /* CONFIG_VIDEO */
-
-int board_early_init_r(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write access for detection
-	 * process.  Note that CS_BOOT cannot be cleared when executing in
-	 * flash.
-	 */
-	/* disable CS_BOOT */
-	clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
-	/* enable CS1 */
-	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17));
-	/* enable CS0 */
-	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
-	/* Low level USB init, required for proper kernel operation */
-	usb_cpu_init();
-#endif
-
-	return (0);
-}
-
-void board_get_enetaddr (uchar * enet)
-{
-	ushort read = 0;
-	ushort addr_of_eth_addr = 0;
-	ushort len_sys = 0;
-	ushort len_sys_cfg = 0;
-
-	/* check identification word */
-	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2);
-	if (read != EEPROM_IDENT)
-		return;
-
-	/* calculate offset of config area */
-	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2);
-	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG,
-		(uchar *)&len_sys_cfg, 2);
-	addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1;
-	if (addr_of_eth_addr >= EEPROM_LEN)
-		return;
-
-	eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6);
-}
-
-int misc_init_r(void)
-{
-	pci_dev_t devbusfn;
-	uchar enetaddr[6];
-
-	/* check if graphic extension board is present */
-	devbusfn = pci_find_device(PCI_VENDOR_ID_FUJITSU,
-				   PCI_DEVICE_ID_CORAL_PA, 0);
-	if (devbusfn != -1)
-		exbo_hw_init();
-
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
-		board_get_enetaddr(enetaddr);
-		eth_setenv_enetaddr("ethaddr", enetaddr);
-	}
-
-	return 0;
-}
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#ifdef CONFIG_IDE
-
-#ifdef CONFIG_IDE_RESET
-
-void init_ide_reset(void)
-{
-	debug ("init_ide_reset\n");
-
-	/* set gpio output value to 1 */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
-	/* open drain output */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
-	/* direction output */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
-	/* enable gpio */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
-
-}
-
-void ide_set_reset(int idereset)
-{
-	debug ("ide_reset(%d)\n", idereset);
-
-	/* set gpio output value to 0 */
-	clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
-	/* open drain output */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
-	/* direction output */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
-	/* enable gpio */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
-
-	udelay(10000);
-
-	/* set gpio output value to 1 */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
-	/* open drain output */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
-	/* direction output */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
-	/* enable gpio */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
-}
-#endif /* CONFIG_IDE_RESET */
-#endif /* CONFIG_IDE */
-
-#ifdef CONFIG_OF_BOARD_SETUP
-static void ft_delete_node(void *fdt, const char *compat)
-{
-	int off = -1;
-	int ret;
-
-	off = fdt_node_offset_by_compatible(fdt, -1, compat);
-	if (off < 0) {
-		printf("Could not find %s node.\n", compat);
-		return;
-	}
-
-	ret = fdt_del_node(fdt, off);
-	if (ret < 0)
-		printf("Could not delete %s node.\n", compat);
-}
-#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
-static void ft_adapt_flash_base(void *blob)
-{
-	flash_info_t	*dev = &flash_info[0];
-	int off;
-	struct fdt_property *prop;
-	int len;
-	u32 *reg, *reg2;
-
-	off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
-	if (off < 0) {
-		printf("Could not find fsl,mpc5200b-lpb node.\n");
-		return;
-	}
-
-	/* found compatible property */
-	prop = fdt_get_property_w(blob, off, "ranges", &len);
-	if (prop) {
-		reg = reg2 = (u32 *)&prop->data[0];
-
-		reg[2] = dev->start[0];
-		reg[3] = dev->size;
-		fdt_setprop(blob, off, "ranges", reg2, len);
-	} else
-		printf("Could not find ranges\n");
-}
-
-extern ulong flash_get_size (phys_addr_t base, int banknum);
-
-/* Update the Flash Baseaddr settings */
-int update_flash_size (int flash_size)
-{
-	volatile struct mpc5xxx_mmap_ctl *mm =
-		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
-	flash_info_t	*dev;
-	int	i;
-	int size = 0;
-	unsigned long base = 0x0;
-	u32 *cs_reg = (u32 *)&mm->cs0_start;
-
-	for (i = 0; i < 2; i++) {
-		dev = &flash_info[i];
-
-		if (dev->size) {
-			/* calculate new base addr for this chipselect */
-			base -= dev->size;
-			out_be32(cs_reg, START_REG(base));
-			cs_reg++;
-			out_be32(cs_reg, STOP_REG(base, dev->size));
-			cs_reg++;
-			/* recalculate the sectoraddr in the cfi driver */
-			size += flash_get_size(base, i);
-		}
-	}
-	flash_protect_default();
-	gd->bd->bi_flashstart = base;
-	return 0;
-}
-#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	int phy_addr = CONFIG_PHY_ADDR;
-	char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
-
-	ft_cpu_setup(blob, bd);
-	/*
-	 * There are 2 RTC nodes in the DTS, so remove
-	 * the unneeded node here.
-	 */
-#if defined(CONFIG_DIGSY_REV5)
-	ft_delete_node(blob, "dallas,ds1339");
-#else
-	ft_delete_node(blob, "mc,rv3029c2");
-#endif
-#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
-#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
-	/* Update reg property in all nor flash nodes too */
-	fdt_fixup_nor_flash_size(blob);
-#endif
-	ft_adapt_flash_base(blob);
-#endif
-	/* fix up the phy address */
-	do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/intercontrol/digsy_mtc/eeprom.h b/board/intercontrol/digsy_mtc/eeprom.h
deleted file mode 100644
index 17bd034072..0000000000
--- a/board/intercontrol/digsy_mtc/eeprom.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * (C) Copyright 2009 Semihalf.
- * Written by: Grzegorz Bernacki <gjb@semihalf.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef CMD_EEPROM_H
-#define CMD_EEPROM_H
-
-#define EEPROM_ADDR		CONFIG_SYS_I2C_EEPROM_ADDR
-#define EEPROM_LEN		1024	/* eeprom length */
-#define EEPROM_IDENT		2408	/* identification word */
-#define EEPROM_ADDR_IDENT	0	/* identification word offset */
-#define EEPROM_ADDR_LEN_SYS	2	/* system area lenght offset */
-#define EEPROM_ADDR_LEN_SYSCFG	4	/* system config area length offset */
-#define EEPROM_ADDR_ETHADDR	23	/* ethernet address offset */
-
-#endif
diff --git a/board/intercontrol/digsy_mtc/is42s16800a-7t.h b/board/intercontrol/digsy_mtc/is42s16800a-7t.h
deleted file mode 100644
index c555d2d623..0000000000
--- a/board/intercontrol/digsy_mtc/is42s16800a-7t.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * (C) Copyright 2004-2009
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_MODE	0x00CD0000
-#define SDRAM_CONTROL	0x505F0000
-#define SDRAM_CONFIG1	0xD2322900
-#define SDRAM_CONFIG2	0x8AD70000
diff --git a/board/intercontrol/digsy_mtc/is45s16800a2.h b/board/intercontrol/digsy_mtc/is45s16800a2.h
deleted file mode 100644
index c42ba38e34..0000000000
--- a/board/intercontrol/digsy_mtc/is45s16800a2.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2010
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * based on:
- * (C) Copyright 2004-2009
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_MODE	0x00CD0000
-#define SDRAM_CONTROL	0x50470000
-#define SDRAM_CONFIG1	0xD2322900
-#define SDRAM_CONFIG2	0x8AD70000
diff --git a/board/ipek01/Kconfig b/board/ipek01/Kconfig
deleted file mode 100644
index 34e094d79d..0000000000
--- a/board/ipek01/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_IPEK01
-
-config SYS_BOARD
-	default "ipek01"
-
-config SYS_CONFIG_NAME
-	default "ipek01"
-
-endif
diff --git a/board/ipek01/MAINTAINERS b/board/ipek01/MAINTAINERS
deleted file mode 100644
index 906d39ef80..0000000000
--- a/board/ipek01/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-IPEK01 BOARD
-M:	Anatolij Gustschin <agust@denx.de>
-S:	Maintained
-F:	board/ipek01/
-F:	include/configs/ipek01.h
-F:	configs/ipek01_defconfig
diff --git a/board/ipek01/Makefile b/board/ipek01/Makefile
deleted file mode 100644
index a786ab2118..0000000000
--- a/board/ipek01/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= ipek01.o
diff --git a/board/ipek01/ipek01.c b/board/ipek01/ipek01.c
deleted file mode 100644
index 133db8c6bd..0000000000
--- a/board/ipek01/ipek01.c
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2006
- * MicroSys GmbH
- *
- * (C) Copyright 2009
- * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <netdev.h>
-#include <miiphy.h>
-#include <libfdt.h>
-#include <mb862xx.h>
-#include <video_fb.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_OF_LIBFDT
-#include <fdt_support.h>
-#endif /* CONFIG_OF_LIBFDT */
-
-/* mt46v16m16-75 */
-#ifdef CONFIG_MPC5200_DDR
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x714f0f00
-#define SDRAM_CONFIG1	0x73722930
-#define SDRAM_CONFIG2	0x47770000
-#define SDRAM_TAPDELAY	0x10000000
-#else
-#error SDRAM is not supported on this board
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void sdram_start (int hi_addr)
-{
-	struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);
-
-	/* precharge all banks */
-	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
-
-	/* set mode register: extended mode */
-	out_be32 (&sdram->mode, SDRAM_EMODE);
-
-	/* set mode register: reset DLL */
-	out_be32 (&sdram->mode, SDRAM_MODE | 0x04000000);
-
-	/* precharge all banks */
-	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
-
-	/* auto refresh */
-	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);
-
-	/* set mode register */
-	out_be32 (&sdram->mode, SDRAM_MODE);
-
-	/* normal operation */
-	out_be32 (&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
-}
-
-/*
- * ATTENTION: Although partially referenced dram_init does NOT make real
- *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if
- *	      CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
- */
-
-int dram_init(void)
-{
-	struct mpc5xxx_mmap_ctl *mmap_ctl =
-		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
-	struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-	struct mpc5xxx_cdm *cdm = (struct mpc5xxx_cdm *)MPC5XXX_CDM;
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	out_be32 (&mmap_ctl->sdram0, 0x0000001e);	/* 2G at 0x0 */
-	out_be32 (&mmap_ctl->sdram1, 0x00000000);	/* disabled */
-
-	/* setup config registers */
-	out_be32 (&sdram->config1, SDRAM_CONFIG1);
-	out_be32 (&sdram->config2, SDRAM_CONFIG2);
-
-	/* set tap delay */
-	out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start (0);
-	test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start (1);
-	test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start (0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0)
-		out_be32 (&mmap_ctl->sdram0,
-			  0x13 + __builtin_ffs (dramsize >> 20) - 1);
-	else
-		out_be32 (&mmap_ctl->sdram1, 0);	/* disabled */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	out_be32 (&sdram->sdelay, 0x04);
-
-	gd->ram_size = dramsize + dramsize2;
-
-	return 0;
-}
-
-int checkboard (void)
-{
-	puts ("Board: IPEK01 \n");
-	return 0;
-}
-
-void flash_preinit (void)
-{
-	struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
-
-	/*
-	 * Now, when we are in RAM, enable flash write
-	 * access for detection process.
-	 * Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
-	 */
-	clrbits_be32 (&lpb->cs0_cfg, 0x1);	/* clear RO */
-}
-
-void flash_afterinit (ulong start, ulong size)
-{
-	struct mpc5xxx_mmap_ctl *mmap_ctl =
-		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
-
-#if defined(CONFIG_BOOT_ROM)
-	/* adjust mapping */
-	out_be32 (&mmap_ctl->cs1_start, START_REG (start));
-	out_be32 (&mmap_ctl->cs1_stop, STOP_REG (start, size));
-#else
-	/* adjust mapping */
-	out_be32 (&mmap_ctl->boot_start, START_REG (start));
-	out_be32 (&mmap_ctl->cs0_start, START_REG (start));
-	out_be32 (&mmap_ctl->boot_stop, STOP_REG (start, size));
-	out_be32 (&mmap_ctl->cs0_stop, STOP_REG (start, size));
-#endif
-}
-
-extern flash_info_t flash_info[];	/* info for FLASH chips */
-
-int misc_init_r (void)
-{
-	/* adjust flash start */
-	gd->bd->bi_flashstart = flash_info[0].start[0];
-	return (0);
-}
-
-#ifdef	CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init (struct pci_controller *);
-
-void pci_init_board (void)
-{
-	pci_mpc5xxx_init (&hose);
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup (blob, bd);
-	fdt_fixup_memory (blob, (u64) bd->bi_memstart, (u64) bd->bi_memsize);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-int board_eth_init(bd_t *bis)
-{
-	cpu_eth_init(bis); /* Built in FEC comes first */
-	return pci_eth_init(bis);
-}
-
-#ifdef CONFIG_VIDEO
-extern GraphicDevice mb862xx;
-
-static const gdc_regs init_regs[] = {
-	{0x0100, 0x00000900},
-	{0x0020, 0x80190257},
-	{0x0024, 0x00000000},
-	{0x0028, 0x00000000},
-	{0x002c, 0x00000000},
-	{0x0110, 0x00000000},
-	{0x0114, 0x00000000},
-	{0x0118, 0x02570320},
-	{0x0004, 0x041f0000},
-	{0x0008, 0x031f031f},
-	{0x000c, 0x067f0347},
-	{0x0010, 0x02780000},
-	{0x0014, 0x0257025c},
-	{0x0018, 0x00000000},
-	{0x001c, 0x02570320},
-	{0x0100, 0x80010900},
-	{0x0, 0x0}
-};
-
-const gdc_regs *board_get_regs (void)
-{
-	return init_regs;
-}
-
-/* Returns Lime base address */
-unsigned int board_video_init (void)
-{
-	if (mb862xx_probe (CONFIG_SYS_LIME_BASE) != MB862XX_TYPE_LIME)
-		return 0;
-
-	mb862xx.winSizeX = 800;
-	mb862xx.winSizeY = 600;
-	mb862xx.gdfIndex = GDF_15BIT_555RGB;
-	mb862xx.gdfBytesPP = 2;
-
-	return CONFIG_SYS_LIME_BASE;
-}
-
-#if defined(CONFIG_CONSOLE_EXTRA_INFO)
-/*
- * Return text to be printed besides the logo.
- */
-void video_get_info_str (int line_number, char *info)
-{
-	if (line_number == 1)
-		strcpy (info, " Board: IPEK01");
-	else
-		info[0] = '\0';
-}
-#endif
-#endif /* CONFIG_VIDEO */
diff --git a/board/jupiter/Kconfig b/board/jupiter/Kconfig
deleted file mode 100644
index d71acbbc4d..0000000000
--- a/board/jupiter/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_JUPITER
-
-config SYS_BOARD
-	default "jupiter"
-
-config SYS_CONFIG_NAME
-	default "jupiter"
-
-endif
diff --git a/board/jupiter/MAINTAINERS b/board/jupiter/MAINTAINERS
deleted file mode 100644
index 5a79a616cc..0000000000
--- a/board/jupiter/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-JUPITER BOARD
-M:	Heiko Schocher <hs@denx.de>
-S:	Maintained
-F:	board/jupiter/
-F:	include/configs/jupiter.h
-F:	configs/jupiter_defconfig
diff --git a/board/jupiter/Makefile b/board/jupiter/Makefile
deleted file mode 100644
index 4d3ef9ed7a..0000000000
--- a/board/jupiter/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= jupiter.o
diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c
deleted file mode 100644
index 52d2766e9a..0000000000
--- a/board/jupiter/jupiter.c
+++ /dev/null
@@ -1,296 +0,0 @@
-/*
- * (C) Copyright 2007
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <libfdt.h>
-
-#define SDRAM_DDR	0
-#if 1
-/* Settings Icecube */
-#define SDRAM_MODE	0x00CD0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xD2322800
-#define SDRAM_CONFIG2	0x8AD70000
-#else
-/*Settings Jupiter UB 1.0.0 */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_CONTROL	0xD04F0000
-#define SDRAM_CONFIG1	0xf7277f00
-#define SDRAM_CONFIG2	0x88b70004
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set mode register: extended mode */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
-	__asm__ volatile ("sync");
-
-	/* set mode register: reset DLL */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
-	__asm__ volatile ("sync");
-#endif
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* set mode register */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-	__asm__ volatile ("sync");
-
-	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-	__asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced dram_init does NOT make real use
- *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- *            is something else than 0x00000000.
- */
-
-int dram_init(void)
-{
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-	uint svr, pvr;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set tap delay */
-	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
-	__asm__ volatile ("sync");
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20)) {
-		dramsize = 0;
-	}
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-	}
-
-	/* let SDRAM CS1 start right after CS0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
-
-	/* find RAM size using SDRAM CS1 only */
-	if (!dramsize)
-		sdram_start(0);
-	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	if (!dramsize) {
-		sdram_start(1);
-		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	}
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize2 = test1;
-	} else {
-		dramsize2 = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize2 < (1 << 20)) {
-		dramsize2 = 0;
-	}
-
-	/* set SDRAM CS1 size according to the amount of RAM found */
-	if (dramsize2 > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
-			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
-	if (dramsize >= 0x13) {
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	} else {
-		dramsize = 0;
-	}
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
-	if (dramsize2 >= 0x13) {
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	} else {
-		dramsize2 = 0;
-	}
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	svr = get_svr();
-	pvr = get_pvr();
-	if ((SVR_MJREV(svr) >= 2) &&
-	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
-
-		*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
-		__asm__ volatile ("sync");
-	}
-
-	gd->ram_size = dramsize + dramsize2;
-
-	return 0;
-}
-
-int checkboard (void)
-{
-	puts ("Board: Sauter (Jupiter)\n");
-	return 0;
-}
-
-void flash_preinit(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write
-	 * access for detection process.
-	 * Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
-	 */
-	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-}
-
-int board_early_init_r (void)
-{
-	flash_preinit ();
-	return 0;
-}
-
-void flash_afterinit(ulong size)
-{
-	if (size == 0x1000000) { /* adjust mapping */
-		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
-			START_REG(CONFIG_SYS_BOOTCS_START | size);
-		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
-			STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
-	}
-	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
-}
-
-int update_flash_size (int flash_size)
-{
-	flash_afterinit (flash_size);
-	return 0;
-}
-
-int board_early_init_f (void)
-{
-	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-	return 0;
-}
-
-#ifdef	CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET)
-
-void init_ide_reset (void)
-{
-	debug ("init_ide_reset\n");
-
-	/* Configure PSC1_4 as GPIO output for ATA reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
-	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
-	/* Deassert reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O   |= GPIO_PSC1_4;
-}
-
-void ide_set_reset (int idereset)
-{
-	debug ("ide_reset(%d)\n", idereset);
-
-	if (idereset) {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
-		/* Make a delay. MPC5200 spec says 25 usec min */
-		udelay(500000);
-	} else {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
-	}
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/motionpro/Kconfig b/board/motionpro/Kconfig
deleted file mode 100644
index f624f6c95f..0000000000
--- a/board/motionpro/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_MOTIONPRO
-
-config SYS_BOARD
-	default "motionpro"
-
-config SYS_CONFIG_NAME
-	default "motionpro"
-
-endif
diff --git a/board/motionpro/MAINTAINERS b/board/motionpro/MAINTAINERS
deleted file mode 100644
index 2f8b5cb580..0000000000
--- a/board/motionpro/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MOTIONPRO BOARD
-#M:	-
-S:	Maintained
-F:	board/motionpro/
-F:	include/configs/motionpro.h
-F:	configs/motionpro_defconfig
diff --git a/board/motionpro/Makefile b/board/motionpro/Makefile
deleted file mode 100644
index 898a384c39..0000000000
--- a/board/motionpro/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= motionpro.o
diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c
deleted file mode 100644
index 7883a179e8..0000000000
--- a/board/motionpro/motionpro.c
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * (C) Copyright 2003-2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * modified for Promess PRO - by Andy Joseph, andy@promessdev.com
- * modified for Promess PRO-Motion - by Robert McCullough, rob@promessdev.com
- * modified by Chris M. Tumas 6/20/06 Change CAS latency to 2 from 3
- * Also changed the refresh for 100MHz operation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <miiphy.h>
-#include <libfdt.h>
-
-#if defined(CONFIG_LED_STATUS)
-#include <status_led.h>
-#endif /* CONFIG_LED_STATUS */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Kollmorgen DPR initialization data */
-struct init_elem {
-	unsigned long addr;
-	unsigned len;
-	char *data;
-	} init_seq[] = {
-		{0x500003F2, 2, "\x86\x00"},		/* HW parameter */
-		{0x500003F0, 2, "\x00\x00"},
-		{0x500003EC, 4, "\x00\x80\xc1\x52"},	/* Magic word */
-	};
-
-/*
- * Initialize Kollmorgen DPR
- */
-static void kollmorgen_init(void)
-{
-	unsigned i, j;
-	vu_char *p;
-
-	for (i = 0; i < sizeof(init_seq) / sizeof(struct init_elem); ++i) {
-		p = (vu_char *)init_seq[i].addr;
-		for (j = 0; j < init_seq[i].len; ++j)
-			*(p + j) = *(init_seq[i].data + j);
-	}
-
-	printf("DPR:   Kollmorgen DPR initialized\n");
-}
-
-
-/*
- * Early board initalization.
- */
-int board_early_init_r(void)
-{
-	/* Now, when we are in RAM, disable Boot Chipselect and enable CS0 */
-	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25);
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16);
-
-	/* Initialize Kollmorgen DPR */
-	kollmorgen_init();
-
-	return 0;
-}
-
-
-/*
- * Additional PHY intialization. After being reset in mpc5xxx_fec_init_phy(),
- * PHY goes into FX mode.  To take it out of the FX mode and switch into
- * desired TX operation, one needs to clear the FX_SEL bit of Mode Control
- * Register.
- */
-void reset_phy(void)
-{
-	unsigned short mode_control;
-
-	miiphy_read("FEC", CONFIG_PHY_ADDR, 0x15, &mode_control);
-	miiphy_write("FEC", CONFIG_PHY_ADDR, 0x15,
-			mode_control & 0xfffe);
-	return;
-}
-
-#ifndef CONFIG_SYS_RAMBOOT
-/*
- * Helper function to initialize SDRAM controller.
- */
-static void sdram_start(int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
-						hi_addr_bit;
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
-						hi_addr_bit;
-
-	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
-						hi_addr_bit;
-
-	/* auto refresh, second time */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
-						hi_addr_bit;
-
-	/* set mode register */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-
-	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-}
-#endif /* !CONFIG_SYS_RAMBOOT */
-
-
-/*
- * Initalize SDRAM - configure SDRAM controller, detect memory size.
- */
-int dram_init(void)
-{
-	ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* According to AN3221 (MPC5200B SDRAM Initialization and
-	 * Configuration), the SDelay register must be written a value of
-	 * 0x00000004 as the first step of the SDRAM contorller configuration.
-	 */
-	*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
-
-	/* configure SDRAM start/end for detection */
-	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
-			__builtin_ffs(dramsize >> 20) - 1;
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-	}
-
-	/* let SDRAM CS1 start right after CS0 and disable it */
-	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;
-
-#else /* !CONFIG_SYS_RAMBOOT */
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
-	if (dramsize >= 0x13)
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	else
-		dramsize = 0;
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/* return total ram size */
-	gd->ram_size = dramsize;
-
-	return 0;
-}
-
-
-int checkboard(void)
-{
-	uchar rev = *(vu_char *)CPLD_REV_REGISTER;
-	printf("Board: Promess Motion-PRO board (CPLD rev. 0x%02x)\n", rev);
-	return 0;
-}
-
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-
-#if defined(CONFIG_LED_STATUS)
-vu_long *regcode_to_regaddr(led_id_t regcode)
-{
-	/* GPT Enable and Mode Select Register address */
-	vu_long *reg_translate[] = {
-					(vu_long *)MPC5XXX_GPT6_ENABLE,
-					(vu_long *)MPC5XXX_GPT7_ENABLE,
-				   };
-
-	if (ARRAY_SIZE(reg_translate) <= regcode)
-		return NULL;
-	return reg_translate[regcode];
-}
-
-void __led_init(led_id_t regcode, int state)
-{
-	vu_long *regaddr = regcode_to_regaddr(regcode);
-
-	*regaddr |= ENABLE_GPIO_OUT;
-
-	if (state == CONFIG_LED_STATUS_ON)
-		*((vu_long *) regaddr) |= LED_ON;
-	else
-		*((vu_long *) regaddr) &= ~LED_ON;
-}
-
-void __led_set(led_id_t regcode, int state)
-{
-	vu_long *regaddr = regcode_to_regaddr(regcode);
-
-	if (state == CONFIG_LED_STATUS_ON)
-		*regaddr |= LED_ON;
-	else
-		*regaddr &= ~LED_ON;
-}
-
-void __led_toggle(led_id_t regcode)
-{
-	vu_long *regaddr = regcode_to_regaddr(regcode);
-
-	*regaddr ^= LED_ON;
-}
-#endif /* CONFIG_LED_STATUS */
diff --git a/board/munices/Kconfig b/board/munices/Kconfig
deleted file mode 100644
index 019aaae3e9..0000000000
--- a/board/munices/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_MUNICES
-
-config SYS_BOARD
-	default "munices"
-
-config SYS_CONFIG_NAME
-	default "munices"
-
-endif
diff --git a/board/munices/MAINTAINERS b/board/munices/MAINTAINERS
deleted file mode 100644
index 50d3e7ebda..0000000000
--- a/board/munices/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MUNICES BOARD
-#M:	-
-S:	Maintained
-F:	board/munices/
-F:	include/configs/munices.h
-F:	configs/munices_defconfig
diff --git a/board/munices/Makefile b/board/munices/Makefile
deleted file mode 100644
index d16e2a1fa2..0000000000
--- a/board/munices/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= munices.o
diff --git a/board/munices/mt48lc16m16a2-75.h b/board/munices/mt48lc16m16a2-75.h
deleted file mode 100644
index 0133eaa2ca..0000000000
--- a/board/munices/mt48lc16m16a2-75.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	0		/* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x00CD0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xD2322800
-#define SDRAM_CONFIG2	0x8AD70000
diff --git a/board/munices/munices.c b/board/munices/munices.c
deleted file mode 100644
index 468eb3723e..0000000000
--- a/board/munices/munices.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * (C) Copyright 2007
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-
-#include "mt48lc16m16a2-75.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set mode register: extended mode */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
-	__asm__ volatile ("sync");
-
-	/* set mode register: reset DLL */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
-	__asm__ volatile ("sync");
-#endif
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* set mode register */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-	__asm__ volatile ("sync");
-
-	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-	__asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced dram_init does NOT make real use
- *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- *            is something else than 0x00000000.
- */
-
-int dram_init(void)
-{
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001b;/* 256MB at 0x0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x10000000;/* disabled */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR && SDRAM_TAPDELAY
-	/* set tap delay */
-	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
-	__asm__ volatile ("sync");
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000);
-	sdram_start(1);
-	test2 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20)) {
-		dramsize = 0;
-	}
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
-	if (dramsize >= 0x13) {
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	} else {
-		dramsize = 0;
-	}
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
-	if (dramsize2 >= 0x13) {
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	} else {
-		dramsize2 = 0;
-	}
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	gd->ram_size = dramsize + dramsize2;
-
-	return 0;
-}
-
-int checkboard (void)
-{
-	puts ("Board: MUNICes\n");
-	return 0;
-}
-
-#ifdef	CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/pdm360ng/Kconfig b/board/pdm360ng/Kconfig
deleted file mode 100644
index 33173a0a2a..0000000000
--- a/board/pdm360ng/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_PDM360NG
-
-config SYS_BOARD
-	default "pdm360ng"
-
-config SYS_CONFIG_NAME
-	default "pdm360ng"
-
-endif
diff --git a/board/pdm360ng/MAINTAINERS b/board/pdm360ng/MAINTAINERS
deleted file mode 100644
index 5c99f59e8f..0000000000
--- a/board/pdm360ng/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PDM360NG BOARD
-M:	Michael Weiss <michael.weiss@ifm.com>
-S:	Maintained
-F:	board/pdm360ng/
-F:	include/configs/pdm360ng.h
-F:	configs/pdm360ng_defconfig
diff --git a/board/pdm360ng/Makefile b/board/pdm360ng/Makefile
deleted file mode 100644
index 99201a41f6..0000000000
--- a/board/pdm360ng/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= pdm360ng.o
diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c
deleted file mode 100644
index 371bcd9e6b..0000000000
--- a/board/pdm360ng/pdm360ng.c
+++ /dev/null
@@ -1,581 +0,0 @@
-/*
- * (C) Copyright 2009, 2010 Wolfgang Denk <wd@denx.de>
- *
- * (C) Copyright 2009-2010
- * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/bitops.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/mpc512x.h>
-#include <fdt_support.h>
-#include <flash.h>
-#ifdef CONFIG_MISC_INIT_R
-#include <i2c.h>
-#endif
-#include <serial.h>
-#include <jffs2/load_kernel.h>
-#include <mtd_node.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[];
-ulong flash_get_size (phys_addr_t base, int banknum);
-
-sdram_conf_t mddrc_config[] = {
-	{
-		(512 << 20),	/* 512 MB RAM configuration */
-		{
-			CONFIG_SYS_MDDRC_SYS_CFG,
-			CONFIG_SYS_MDDRC_TIME_CFG0,
-			CONFIG_SYS_MDDRC_TIME_CFG1,
-			CONFIG_SYS_MDDRC_TIME_CFG2
-		}
-	},
-	{
-		(128 << 20),	/* 128 MB RAM configuration */
-		{
-			CONFIG_SYS_MDDRC_SYS_CFG_ALT1,
-			CONFIG_SYS_MDDRC_TIME_CFG0_ALT1,
-			CONFIG_SYS_MDDRC_TIME_CFG1_ALT1,
-			CONFIG_SYS_MDDRC_TIME_CFG2_ALT1
-		}
-	},
-};
-
-int dram_init(void)
-{
-	int i;
-	u32 msize = 0;
-	u32 pdm360ng_init_seq[] = {
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_PCHG_ALL,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_MICRON_INIT_DEV_OP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_EM2,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_PCHG_ALL,
-		CONFIG_SYS_DDRCMD_EM2,
-		CONFIG_SYS_DDRCMD_EM3,
-		CONFIG_SYS_DDRCMD_EN_DLL,
-		CONFIG_SYS_DDRCMD_RES_DLL,
-		CONFIG_SYS_DDRCMD_PCHG_ALL,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_MICRON_INIT_DEV_OP,
-		CONFIG_SYS_DDRCMD_OCD_DEFAULT,
-		CONFIG_SYS_DDRCMD_OCD_EXIT,
-		CONFIG_SYS_DDRCMD_PCHG_ALL,
-		CONFIG_SYS_DDRCMD_NOP
-	};
-
-	for (i = 0; i < ARRAY_SIZE(mddrc_config); i++) {
-		msize = fixed_sdram(&mddrc_config[i].cfg, pdm360ng_init_seq,
-				    ARRAY_SIZE(pdm360ng_init_seq));
-		if (msize == mddrc_config[i].size)
-			break;
-	}
-
-	gd->ram_size = msize;
-
-	return 0;
-}
-
-static int set_lcd_brightness(char *);
-
-int misc_init_r(void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
-	/*
-	 * Re-configure flash setup using auto-detected info
-	 */
-	if (flash_info[1].size > 0) {
-		out_be32(&im->sysconf.lpcs1aw,
-			CSAW_START(gd->bd->bi_flashstart + flash_info[1].size) |
-			CSAW_STOP(gd->bd->bi_flashstart + flash_info[1].size,
-				  flash_info[1].size));
-		sync_law(&im->sysconf.lpcs1aw);
-		/*
-		 * Re-check to get correct base address
-		 */
-		flash_get_size (gd->bd->bi_flashstart + flash_info[1].size, 1);
-	} else {
-		/* Disable Bank 1 */
-		out_be32(&im->sysconf.lpcs1aw, 0x01000100);
-		sync_law(&im->sysconf.lpcs1aw);
-	}
-
-	out_be32(&im->sysconf.lpcs0aw,
-		CSAW_START(gd->bd->bi_flashstart) |
-		CSAW_STOP(gd->bd->bi_flashstart, flash_info[0].size));
-	sync_law(&im->sysconf.lpcs0aw);
-
-	/*
-	 * Re-check to get correct base address
-	 */
-	flash_get_size (gd->bd->bi_flashstart, 0);
-
-	/*
-	 * Re-do flash protection upon new addresses
-	 */
-	flash_protect (FLAG_PROTECT_CLEAR,
-		       gd->bd->bi_flashstart, 0xffffffff,
-		       &flash_info[0]);
-
-	/* Monitor protection ON by default */
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_SYS_MONITOR_BASE,
-		       CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
-		       &flash_info[0]);
-
-	/* Environment protection ON by default */
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_ENV_ADDR,
-		       CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-		       &flash_info[0]);
-
-#ifdef CONFIG_ENV_ADDR_REDUND
-	/* Redundant environment protection ON by default */
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_ENV_ADDR_REDUND,
-		       CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
-		       &flash_info[0]);
-#endif
-
-#ifdef CONFIG_FSL_DIU_FB
-	set_lcd_brightness(0);
-	/* Switch LCD-Backlight and LVDS-Interface on */
-	setbits_be32(&im->gpio.gpdir, 0x01040000);
-	clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000);
-#endif
-
-	return 0;
-}
-
-static  iopin_t ioregs_init[] = {
-	/* FUNC1=LPC_CS4 */
-	{
-		offsetof(struct ioctrl512x, io_control_pata_ce1), 1, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
-		IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=GPIO10 */
-	{
-		offsetof(struct ioctrl512x, io_control_pata_ce2), 1, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC1=CAN3_TX */
-	{
-		offsetof(struct ioctrl512x, io_control_pata_isolate), 1, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC3=GPIO14 */
-	{
-		offsetof(struct ioctrl512x, io_control_pata_iochrdy), 1, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC2=DIU_LD22 Sets Next 2 to DIU_LD pads */
-	/* DIU_LD22-DIU_LD23 */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_ad31), 2, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
-	},
-	/* FUNC2=USB1_DATA7 Sets Next 12 to USB1 pads */
-	/* USB1_DATA7-USB1_DATA0, USB1_STOP, USB1_NEXT, USB1_CLK, USB1_DIR */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_ad29), 12, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
-	},
-	/* FUNC1=VIU_DATA0 Sets Next 3 to VIU_DATA pads */
-	/* VIU_DATA0-VIU_DATA2 */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_ad17), 3, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
-	},
-	/* FUNC2=FEC_TXD_0 */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_ad14), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
-	},
-	/* FUNC1=VIU_DATA3 Sets Next 2 to VIU_DATA pads */
-	/* VIU_DATA3, VIU_DATA4 */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_ad13), 2, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
-	},
-	/* FUNC2=FEC_RXD_1 Sets Next 12 to FEC pads */
-	/* FEC_RXD_1, FEC_RXD_0, FEC_RX_CLK, FEC_TX_CLK, FEC_RX_ER, FEC_RX_DV */
-	/* FEC_TX_EN, FEC_TX_ER, FEC_CRS, FEC_MDC, FEC_MDIO, FEC_COL */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_ad11), 12, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
-	},
-	/* FUNC2=DIU_LD03 Sets Next 25 to DIU pads */
-	/* DIU_LD00-DIU_LD21 */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_cbe0), 22, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
-	},
-	/* FUNC2=DIU_CLK Sets Next 3 to DIU pads */
-	/* DIU_CLK, DIU_VSYNC, DIU_HSYNC */
-	{
-		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC2=CAN3_RX */
-	{
-		offsetof(struct ioctrl512x, io_control_irq1), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* Sets lowest slew on 2 CAN_TX Pins*/
-	{
-		offsetof(struct ioctrl512x, io_control_can1_tx), 2, 0,
-		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC3=CAN4_TX Sets Next 2 to CAN4 pads */
-	/* CAN4_TX, CAN4_RX */
-	{
-		offsetof(struct ioctrl512x, io_control_j1850_tx), 2, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC3=GPIO8 Sets Next 2 to GPIO pads */
-	/* GPIO8, GPIO9 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc0_0), 2, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC1=FEC_TXD_1 Sets Next 3 to FEC pads */
-	/* FEC_TXD_1, FEC_TXD_2, FEC_TXD_3 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc0_4), 3, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=FEC_RXD_3 Sets Next 2 to FEC pads */
-	/* FEC_RXD_3, FEC_RXD_2 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc1_4), 2, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=GPIO17 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc2_1), 1, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC3=GPIO2/GPT2 Sets Next 3 to GPIO pads */
-	/* GPIO2, GPIO20, GPIO21 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc2_4), 3, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC2=VIU_PIX_CLK */
-	{
-		offsetof(struct ioctrl512x, io_control_psc3_4), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=GPIO24 Sets Next 2 to GPIO pads */
-	/* GPIO24, GPIO25 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc4_0), 2, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC1=NFC_CE2 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc4_4), 1, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
-		IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC2=VIU_DATA5 Sets Next 5 to VIU_DATA pads */
-	/* VIU_DATA5-VIU_DATA9 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc5_0), 5, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=LPC_TSIZ1 Sets Next 2 to LPC_TSIZ pads */
-	/* LPC_TSIZ1-LPC_TSIZ2 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc6_0), 2, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=LPC_TS */
-	{
-		offsetof(struct ioctrl512x, io_control_psc6_4), 1, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=GPIO16 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc7_0), 1, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC3=GPIO18 Sets Next 3 to GPIO pads */
-	/* GPIO18-GPIO19, GPT7/GPIO7 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc7_2), 3, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC3=GPIO0/GPT0 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc8_4), 1, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC3=GPIO11 Sets Next 4 to GPIO pads */
-	/* GPIO11, GPIO2, GPIO12, GPIO13 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc10_3), 4, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC2=DIU_DE */
-	{
-		offsetof(struct ioctrl512x, io_control_psc11_4), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	}
-};
-
-int checkboard (void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
-	puts("Board: PDM360NG\n");
-
-	/* initialize function mux & slew rate IO inter alia on IO Pins  */
-
-	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
-
-	/* initialize IO_CONTROL_GP (GPIO/GPT-mux-register) */
-	setbits_be32(&im->io_ctrl.io_control_gp,
-		     (1 << 0) |   /* GP_MUX7->GPIO7 */
-		     (1 << 5));	  /* GP_MUX2->GPIO2 */
-
-	/* configure GPIO24 (VIU_CE), output/high */
-	setbits_be32(&im->gpio.gpdir, 0x80);
-	setbits_be32(&im->gpio.gpdat, 0x80);
-
-	return 0;
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-#ifdef CONFIG_FDT_FIXUP_PARTITIONS
-struct node_info nodes[] = {
-	{ "fsl,mpc5121-nfc",	MTD_DEV_TYPE_NAND, },
-	{ "cfi-flash",		MTD_DEV_TYPE_NOR,  },
-};
-#endif
-
-#if defined(CONFIG_VIDEO)
-/*
- * EDID block has been generated using Phoenix EDID Designer 1.3.
- * This tool creates a text file containing:
- *
- * EDID BYTES:
- * 0x   00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
- *     ------------------------------------------------
- * 00 | 00 FF FF FF FF FF FF 00 42 C9 34 12 01 00 00 00
- * 10 | 0A 0C 01 03 80 98 5B 78 CA 7E 50 A0 58 4E 96 25
- * 20 | 1E 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
- * 30 | 01 01 01 01 01 01 80 0C 20 00 31 E0 2D 10 2A 80
- * 40 | 12 08 30 E4 10 00 00 18 00 00 00 FD 00 38 3C 1F
- * 50 | 3C 04 0A 20 20 20 20 20 20 20 00 00 00 FF 00 50
- * 60 | 4D 30 37 30 57 4C 33 0A 0A 0A 0A 0A 00 00 00 FF
- * 70 | 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D4
- *
- * Then this data has been manually converted to the char
- * array below.
- */
-static unsigned char edid_buf[128] = {
-	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
-	0x42, 0xC9, 0x34, 0x12, 0x01, 0x00, 0x00, 0x00,
-	0x0A, 0x0C, 0x01, 0x03, 0x80, 0x98, 0x5B, 0x78,
-	0xCA, 0x7E, 0x50, 0xA0, 0x58, 0x4E, 0x96, 0x25,
-	0x1E, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01,
-	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x80, 0x0C,
-	0x20, 0x00, 0x31, 0xE0, 0x2D, 0x10, 0x2A, 0x80,
-	0x12, 0x08, 0x30, 0xE4, 0x10, 0x00, 0x00, 0x18,
-	0x00, 0x00, 0x00, 0xFD, 0x00, 0x38, 0x3C, 0x1F,
-	0x3C, 0x04, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20,
-	0x20, 0x20, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x50,
-	0x4D, 0x30, 0x37, 0x30, 0x57, 0x4C, 0x33, 0x0A,
-	0x0A, 0x0A, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0xFF,
-	0x00, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
-	0x30, 0x30, 0x30, 0x30, 0x30, 0x31, 0x00, 0xD4,
-};
-#endif
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	u32 val[8];
-	int rc, i = 0;
-
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_FDT_FIXUP_PARTITIONS
-	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
-#endif
-#if defined(CONFIG_VIDEO)
-	fdt_add_edid(blob, "fsl,mpc5121-diu", edid_buf);
-#endif
-
-	/* Fixup NOR FLASH mapping */
-	val[i++] = 0;				/* chip select number */
-	val[i++] = 0;				/* always 0 */
-	val[i++] = gd->bd->bi_flashstart;
-	val[i++] = gd->bd->bi_flashsize;
-
-	/* Fixup MRAM mapping */
-	val[i++] = 2;				/* chip select number */
-	val[i++] = 0;				/* always 0 */
-	val[i++] = CONFIG_SYS_MRAM_BASE;
-	val[i++] = CONFIG_SYS_MRAM_SIZE;
-
-	rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
-				  val, i * sizeof(u32), 1);
-	if (rc)
-		printf("Unable to update localbus ranges, err=%s\n",
-		       fdt_strerror(rc));
-
-	/* Fixup reg property in NOR Flash node */
-	i = 0;
-	val[i++] = 0;			/* always 0 */
-	val[i++] = 0;			/* start at offset 0 */
-	val[i++] = flash_info[0].size;	/* size of Bank 0 */
-
-	/* Second Bank available? */
-	if (flash_info[1].size > 0) {
-		val[i++] = 0;			/* always 0 */
-		val[i++] = flash_info[0].size;	/* offset of Bank 1 */
-		val[i++] = flash_info[1].size;	/* size of Bank 1 */
-	}
-
-	rc = fdt_find_and_setprop(blob, "/localbus/flash", "reg",
-				  val, i * sizeof(u32), 1);
-	if (rc)
-		printf("Unable to update flash reg property, err=%s\n",
-		       fdt_strerror(rc));
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-/*
- * If argument is NULL, set the LCD brightness to the
- * value from "brightness" environment variable. Set
- * the LCD brightness to the value specified by the
- * argument otherwise. Default brightness is zero.
- */
-#define MAX_BRIGHTNESS	99
-static int set_lcd_brightness(char *brightness)
-{
-	struct stdio_dev *cop_port;
-	char *env;
-	char cmd_buf[20];
-	int val = 0;
-	int cs = 0;
-	int len, i;
-
-	if (brightness) {
-		val = simple_strtol(brightness, NULL, 10);
-	} else {
-		env = getenv("brightness");
-		if (env)
-			val = simple_strtol(env, NULL, 10);
-	}
-
-	if (val < 0)
-		val = 0;
-
-	if (val > MAX_BRIGHTNESS)
-		val = MAX_BRIGHTNESS;
-
-	sprintf(cmd_buf, "$SB;%04d;", val);
-
-	len = strlen(cmd_buf);
-	for (i = 1; i <= len; i++)
-		cs += cmd_buf[i];
-
-	cs = (~cs + 1) & 0xff;
-	sprintf(cmd_buf + len, "%02X\n", cs);
-
-	/* IO Coprocessor communication */
-	cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE);
-	if (!cop_port) {
-		printf("Error: Can't open IO Coprocessor port.\n");
-		return -1;
-	}
-
-	debug("%s: cmd: %s", __func__, cmd_buf);
-	write_port(cop_port, cmd_buf);
-	/*
-	 * Wait for transmission and maybe response data
-	 * before closing the port.
-	 */
-	udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY);
-	memset(cmd_buf, 0, sizeof(cmd_buf));
-	len = read_port(cop_port, cmd_buf, sizeof(cmd_buf));
-	if (len)
-		printf("Error: %s\n", cmd_buf);
-
-	close_port(4);
-
-	return 0;
-}
-
-static int cmd_lcd_brightness(cmd_tbl_t *cmdtp, int flag,
-			      int argc, char * const argv[])
-{
-	if (argc < 2)
-		return cmd_usage(cmdtp);
-
-	return set_lcd_brightness(argv[1]);
-}
-
-U_BOOT_CMD(lcdbr, 2, 1, cmd_lcd_brightness,
-	"set LCD brightness",
-	"<brightness> - set LCD backlight level to <brightness>.\n"
-);
diff --git a/board/phytec/pcm030/Kconfig b/board/phytec/pcm030/Kconfig
deleted file mode 100644
index 3a3eab8576..0000000000
--- a/board/phytec/pcm030/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_PCM030
-
-config SYS_BOARD
-	default "pcm030"
-
-config SYS_VENDOR
-	default "phytec"
-
-config SYS_CONFIG_NAME
-	default "pcm030"
-
-endif
diff --git a/board/phytec/pcm030/MAINTAINERS b/board/phytec/pcm030/MAINTAINERS
deleted file mode 100644
index 4e2ab0d64e..0000000000
--- a/board/phytec/pcm030/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-PCM030 BOARD
-M:	Jon Smirl <jonsmirl@gmail.com>
-S:	Maintained
-F:	board/phytec/pcm030/
-F:	include/configs/pcm030.h
-F:	configs/pcm030_defconfig
-F:	configs/pcm030_LOWBOOT_defconfig
diff --git a/board/phytec/pcm030/Makefile b/board/phytec/pcm030/Makefile
deleted file mode 100644
index 2bb49dc7aa..0000000000
--- a/board/phytec/pcm030/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= pcm030.o
diff --git a/board/phytec/pcm030/README b/board/phytec/pcm030/README
deleted file mode 100644
index 05faab68c8..0000000000
--- a/board/phytec/pcm030/README
+++ /dev/null
@@ -1,42 +0,0 @@
-To build RAMBOOT, replace this section the main Makefile
-
-pcm030_config \
-pcm030_RAMBOOT_config \
-pcm030_LOWBOOT_config:	unconfig
-	@ >include/config.h
-	@[ -z "$(findstring LOWBOOT_,$@)" ] || \
-		{ echo "CONFIG_SYS_TEXT_BASE = 0xFF000000"	>board/phytec/pcm030/config.tmp ; \
-		  echo "... with LOWBOOT configuration" ; \
-		}
-	@[ -z "$(findstring RAMBOOT_,$@)" ] || \
-	       { echo "CONFIG_SYS_TEXT_BASE = 0x00100000" >board/phycore_mpc5200b_tiny/\
-			config.tmp ; \
-		 echo "... with RAMBOOT configuration" ; \
-		 echo "... remember to make sure that MBAR is already \
-				switched to 0xF0000000 !!!" ; \
-	       }
-	@$(MKCONFIG) -a pcm030 ppc mpc5xxx pcm030 phytec
-	@ echo "remember to set pcm030_REV to 0 for rev 1245.0 rev or to 1 for rev 1245.1"
-
-Alternative SDRAM settings:
-
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x715f0f00
-#define SDRAM_CONFIG1	0x73722930
-#define SDRAM_CONFIG2	0x47770000
-
-/* Settings for XLB = 99 MHz */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x714b0f00
-#define SDRAM_CONFIG1	0x63611730
-#define SDRAM_CONFIG2	0x47670000
-
-The board ships default with the environment in EEPROM
-Moving the environment to flash can be more reliable
-
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0xfe0000)
-#define CONFIG_ENV_SIZE		0x20000
-#define CONFIG_ENV_SECT_SIZE	0x20000
diff --git a/board/phytec/pcm030/mt46v32m16-75.h b/board/phytec/pcm030/mt46v32m16-75.h
deleted file mode 100644
index 47fc7c04bd..0000000000
--- a/board/phytec/pcm030/mt46v32m16-75.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * Eric Schumann, Phytec Messtechnik
- * adapted for mt46v32m16-75 DDR-RAM
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	1		/* is DDR */
-
-/* Settings for XLB = 132 MHz */
-
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x71500F00
-#define SDRAM_CONFIG1	0x73711930
-#define SDRAM_CONFIG2	0x47770000
-
-#define SDRAM_TAPDELAY	0x10000000 /* reserved Bit in MPC5200 B3-Step */
diff --git a/board/phytec/pcm030/pcm030.c b/board/phytec/pcm030/pcm030.c
deleted file mode 100644
index bdd980da91..0000000000
--- a/board/phytec/pcm030/pcm030.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2006
- * Eric Schumann, Phytec Messtechnik GmbH
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/io.h>
-
-#include "mt46v32m16-75.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start(int hi_addr)
-{
-	volatile struct mpc5xxx_cdm *cdm =
-		(struct mpc5xxx_cdm *)MPC5XXX_CDM;
-	volatile struct mpc5xxx_sdram *sdram =
-		(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	out_be32 (&sdram->ctrl,
-		(SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
-
-	/* precharge all banks */
-	out_be32 (&sdram->ctrl,
-		(SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
-
-#ifdef SDRAM_DDR
-	/* set mode register: extended mode */
-	out_be32 (&sdram->mode, (SDRAM_EMODE));
-
-	/* set mode register: reset DLL */
-	out_be32 (&sdram->mode,
-		(SDRAM_MODE | 0x04000000));
-#endif
-
-	/* precharge all banks */
-	out_be32 (&sdram->ctrl,
-		(SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
-
-	/* auto refresh */
-	out_be32 (&sdram->ctrl,
-		(SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
-
-	/* set mode register */
-	out_be32 (&sdram->mode, (SDRAM_MODE));
-
-	/* normal operation */
-	out_be32 (&sdram->ctrl,
-		(SDRAM_CONTROL | hi_addr_bit));
-
-	/* set CDM clock enable register, set MPC5200B SDRAM bus */
-	/* to reduced driver strength */
-	out_be32 (&cdm->clock_enable, (0x00CFFFFF));
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced dram_init does NOT make
- *	real use of CONFIG_SYS_SDRAM_BASE. The code does not
- *	work if CONFIG_SYS_SDRAM_BASE
- *	is something else than 0x00000000.
- */
-
-int dram_init(void)
-{
-	volatile struct mpc5xxx_mmap_ctl *mm =
-		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
-	volatile struct mpc5xxx_cdm *cdm =
-		(struct mpc5xxx_cdm *)MPC5XXX_CDM;
-	volatile struct mpc5xxx_sdram *sdram =
-		(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-							 /* 256MB at 0x0 */
-	out_be32 (&mm->sdram0, 0x0000001b);
-							 /* disabled */
-	out_be32 (&mm->sdram1, 0x10000000);
-
-	/* setup config registers */
-	out_be32 (&sdram->config1, SDRAM_CONFIG1);
-	out_be32 (&sdram->config2, SDRAM_CONFIG2);
-
-#if defined(SDRAM_DDR) && defined(SDRAM_TAPDELAY)
-	/* set tap delay */
-	out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else
-		dramsize = test2;
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		out_be32 (&mm->sdram0,
-			(0x13 + __builtin_ffs(dramsize >> 20) - 1));
-	} else {
-							/* disabled */
-		out_be32 (&mm->sdram0, 0);
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = in_be32(&mm->sdram0) & 0xFF;
-	if (dramsize >= 0x13)
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	else
-		dramsize = 0;
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = in_be32(&mm->sdram1) & 0xFF;
-	if (dramsize2 >= 0x13)
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	else
-		dramsize2 = 0;
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	gd->ram_size = dramsize + dramsize2;
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	puts("Board: phyCORE-MPC5200B-tiny\n");
-	return 0;
-}
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET)
-
-#define GPIO_PSC2_4	0x02000000UL
-
-void init_ide_reset(void)
-{
-	volatile struct mpc5xxx_wu_gpio *wu_gpio =
-		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
-	debug("init_ide_reset\n");
-
-	/* Configure PSC2_4 as GPIO output for ATA reset */
-	setbits_be32(&wu_gpio->enable, GPIO_PSC2_4);
-	setbits_be32(&wu_gpio->ddr, GPIO_PSC2_4);
-	/* Deassert reset */
-	setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
-}
-
-void ide_set_reset(int idereset)
-{
-	volatile struct mpc5xxx_wu_gpio *wu_gpio =
-		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
-	debug("ide_reset(%d)\n", idereset);
-
-	if (idereset) {
-		clrbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
-		/* Make a delay. MPC5200 spec says 25 usec min */
-		udelay(500000);
-	} else
-		setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
-}
-#endif /* defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET) */
diff --git a/board/tqc/tqm5200/Kconfig b/board/tqc/tqm5200/Kconfig
deleted file mode 100644
index 738dc80551..0000000000
--- a/board/tqc/tqm5200/Kconfig
+++ /dev/null
@@ -1,25 +0,0 @@
-if TARGET_CHARON
-
-config SYS_BOARD
-	default "tqm5200"
-
-config SYS_VENDOR
-	default "tqc"
-
-config SYS_CONFIG_NAME
-	default "charon"
-
-endif
-
-if TARGET_TQM5200
-
-config SYS_BOARD
-	default "tqm5200"
-
-config SYS_VENDOR
-	default "tqc"
-
-config SYS_CONFIG_NAME
-	default "TQM5200"
-
-endif
diff --git a/board/tqc/tqm5200/MAINTAINERS b/board/tqc/tqm5200/MAINTAINERS
deleted file mode 100644
index 12d143d73f..0000000000
--- a/board/tqc/tqm5200/MAINTAINERS
+++ /dev/null
@@ -1,23 +0,0 @@
-TQM5200 BOARD
-#M:	-
-S:	Maintained
-F:	board/tqc/tqm5200/
-F:	include/configs/aev.h
-F:	configs/aev_defconfig
-F:	include/configs/TQM5200.h
-F:	configs/cam5200_defconfig
-F:	configs/cam5200_niosflash_defconfig
-F:	configs/fo300_defconfig
-F:	configs/MiniFAP_defconfig
-F:	configs/TQM5200_defconfig
-F:	configs/TQM5200_B_defconfig
-F:	configs/TQM5200_B_HIGHBOOT_defconfig
-F:	configs/TQM5200_STK100_defconfig
-F:	configs/TQM5200S_defconfig
-F:	configs/TQM5200S_HIGHBOOT_defconfig
-
-CHARON BOARD
-M:	Heiko Schocher <hs@denx.de>
-S:	Maintained
-F:	include/configs/charon.h
-F:	configs/charon_defconfig
diff --git a/board/tqc/tqm5200/Makefile b/board/tqc/tqm5200/Makefile
deleted file mode 100644
index f7c97b72c8..0000000000
--- a/board/tqc/tqm5200/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= tqm5200.o cmd_stk52xx.o cam5200_flash.o
diff --git a/board/tqc/tqm5200/cam5200_flash.c b/board/tqc/tqm5200/cam5200_flash.c
deleted file mode 100644
index c3ae5c010b..0000000000
--- a/board/tqc/tqm5200/cam5200_flash.c
+++ /dev/null
@@ -1,768 +0,0 @@
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <asm/processor.h>
-
-#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
-
-#if 0
-#define DEBUGF(x...) printf(x)
-#else
-#define DEBUGF(x...)
-#endif
-
-#define swap16(x) __swab16(x)
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
-
-/*
- * CAM5200 is a TQM5200B based board. Additionally it also features
- * a NIOS cpu. The NIOS CPU peripherals are accessible through MPC5xxx
- * Local Bus on CS5. This includes 32 bit wide RAM and SRAM as well as
- * 16 bit wide flash device. Big Endian order on a 32 bit CS5 makes
- * access to flash chip slightly more complicated as additional byte
- * swapping is necessary within each 16 bit wide flash 'word'.
- *
- * This driver's task is to handle both flash devices: 32 bit TQM5200B
- * flash chip and 16 bit NIOS cpu flash chip. In the below
- * flash_addr_table table we use least significant address bit to mark
- * 16 bit flash bank and two sets of routines *_32 and *_16 to handle
- * specifics of both flashes.
- */
-static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = {
-	{CONFIG_SYS_BOOTCS_START, CONFIG_SYS_CS5_START | 1}
-};
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word(flash_info_t * info, ulong dest, ulong data);
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-static int write_word_32(flash_info_t * info, ulong dest, ulong data);
-static int write_word_16(flash_info_t * info, ulong dest, ulong data);
-static int flash_erase_32(flash_info_t * info, int s_first, int s_last);
-static int flash_erase_16(flash_info_t * info, int s_first, int s_last);
-static ulong flash_get_size_32(vu_long * addr, flash_info_t * info);
-static ulong flash_get_size_16(vu_long * addr, flash_info_t * info);
-#endif
-
-void flash_print_info(flash_info_t * info)
-{
-	int i, k;
-	int size, erased;
-	volatile unsigned long *flash;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-		case FLASH_MAN_AMD:
-			printf("AMD ");
-			break;
-		case FLASH_MAN_FUJ:
-			printf("FUJITSU ");
-			break;
-		default:
-			printf("Unknown Vendor ");
-			break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-		case FLASH_S29GL128N:
-			printf ("S29GL128N (256 Mbit, uniform sector size)\n");
-			break;
-		case FLASH_AM320B:
-			printf ("29LV320B (32 Mbit, bottom boot sect)\n");
-			break;
-		case FLASH_AM320T:
-			printf ("29LV320T (32 Mbit, top boot sect)\n");
-			break;
-		default:
-			printf("Unknown Chip Type\n");
-			break;
-	}
-
-	printf("  Size: %ld KB in %d Sectors\n",
-			info->size >> 10, info->sector_count);
-
-	printf("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-		/*
-		 * Check if whole sector is erased
-		 */
-		if (i != (info->sector_count - 1))
-			size = info->start[i + 1] - info->start[i];
-		else
-			size = info->start[0] + info->size - info->start[i];
-
-		erased = 1;
-		flash = (volatile unsigned long *)info->start[i];
-		size = size >> 2;	/* divide by 4 for longword access */
-
-		for (k = 0; k < size; k++) {
-			if (*flash++ != 0xffffffff) {
-				erased = 0;
-				break;
-			}
-		}
-
-		if ((i % 5) == 0)
-			printf("\n   ");
-
-		printf(" %08lX%s%s", info->start[i],
-				erased ? " E" : "  ",
-				info->protect[i] ? "RO " : "   ");
-	}
-	printf("\n");
-	return;
-}
-
-
-/*
- * The following code cannot be run from FLASH!
- */
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-static ulong flash_get_size(vu_long * addr, flash_info_t * info)
-{
-
-	DEBUGF("get_size: FLASH ADDR %08lx\n", addr);
-
-	/* bit 0 used for big flash marking */
-	if ((ulong)addr & 0x1)
-		return flash_get_size_16((vu_long *)((ulong)addr & 0xfffffffe), info);
-	else
-		return flash_get_size_32(addr, info);
-}
-
-static ulong flash_get_size_32(vu_long * addr, flash_info_t * info)
-#else
-static ulong flash_get_size(vu_long * addr, flash_info_t * info)
-#endif
-{
-	short i;
-	CONFIG_SYS_FLASH_WORD_SIZE value;
-	ulong base = (ulong) addr;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
-
-	DEBUGF("get_size32: FLASH ADDR: %08x\n", (unsigned)addr);
-
-	/* Write auto select command: read Manufacturer ID */
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
-	udelay(1000);
-
-	value = addr2[0];
-	DEBUGF("FLASH MANUFACT: %x\n", value);
-
-	switch (value) {
-		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
-			info->flash_id = FLASH_MAN_AMD;
-			break;
-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			info->sector_count = 0;
-			info->size = 0;
-			return (0);	/* no or unknown flash  */
-	}
-
-	value = addr2[1];	/* device ID            */
-	DEBUGF("\nFLASH DEVICEID: %x\n", value);
-
-	switch (value) {
-		case AMD_ID_MIRROR:
-			DEBUGF("Mirror Bit flash: addr[14] = %08lX  addr[15] = %08lX\n",
-					addr[14], addr[15]);
-			switch(addr[14]) {
-				case AMD_ID_GL128N_2:
-					if (addr[15] != AMD_ID_GL128N_3) {
-						DEBUGF("Chip: S29GL128N -> unknown\n");
-						info->flash_id = FLASH_UNKNOWN;
-					} else {
-						DEBUGF("Chip: S29GL128N\n");
-						info->flash_id += FLASH_S29GL128N;
-						info->sector_count = 128;
-						info->size = 0x02000000;
-					}
-					break;
-				default:
-					info->flash_id = FLASH_UNKNOWN;
-					return(0);
-			}
-			break;
-
-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			return (0);	/* => no or unknown flash */
-	}
-
-	/* set up sector start address table */
-	for (i = 0; i < info->sector_count; i++)
-		info->start[i] = base + (i * 0x00040000);
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
-
-		info->protect[i] = addr2[2] & 1;
-	}
-
-	/* issue bank reset to return to read mode */
-	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
-
-	return (info->size);
-}
-
-static int wait_for_DQ7_32(flash_info_t * info, int sect)
-{
-	ulong start, now, last;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
-		(CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
-	start = get_timer(0);
-	last = start;
-	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
-			(CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf("Timeout\n");
-			return -1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc('.');
-			last = now;
-		}
-	}
-	return 0;
-}
-
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-{
-	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) {
-		return flash_erase_16(info, s_first, s_last);
-	} else {
-		return flash_erase_32(info, s_first, s_last);
-	}
-}
-
-static int flash_erase_32(flash_info_t * info, int s_first, int s_last)
-#else
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-#endif
-{
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
-	int flag, prot, sect;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN)
-			printf("- missing\n");
-		else
-			printf("- no sectors to erase\n");
-		return 1;
-	}
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect])
-			prot++;
-	}
-
-	if (prot)
-		printf("- Warning: %d protected sectors will not be erased!", prot);
-
-	printf("\n");
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
-
-			/*
-			 * Wait for each sector to complete, it's more
-			 * reliable.  According to AMD Spec, you must
-			 * issue all erase commands within a specified
-			 * timeout.  This has been seen to fail, especially
-			 * if printf()s are included (for debug)!!
-			 */
-			wait_for_DQ7_32(info, sect);
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay(1000);
-
-	/* reset to read mode */
-	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
-
-	printf(" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i = 0, cp = wp; i < l; ++i, ++cp)
-			data = (data << 8) | (*(uchar *) cp);
-
-		for (; i < 4 && cnt > 0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-
-		for (; cnt == 0 && i < 4; ++i, ++cp)
-			data = (data << 8) | (*(uchar *) cp);
-
-		if ((rc = write_word(info, wp, data)) != 0)
-			return (rc);
-
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i = 0; i < 4; ++i)
-			data = (data << 8) | *src++;
-
-		if ((rc = write_word(info, wp, data)) != 0)
-			return (rc);
-
-		wp += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0)
-		return (0);
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i < 4; ++i, ++cp)
-		data = (data << 8) | (*(uchar *) cp);
-
-	return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-static int write_word(flash_info_t * info, ulong dest, ulong data)
-{
-	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) {
-		return write_word_16(info, dest, data);
-	} else {
-		return write_word_32(info, dest, data);
-	}
-}
-
-static int write_word_32(flash_info_t * info, ulong dest, ulong data)
-#else
-static int write_word(flash_info_t * info, ulong dest, ulong data)
-#endif
-{
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
-	ulong *datap = &data;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 =
-			(volatile CONFIG_SYS_FLASH_WORD_SIZE *)datap;
-	ulong start;
-	int i, flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *)dest) & data) != data)
-		return (2);
-
-	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
-		/* Disable interrupts which might cause a timeout here */
-		flag = disable_interrupts();
-
-		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
-
-		dest2[i] = data2[i];
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts();
-
-		/* data polling for D7 */
-		start = get_timer(0);
-		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
-				(data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
-
-			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
-				return (1);
-		}
-	}
-
-	return (0);
-}
-
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-
-#undef  CONFIG_SYS_FLASH_WORD_SIZE
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size_16(vu_long * addr, flash_info_t * info)
-{
-	short i;
-	CONFIG_SYS_FLASH_WORD_SIZE value;
-	ulong base = (ulong) addr;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
-
-	DEBUGF("get_size16: FLASH ADDR: %08x\n", (unsigned)addr);
-
-	/* issue bank reset to return to read mode */
-	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000;
-
-	/* Write auto select command: read Manufacturer ID */
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
-	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90009000;
-	udelay(1000);
-
-	value = swap16(addr2[0]);
-	DEBUGF("FLASH MANUFACT: %x\n", value);
-
-	switch (value) {
-		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
-			info->flash_id = FLASH_MAN_AMD;
-			break;
-		case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
-			info->flash_id = FLASH_MAN_FUJ;
-			break;
-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			info->sector_count = 0;
-			info->size = 0;
-			return (0);	/* no or unknown flash  */
-	}
-
-	value = swap16(addr2[1]);	/* device ID            */
-	DEBUGF("\nFLASH DEVICEID: %x\n", value);
-
-	switch (value) {
-		case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
-			info->flash_id += FLASH_AM320B;
-			info->sector_count = 71;
-			info->size = 0x00400000;
-			break;	/* => 4 MB	*/
-		case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
-			info->flash_id += FLASH_AM320T;
-			info->sector_count = 71;
-			info->size = 0x00400000;
-			break;	/* => 4 MB	*/
-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			return (0);	/* => no or unknown flash */
-	}
-
-	if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type        */
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00002000;
-		info->start[2] = base + 0x00004000;
-		info->start[3] = base + 0x00006000;
-		info->start[4] = base + 0x00008000;
-		info->start[5] = base + 0x0000a000;
-		info->start[6] = base + 0x0000c000;
-		info->start[7] = base + 0x0000e000;
-
-		for (i = 8; i < info->sector_count; i++)
-			info->start[i] = base + (i * 0x00010000) - 0x00070000;
-	} else {
-		/* set sector offsets for top boot block type           */
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00002000;
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00006000;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000a000;
-		info->start[i--] = base + info->size - 0x0000c000;
-		info->start[i--] = base + info->size - 0x0000e000;
-
-		for (; i >= 0; i--)
-			info->start[i] = base + i * 0x00010000;
-	}
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
-
-		info->protect[i] = addr2[2] & 1;
-	}
-
-	/* issue bank reset to return to read mode */
-	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000;
-
-	return (info->size);
-}
-
-static int wait_for_DQ7_16(flash_info_t * info, int sect)
-{
-	ulong start, now, last;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
-		(CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
-	start = get_timer(0);
-	last = start;
-	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) !=
-			(CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) {
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf("Timeout\n");
-			return -1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc('.');
-			last = now;
-		}
-	}
-	return 0;
-}
-
-static int flash_erase_16(flash_info_t * info, int s_first, int s_last)
-{
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
-	int flag, prot, sect;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN)
-			printf("- missing\n");
-		else
-			printf("- no sectors to erase\n");
-		return 1;
-	}
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect])
-			prot++;
-	}
-
-	if (prot)
-		printf("- Warning: %d protected sectors will not be erased!",	prot);
-
-	printf("\n");
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
-			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000;
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
-			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
-			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30003000;	/* sector erase */
-
-			/*
-			 * Wait for each sector to complete, it's more
-			 * reliable.  According to AMD Spec, you must
-			 * issue all erase commands within a specified
-			 * timeout.  This has been seen to fail, especially
-			 * if printf()s are included (for debug)!!
-			 */
-			wait_for_DQ7_16(info, sect);
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay(1000);
-
-	/* reset to read mode */
-	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000;	/* reset bank */
-
-	printf(" done\n");
-	return 0;
-}
-
-static int write_word_16(flash_info_t * info, ulong dest, ulong data)
-{
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
-	ulong *datap = &data;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 =
-			(volatile CONFIG_SYS_FLASH_WORD_SIZE *)datap;
-	ulong start;
-	int i;
-
-	/* Check if Flash is (sufficiently) erased */
-	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
-		if ((dest2[i] & swap16(data2[i])) != swap16(data2[i]))
-			return (2);
-	}
-
-	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
-		int flag;
-
-		/* Disable interrupts which might cause a timeout here */
-		flag = disable_interrupts();
-
-		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
-		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
-		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xA000A000;
-
-		dest2[i] = swap16(data2[i]);
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts();
-
-		/* data polling for D7 */
-		start = get_timer(0);
-		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) !=
-				(swap16(data2[i]) & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000)) {
-
-			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-				return (1);
-			}
-		}
-	}
-
-	return (0);
-}
-#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info);
-static int write_word(flash_info_t * info, ulong dest, ulong data);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init(void)
-{
-	unsigned long total_b = 0;
-	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
-	unsigned short index = 0;
-	int i;
-
-	DEBUGF("\n");
-	DEBUGF("FLASH: Index: %d\n", index);
-
-	/* Init: no FLASHes known */
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-		flash_info[i].sector_count = -1;
-		flash_info[i].size = 0;
-
-		/* check whether the address is 0 */
-		if (flash_addr_table[index][i] == 0)
-			continue;
-
-		/* call flash_get_size() to initialize sector address */
-		size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
-				&flash_info[i]);
-
-		flash_info[i].size = size_b[i];
-
-		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
-			printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
-					i+1, size_b[i], size_b[i] << 20);
-			flash_info[i].sector_count = -1;
-			flash_info[i].size = 0;
-		}
-
-		/* Monitor protection ON by default */
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
-				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
-				    &flash_info[i]);
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
-				    CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-				    &flash_info[i]);
-#if defined(CONFIG_ENV_ADDR_REDUND)
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
-				    CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
-				    &flash_info[i]);
-#endif
-#endif
-		total_b += flash_info[i].size;
-	}
-
-	return total_b;
-}
-#endif /* if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) */
diff --git a/board/tqc/tqm5200/cmd_stk52xx.c b/board/tqc/tqm5200/cmd_stk52xx.c
deleted file mode 100644
index a3916ed957..0000000000
--- a/board/tqc/tqm5200/cmd_stk52xx.c
+++ /dev/null
@@ -1,1228 +0,0 @@
-/*
- * (C) Copyright 2005
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * STK52XX specific functions
- */
-/*#define DEBUG*/
-
-#include <common.h>
-#include <command.h>
-#include <console.h>
-
-#if defined(CONFIG_CMD_BSP)
-
-#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
-#define DEFAULT_VOL	45
-#define DEFAULT_FREQ	500
-#define DEFAULT_DURATION	200
-#define LEFT		1
-#define RIGHT		2
-#define LEFT_RIGHT	3
-#define BL_OFF		0
-#define BL_ON		1
-
-#define SM501_GPIO_CTRL_LOW		0x00000008UL
-#define SM501_GPIO_CTRL_HIGH		0x0000000CUL
-#define SM501_POWER_MODE0_GATE		0x00000040UL
-#define SM501_POWER_MODE1_GATE		0x00000048UL
-#define POWER_MODE_GATE_GPIO_PWM_I2C	0x00000040UL
-#define SM501_GPIO_DATA_LOW		0x00010000UL
-#define SM501_GPIO_DATA_HIGH		0x00010004UL
-#define SM501_GPIO_DATA_DIR_LOW		0x00010008UL
-#define SM501_GPIO_DATA_DIR_HIGH	0x0001000CUL
-#define SM501_PANEL_DISPLAY_CONTROL	0x00080000UL
-
-static int i2s_squarewave(unsigned long duration, unsigned int freq,
-			  unsigned int channel);
-static int i2s_sawtooth(unsigned long duration, unsigned int freq,
-			unsigned int channel);
-static void spi_init(void);
-static int spi_transmit(unsigned char data);
-static void pcm1772_write_reg(unsigned char addr, unsigned char data);
-static void set_attenuation(unsigned char attenuation);
-
-static void spi_init(void)
-{
-	struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-
-	/* PSC3 as SPI and GPIOs */
-	gpio->port_config &= 0xFFFFF0FF;
-	gpio->port_config |= 0x00000800;
-	/*
-	 * Its important to use the correct order when initializing the
-	 * registers
-	 */
-	spi->ddr = 0x0F; /* set all SPI pins as output */
-	spi->pdr = 0x08; /* set SS high */
-	spi->cr1 = 0x50; /* SPI is master, SS is general purpose output */
-	spi->cr2 = 0x00; /* normal operation */
-	spi->brr = 0xFF; /* baud rate: IPB clock / 2048 */
-}
-
-static int spi_transmit(unsigned char data)
-{
-	struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
-
-	spi->dr = data;
-	/* wait for SPI transmission completed */
-	while (!(spi->sr & 0x80)) {
-		if (spi->sr & 0x40) {	/* if write collision occurred */
-			int dummy;
-
-			/* do dummy read to clear status register */
-			dummy = spi->dr;
-			printf("SPI write collision: dr=0x%x\n", dummy);
-			return -1;
-		}
-	}
-	return (spi->dr);
-}
-
-static void pcm1772_write_reg(unsigned char addr, unsigned char data)
-{
-	struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
-
-	spi->pdr = 0x00; /* Set SS low */
-	spi_transmit(addr);
-	spi_transmit(data);
-	/* wait some time to meet MS# hold time of PCM1772 */
-	udelay (1);
-	spi->pdr = 0x08; /* set SS high */
-}
-
-static void set_attenuation(unsigned char attenuation)
-{
-	pcm1772_write_reg(0x01, attenuation); /* left channel */
-	debug ("PCM1772 attenuation left set to %d.\n", attenuation);
-	pcm1772_write_reg(0x02, attenuation); /* right channel */
-	debug ("PCM1772 attenuation right set to %d.\n", attenuation);
-}
-
-void amplifier_init(void)
-{
-	static int init_done = 0;
-	int i;
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-
-	/* Do this only once, because of the long time delay */
-	if (!init_done) {
-		/* configure PCM1772 audio format as I2S */
-		pcm1772_write_reg(0x03, 0x01);
-		/* enable audio amplifier */
-		gpio->sint_gpioe |=  0x02;	/* PSC3_5 as GPIO */
-		gpio->sint_ode &= ~0x02;	/* PSC3_5 is not open Drain */
-		gpio->sint_dvo &= ~0x02;	/* PSC3_5 is LOW */
-		gpio->sint_ddr |=  0x02;	/* PSC3_5 as output */
-		/*
-		 * wait some time to allow amplifier to recover from shutdown
-		 * mode.
-		 */
-		for(i = 0; i < 350; i++)
-			udelay(1000);
-		/*
-		 * The used amplifier (LM4867) has a so called "pop and click"
-		 * elmination filter. The input signal of the amplifier must
-		 * exceed a certain level once after power up to activate the
-		 * generation of the output signal. This is achieved by
-		 * sending a low frequent (nearly inaudible) sawtooth with a
-		 * sufficient signal level.
-		 */
-		set_attenuation(50);
-		i2s_sawtooth (200, 5, LEFT_RIGHT);
-		init_done = 1;
-	}
-}
-
-static void i2s_init(void)
-{
-	unsigned long i;
-	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-
-	gpio->port_config |= 0x00000070; /* PSC2 ports as Codec with MCLK */
-	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
-	psc->sicr = 0x22E00000;		/* 16 bit data; I2S */
-
-	*(vu_long *)(CONFIG_SYS_MBAR + 0x22C) = 0x805d; /* PSC2 CDM MCLK config; MCLK
-						  * 5.617 MHz */
-	*(vu_long *)(CONFIG_SYS_MBAR + 0x214) |= 0x00000040; /* CDM clock enable
-						       * register */
-	psc->ccr = 0x1F03;	/* 16 bit data width; 5.617MHz MCLK */
-	psc->ctur = 0x0F;	/* 16 bit frame width */
-
-	for (i = 0; i < 128; i++)
-		psc->psc_buffer_32 = 0; /* clear tx fifo */
-}
-
-static int i2s_play_wave(unsigned long addr, unsigned long len)
-{
-	unsigned long i;
-	unsigned char *wave_file = (uchar *)addr + 44;	/* quick'n dirty: skip
-							 * wav header*/
-	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
-
-	/*
-	 * play wave file in memory; bytes/words are be swapped
-	 */
-	psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
-
-	for(i = 0;i < (len / 4); i++) {
-		unsigned char swapped[4];
-		unsigned long *p = (unsigned long*)swapped;
-
-		swapped[3] = *wave_file++;
-		swapped[2] = *wave_file++;
-		swapped[1] = *wave_file++;
-		swapped[0] = *wave_file++;
-
-		psc->psc_buffer_32 =  *p;
-
-		while (psc->tfnum > 400) {
-			if(ctrlc())
-				return 0;
-		}
-	}
-	while (psc->tfnum > 0);		/* wait for fifo empty */
-	udelay (100);
-	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
-	return 0;
-}
-
-static int i2s_sawtooth(unsigned long duration, unsigned int freq,
-			unsigned int channel)
-{
-	long i,j;
-	unsigned long data;
-	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
-
-	psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
-
-	/*
-	 * Generate sawtooth. Start with middle level up to highest level. Then
-	 * go to lowest level and back to middle level.
-	 */
-	for(j = 0; j < ((duration * freq) / 1000); j++)	{
-		for(i = 0; i <= 0x7FFF; i += (0x7FFF/(44100/(freq*4))))	{
-			data = (i & 0xFFFF);
-			/* data format: right data left data) */
-			if (channel == LEFT_RIGHT)
-				data |= (data<<16);
-			if (channel == RIGHT)
-				data = (data<<16);
-			psc->psc_buffer_32 = data;
-			while (psc->tfnum > 400);
-		}
-		for(i = 0x7FFF; i >= -0x7FFF; i -= (0xFFFF/(44100/(freq*2)))) {
-			data = (i & 0xFFFF);
-			/* data format: right data left data) */
-			if (channel == LEFT_RIGHT)
-				data |= (data<<16);
-			if (channel == RIGHT)
-				data = (data<<16);
-			psc->psc_buffer_32 = data;
-			while (psc->tfnum > 400);
-		}
-		for(i = -0x7FFF; i <= 0; i += (0x7FFF/(44100/(freq*4)))) {
-			data = (i & 0xFFFF);
-			/* data format: right data left data) */
-			if (channel == LEFT_RIGHT)
-				data |= (data<<16);
-			if (channel == RIGHT)
-				data = (data<<16);
-			psc->psc_buffer_32 = data;
-			while (psc->tfnum > 400);
-		}
-	}
-	while (psc->tfnum > 0);		/* wait for fifo empty */
-	udelay (100);
-	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
-
-	return 0;
-}
-
-static int i2s_squarewave(unsigned long duration, unsigned int freq,
-			 unsigned int channel)
-{
-	long i,j;
-	unsigned long data;
-	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
-
-	psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
-
-	/*
-	 * Generate sqarewave. Start with high level, duty cycle 1:1.
-	 */
-	for(j = 0; j < ((duration * freq) / 1000); j++)	{
-		for(i = 0; i < (44100/(freq*2)); i ++) {
-			data = 0x7FFF;
-			/* data format: right data left data) */
-			if (channel == LEFT_RIGHT)
-				data |= (data<<16);
-			if (channel == RIGHT)
-				data = (data<<16);
-			psc->psc_buffer_32 = data;
-			while (psc->tfnum > 400);
-		}
-		for(i = 0; i < (44100/(freq*2)); i ++) {
-			data = 0x8000;
-			/* data format: right data left data) */
-			if (channel == LEFT_RIGHT)
-				data |= (data<<16);
-			if (channel == RIGHT)
-				data = (data<<16);
-			psc->psc_buffer_32 = data;
-			while (psc->tfnum > 400);
-		}
-	}
-	while (psc->tfnum > 0);		/* wait for fifo empty */
-	udelay (100);
-	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
-
-	return 0;
-}
-
-static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	unsigned long reg, val, duration;
-	char *tmp;
-	unsigned int freq, channel;
-	unsigned char volume;
-	int rcode = 1;
-
-#ifdef CONFIG_STK52XX_REV100
-	printf ("Revision 100 of STK52XX not supported!\n");
-	return 1;
-#endif
-	spi_init();
-	i2s_init();
-	amplifier_init();
-
-	if ((tmp = getenv ("volume")) != NULL) {
-		volume = simple_strtoul (tmp, NULL, 10);
-	} else {
-		volume = DEFAULT_VOL;
-	}
-	set_attenuation(volume);
-
-	switch (argc) {
-	case 0:
-	case 1:
-		return cmd_usage(cmdtp);
-	case 2:
-		if (strncmp(argv[1],"saw",3) == 0) {
-			printf ("Play sawtooth\n");
-			rcode = i2s_sawtooth (DEFAULT_DURATION, DEFAULT_FREQ,
-					      LEFT_RIGHT);
-			return rcode;
-		} else if (strncmp(argv[1],"squ",3) == 0) {
-			printf ("Play squarewave\n");
-			rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ,
-						LEFT_RIGHT);
-			return rcode;
-		}
-
-		return cmd_usage(cmdtp);
-	case 3:
-		if (strncmp(argv[1],"saw",3) == 0) {
-			duration = simple_strtoul(argv[2], NULL, 10);
-			printf ("Play sawtooth\n");
-			rcode = i2s_sawtooth (duration, DEFAULT_FREQ,
-					      LEFT_RIGHT);
-			return rcode;
-		} else if (strncmp(argv[1],"squ",3) == 0) {
-			duration = simple_strtoul(argv[2], NULL, 10);
-			printf ("Play squarewave\n");
-			rcode = i2s_squarewave (duration, DEFAULT_FREQ,
-						LEFT_RIGHT);
-			return rcode;
-		}
-		return cmd_usage(cmdtp);
-	case 4:
-		if (strncmp(argv[1],"saw",3) == 0) {
-			duration = simple_strtoul(argv[2], NULL, 10);
-			freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
-			printf ("Play sawtooth\n");
-			rcode = i2s_sawtooth (duration, freq,
-					      LEFT_RIGHT);
-			return rcode;
-		} else if (strncmp(argv[1],"squ",3) == 0) {
-			duration = simple_strtoul(argv[2], NULL, 10);
-			freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
-			printf ("Play squarewave\n");
-			rcode = i2s_squarewave (duration, freq,
-						LEFT_RIGHT);
-			return rcode;
-		} else if (strcmp(argv[1],"pcm1772") == 0) {
-			reg = simple_strtoul(argv[2], NULL, 10);
-			val = simple_strtoul(argv[3], NULL, 10);
-			printf("Set PCM1772 %lu. %lu\n", reg, val);
-			pcm1772_write_reg((uchar)reg, (uchar)val);
-			return 0;
-		}
-		return cmd_usage(cmdtp);
-	case 5:
-		if (strncmp(argv[1],"saw",3) == 0) {
-			duration = simple_strtoul(argv[2], NULL, 10);
-			freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
-			if (strncmp(argv[4],"l",1) == 0)
-				channel = LEFT;
-			else if (strncmp(argv[4],"r",1) == 0)
-				channel = RIGHT;
-			else
-				channel = LEFT_RIGHT;
-			printf ("Play squarewave\n");
-			rcode = i2s_sawtooth (duration, freq,
-					      channel);
-			return rcode;
-		} else if (strncmp(argv[1],"squ",3) == 0) {
-			duration = simple_strtoul(argv[2], NULL, 10);
-			freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
-			if (strncmp(argv[4],"l",1) == 0)
-				channel = LEFT;
-			else if (strncmp(argv[4],"r",1) == 0)
-				channel = RIGHT;
-			else
-				channel = LEFT_RIGHT;
-			printf ("Play squarewave\n");
-			rcode = i2s_squarewave (duration, freq,
-						channel);
-			return rcode;
-		}
-		return cmd_usage(cmdtp);
-	}
-	printf ("Usage:\nsound cmd [arg1] [arg2] ...\n");
-	return 1;
-}
-
-static int cmd_wav(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	unsigned long length, addr;
-	unsigned char volume;
-	int rcode = 1;
-	char *tmp;
-
-#ifdef CONFIG_STK52XX_REV100
-	printf ("Revision 100 of STK52XX not supported!\n");
-	return 1;
-#endif
-	spi_init();
-	i2s_init();
-	amplifier_init();
-
-	switch (argc) {
-
-	case 3:
-		length = simple_strtoul(argv[2], NULL, 16);
-		addr = simple_strtoul(argv[1], NULL, 16);
-		break;
-
-	case 2:
-		if ((tmp = getenv ("filesize")) != NULL) {
-			length = simple_strtoul (tmp, NULL, 16);
-		} else {
-			puts ("No filesize provided\n");
-			return 1;
-		}
-		addr = simple_strtoul(argv[1], NULL, 16);
-
-	case 1:
-		if ((tmp = getenv ("filesize")) != NULL) {
-			length = simple_strtoul (tmp, NULL, 16);
-		} else {
-			puts ("No filesize provided\n");
-			return 1;
-		}
-		if ((tmp = getenv ("loadaddr")) != NULL) {
-			addr = simple_strtoul (tmp, NULL, 16);
-		} else {
-			puts ("No loadaddr provided\n");
-			return 1;
-		}
-		break;
-
-	default:
-		printf("Usage:\nwav <addr> <length[s]\n");
-		return 1;
-		break;
-	}
-
-	if ((tmp = getenv ("volume")) != NULL) {
-		volume = simple_strtoul (tmp, NULL, 10);
-	} else {
-		volume = DEFAULT_VOL;
-	}
-	set_attenuation(volume);
-
-	printf("Play wave file at %lX with length %lX\n", addr, length);
-	rcode = i2s_play_wave(addr, length);
-
-	return rcode;
-}
-
-static int cmd_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	unsigned char volume;
-	unsigned int channel;
-	int rcode;
-	char *tmp;
-
-#ifdef CONFIG_STK52XX_REV100
-	printf ("Revision 100 of STK52XX not supported!\n");
-	return 1;
-#endif
-	spi_init();
-	i2s_init();
-	amplifier_init();
-
-	switch (argc) {
-	case 0:
-	case 1:
-		channel = LEFT_RIGHT;
-		break;
-	case 2:
-		if (strncmp(argv[1],"l",1) == 0)
-			channel = LEFT;
-		else if (strncmp(argv[1],"r",1) == 0)
-			channel = RIGHT;
-		else
-			channel = LEFT_RIGHT;
-		break;
-	default:
-		return cmd_usage(cmdtp);
-	}
-
-	if ((tmp = getenv ("volume")) != NULL) {
-		volume = simple_strtoul (tmp, NULL, 10);
-	} else {
-		volume = DEFAULT_VOL;
-	}
-	set_attenuation(volume);
-
-	printf("Beep on ");
-	if (channel == LEFT)
-		printf ("left ");
-	else if (channel == RIGHT)
-		printf ("right ");
-	else
-		printf ("left and right ");
-	printf ("channel\n");
-
-	rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ, channel);
-
-	return rcode;
-}
-#endif
-
-#if defined(CONFIG_STK52XX)
-void led_init(void)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
-
-	/* configure PSC3 for SPI and GPIO */
-	gpio->port_config &= ~(0x00000F00);
-	gpio->port_config |=   0x00000800;
-
-	gpio->simple_gpioe &= ~(0x00000F00);
-	gpio->simple_gpioe |=   0x00000F00;
-
-	gpio->simple_ddr &= ~(0x00000F00);
-	gpio->simple_ddr |=   0x00000F00;
-
-	/* configure timer 4-7 for simple GPIO output */
-	gpt->gpt4.emsr |=  0x00000024;
-	gpt->gpt5.emsr |=  0x00000024;
-	gpt->gpt6.emsr |=  0x00000024;
-	gpt->gpt7.emsr |=  0x00000024;
-
-#ifndef CONFIG_TQM5200S
-	/* enable SM501 GPIO control (in both power modes) */
-	*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
-		POWER_MODE_GATE_GPIO_PWM_I2C;
-	*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
-		POWER_MODE_GATE_GPIO_PWM_I2C;
-
-	/* configure SM501 gpio pins 24-27 as output */
-	*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_CTRL_LOW) &= ~(0xF << 24);
-	*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_LOW) |= (0xF << 24);
-
-	/* configure SM501 gpio pins 48-51 as output */
-	*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= (0xF << 16);
-#endif /* !CONFIG_TQM5200S */
-}
-
-/*
- * return 1 if led number unknown
- * return 0 else
- */
-int do_led(char * const argv[])
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
-
-	switch	(simple_strtoul(argv[2], NULL, 10)) {
-
-	case 0:
-		if (strcmp (argv[3], "on") == 0) {
-			gpio->simple_dvo |=   (1 << 8);
-		} else {
-			gpio->simple_dvo &= ~(1 << 8);
-		}
-		break;
-
-	case 1:
-		if (strcmp (argv[3], "on") == 0) {
-			gpio->simple_dvo |=   (1 << 9);
-		} else {
-			gpio->simple_dvo &= ~(1 << 9);
-		}
-		break;
-
-	case 2:
-		if (strcmp (argv[3], "on") == 0) {
-			gpio->simple_dvo |=   (1 << 10);
-		} else {
-			gpio->simple_dvo &= ~(1 << 10);
-		}
-		break;
-
-	case 3:
-		if (strcmp (argv[3], "on") == 0) {
-			gpio->simple_dvo |=   (1 << 11);
-		} else {
-			gpio->simple_dvo &= ~(1 << 11);
-		}
-		break;
-
-	case 4:
-		if (strcmp (argv[3], "on") == 0) {
-			gpt->gpt4.emsr |=  (1 << 4);
-		} else {
-			gpt->gpt4.emsr &=  ~(1 << 4);
-		}
-		break;
-
-	case 5:
-		if (strcmp (argv[3], "on") == 0) {
-			gpt->gpt5.emsr |=  (1 << 4);
-		} else {
-			gpt->gpt5.emsr &=  ~(1 << 4);
-		}
-		break;
-
-	case 6:
-		if (strcmp (argv[3], "on") == 0) {
-			gpt->gpt6.emsr |=  (1 << 4);
-		} else {
-			gpt->gpt6.emsr &=  ~(1 << 4);
-		}
-		break;
-
-	case 7:
-		if (strcmp (argv[3], "on") == 0) {
-			gpt->gpt7.emsr |=  (1 << 4);
-		} else {
-			gpt->gpt7.emsr &=  ~(1 << 4);
-		}
-		break;
-#ifndef CONFIG_TQM5200S
-	case 24:
-		if (strcmp (argv[3], "on") == 0) {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
-				(0x1 << 24);
-		} else {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
-				~(0x1 << 24);
-		}
-		break;
-
-	case 25:
-		if (strcmp (argv[3], "on") == 0) {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
-				(0x1 << 25);
-		} else {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
-				~(0x1 << 25);
-		}
-		break;
-
-	case 26:
-		if (strcmp (argv[3], "on") == 0) {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
-				(0x1 << 26);
-		} else {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
-				~(0x1 << 26);
-		}
-		break;
-
-	case 27:
-		if (strcmp (argv[3], "on") == 0) {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
-				(0x1 << 27);
-		} else {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
-				~(0x1 << 27);
-		}
-		break;
-
-	case 48:
-		if (strcmp (argv[3], "on") == 0) {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
-				(0x1 << 16);
-		} else {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
-				~(0x1 << 16);
-		}
-		break;
-
-	case 49:
-		if (strcmp (argv[3], "on") == 0) {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
-				(0x1 << 17);
-		} else {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
-				~(0x1 << 17);
-		}
-		break;
-
-	case 50:
-		if (strcmp (argv[3], "on") == 0) {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
-				(0x1 << 18);
-		} else {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
-				~(0x1 << 18);
-		}
-		break;
-
-	case 51:
-		if (strcmp (argv[3], "on") == 0) {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
-				(0x1 << 19);
-		} else {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
-				~(0x1 << 19);
-		}
-		break;
-#endif /* !CONFIG_TQM5200S */
-	default:
-		printf ("%s: invalid led number %s\n", __FUNCTION__, argv[2]);
-		return 1;
-	}
-
-	return 0;
-}
-#endif
-
-#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
-/*
- * return 1 on CAN initialization failure
- * return 0 if no failure
- */
-int can_init(void)
-{
-	static int init_done = 0;
-	int i;
-	struct mpc5xxx_mscan *can1 =
-		(struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0900);
-	struct mpc5xxx_mscan *can2 =
-		(struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0980);
-
-	/* GPIO configuration of the CAN pins is done in TQM5200.h */
-
-	if (!init_done) {
-		/* init CAN 1 */
-		can1->canctl1 |= 0x80;	/* CAN enable */
-		udelay(100);
-
-		i = 0;
-		can1->canctl0 |= 0x02;	/* sleep mode */
-		/* wait until sleep mode reached */
-		while (!(can1->canctl1 & 0x02)) {
-			udelay(10);
-		i++;
-		if (i == 10) {
-			printf ("%s: CAN1 initialize error, "
-				"can not enter sleep mode!\n",
-				__FUNCTION__);
-			return 1;
-		}
-		}
-		i = 0;
-		can1->canctl0 = 0x01;	/* enter init mode */
-		/* wait until init mode reached */
-		while (!(can1->canctl1 & 0x01)) {
-			udelay(10);
-			i++;
-			if (i == 10) {
-				printf ("%s: CAN1 initialize error, "
-					"can not enter init mode!\n",
-					__FUNCTION__);
-				return 1;
-			}
-		}
-		can1->canctl1 = 0x80;
-		can1->canctl1 |= 0x40;
-		can1->canbtr0 = 0x0F;
-		can1->canbtr1 = 0x7F;
-		can1->canidac &= ~(0x30);
-		can1->canidar1 = 0x00;
-		can1->canidar3 = 0x00;
-		can1->canidar5 = 0x00;
-		can1->canidar7 = 0x00;
-		can1->canidmr0 = 0xFF;
-		can1->canidmr1 = 0xFF;
-		can1->canidmr2 = 0xFF;
-		can1->canidmr3 = 0xFF;
-		can1->canidmr4 = 0xFF;
-		can1->canidmr5 = 0xFF;
-		can1->canidmr6 = 0xFF;
-		can1->canidmr7 = 0xFF;
-
-		i = 0;
-		can1->canctl0 &= ~(0x01);	/* leave init mode */
-		can1->canctl0 &= ~(0x02);
-		/* wait until init and sleep mode left */
-		while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) {
-			udelay(10);
-			i++;
-			if (i == 10) {
-				printf ("%s: CAN1 initialize error, "
-					"can not leave init/sleep mode!\n",
-					__FUNCTION__);
-				return 1;
-			}
-		}
-
-		/* init CAN 2 */
-		can2->canctl1 |= 0x80;	/* CAN enable */
-		udelay(100);
-
-		i = 0;
-		can2->canctl0 |= 0x02;	/* sleep mode */
-		/* wait until sleep mode reached */
-		while (!(can2->canctl1 & 0x02))	{
-			udelay(10);
-			i++;
-			if (i == 10) {
-				printf ("%s: CAN2 initialize error, "
-					"can not enter sleep mode!\n",
-					__FUNCTION__);
-				return 1;
-			}
-		}
-		i = 0;
-		can2->canctl0 = 0x01;	/* enter init mode */
-		/* wait until init mode reached */
-		while (!(can2->canctl1 & 0x01))	{
-			udelay(10);
-			i++;
-			if (i == 10) {
-				printf ("%s: CAN2 initialize error, "
-					"can not enter init mode!\n",
-					__FUNCTION__);
-				return 1;
-			}
-		}
-		can2->canctl1 = 0x80;
-		can2->canctl1 |= 0x40;
-		can2->canbtr0 = 0x0F;
-		can2->canbtr1 = 0x7F;
-		can2->canidac &= ~(0x30);
-		can2->canidar1 = 0x00;
-		can2->canidar3 = 0x00;
-		can2->canidar5 = 0x00;
-		can2->canidar7 = 0x00;
-		can2->canidmr0 = 0xFF;
-		can2->canidmr1 = 0xFF;
-		can2->canidmr2 = 0xFF;
-		can2->canidmr3 = 0xFF;
-		can2->canidmr4 = 0xFF;
-		can2->canidmr5 = 0xFF;
-		can2->canidmr6 = 0xFF;
-		can2->canidmr7 = 0xFF;
-		can2->canctl0 &= ~(0x01);	/* leave init mode */
-		can2->canctl0 &= ~(0x02);
-
-		i = 0;
-		/* wait until init mode left */
-		while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) {
-			udelay(10);
-			i++;
-			if (i == 10) {
-				printf ("%s: CAN2 initialize error, "
-					"can not leave init/sleep mode!\n",
-					__FUNCTION__);
-				return 1;
-			}
-		}
-		init_done = 1;
-	}
-	return 0;
-}
-
-/*
- * return 1 on CAN failure
- * return 0 if no failure
- */
-int do_can(char * const argv[])
-{
-	int i;
-	struct mpc5xxx_mscan *can1 =
-		(struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0900);
-	struct mpc5xxx_mscan *can2 =
-		(struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0980);
-
-	/* send a message on CAN1 */
-	can1->cantbsel = 0x01;
-	can1->cantxfg.idr[0] = 0x55;
-	can1->cantxfg.idr[1] = 0x00;
-	can1->cantxfg.idr[1] &= ~0x8;
-	can1->cantxfg.idr[1] &= ~0x10;
-	can1->cantxfg.dsr[0] = 0xCC;
-	can1->cantxfg.dlr = 1;
-	can1->cantxfg.tbpr = 0;
-	can1->cantflg = 0x01;
-
-	i = 0;
-	while ((can1->cantflg & 0x01) == 0) {
-		i++;
-		if (i == 10) {
-			printf ("%s: CAN1 send timeout, "
-				"can not send message!\n",
-				__FUNCTION__);
-			return 1;
-		}
-		udelay(1000);
-	}
-	udelay(1000);
-
-	i = 0;
-	while (!(can2->canrflg & 0x01))	{
-		i++;
-		if (i == 10) {
-			printf ("%s: CAN2 receive timeout, "
-				"no message received!\n",
-				__FUNCTION__);
-			return 1;
-		}
-		udelay(1000);
-	}
-
-	if (can2->canrxfg.dsr[0] != 0xCC) {
-		printf ("%s: CAN2 receive error, "
-			 "data mismatch!\n",
-			__FUNCTION__);
-		return 1;
-	}
-
-	/* send a message on CAN2 */
-	can2->cantbsel = 0x01;
-	can2->cantxfg.idr[0] = 0x55;
-	can2->cantxfg.idr[1] = 0x00;
-	can2->cantxfg.idr[1] &= ~0x8;
-	can2->cantxfg.idr[1] &= ~0x10;
-	can2->cantxfg.dsr[0] = 0xCC;
-	can2->cantxfg.dlr = 1;
-	can2->cantxfg.tbpr = 0;
-	can2->cantflg = 0x01;
-
-	i = 0;
-	while ((can2->cantflg & 0x01) == 0) {
-		i++;
-		if (i == 10) {
-			printf ("%s: CAN2 send error, "
-				"can not send message!\n",
-				__FUNCTION__);
-			return 1;
-		}
-		udelay(1000);
-	}
-	udelay(1000);
-
-	i = 0;
-	while (!(can1->canrflg & 0x01))	{
-		i++;
-		if (i == 10) {
-			printf ("%s: CAN1 receive timeout, "
-				"no message received!\n",
-				__FUNCTION__);
-			return 1;
-		}
-		udelay(1000);
-	}
-
-	if (can1->canrxfg.dsr[0] != 0xCC) {
-		printf ("%s: CAN1 receive error 0x%02x\n",
-			__FUNCTION__, (can1->canrxfg.dsr[0]));
-		return 1;
-	}
-
-	return 0;
-}
-
-/*
- * return 1 if rs232 port unknown
- * return 2 on txd/rxd failure (only rs232 2)
- * return 3 on rts/cts failure
- * return 0 if no failure
- */
-int do_rs232(char * const argv[])
-{
-	int error_status = 0;
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-	struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
-
-	switch	(simple_strtoul(argv[2], NULL, 10)) {
-
-	case 1:
-		/* check RTS <-> CTS loop */
-		/* set rts to 0 */
-		psc1->op1 |= 0x01;
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		/* check status at cts */
-		if ((psc1->ip & 0x01) != 0) {
-			error_status = 3;
-			printf ("%s: failure at rs232_1, cts status is %d "
-				"(should be 0)\n",
-				__FUNCTION__, (psc1->ip & 0x01));
-		}
-
-		/* set rts to 1 */
-		psc1->op0 |= 0x01;
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		/* check status at cts */
-		if ((psc1->ip & 0x01) != 1) {
-			error_status = 3;
-			printf ("%s: failure at rs232_1, cts status is %d "
-				"(should be 1)\n",
-				__FUNCTION__, (psc1->ip & 0x01));
-		}
-
-		break;
-
-	case 2:
-		/* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */
-		gpio->simple_ddr &= ~(0x00000F00);
-		gpio->simple_ddr |=   0x00000500;
-
-		/* check TXD <-> RXD loop */
-		/* set TXD to 1 */
-		gpio->simple_dvo |=   (1 << 8);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000200) != 0x00000200) {
-			error_status = 2;
-			printf ("%s: failure at rs232_2, rxd status is %d "
-				"(should be 1)\n",
-				__FUNCTION__,
-				(gpio->simple_ival & 0x00000200) >> 9);
-		}
-
-		/* set TXD to 0 */
-		gpio->simple_dvo &= ~(1 << 8);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000200) != 0x00000000) {
-			error_status = 2;
-			printf ("%s: failure at rs232_2, rxd status is %d "
-				"(should be 0)\n",
-				__FUNCTION__,
-				(gpio->simple_ival & 0x00000200) >> 9);
-		}
-
-		/* check RTS <-> CTS loop */
-		/* set RTS to 1 */
-		gpio->simple_dvo |=   (1 << 10);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000800) != 0x00000800) {
-			error_status = 3;
-			printf ("%s: failure at rs232_2, cts status is %d "
-				"(should be 1)\n",
-				__FUNCTION__,
-				(gpio->simple_ival & 0x00000800) >> 11);
-		}
-
-		/* set RTS to 0 */
-		gpio->simple_dvo &= ~(1 << 10);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000800) != 0x00000000) {
-			error_status = 3;
-			printf ("%s: failure at rs232_2, cts status is %d "
-				"(should be 0)\n",
-				__FUNCTION__,
-				(gpio->simple_ival & 0x00000800) >> 11);
-		}
-
-		/* set PSC3_0, PSC3_1, PSC3_2 and PSC3_3 as output */
-		gpio->simple_ddr &= ~(0x00000F00);
-		gpio->simple_ddr |=   0x00000F00;
-		break;
-
-	default:
-		printf ("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]);
-		error_status = 1;
-		break;
-	}
-
-	return error_status;
-}
-
-#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S)
-static void sm501_backlight (unsigned int state)
-{
-	if (state == BL_ON) {
-		*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |=
-			(1 << 26) | (1 << 27);
-	} else if (state == BL_OFF)
-		*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &=
-			~((1 << 26) | (1 << 27));
-}
-#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */
-
-int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int rcode;
-
-#ifdef CONFIG_STK52XX_REV100
-	printf ("Revision 100 of STK52XX not supported!\n");
-	return 1;
-#endif
-#if defined(CONFIG_STK52XX)
-	led_init();
-#endif
-	can_init();
-
-	switch (argc) {
-
-	case 0:
-	case 1:
-		break;
-
-	case 2:
-		if (strncmp (argv[1], "can", 3) == 0) {
-			rcode = do_can (argv);
-			if (rcode == 0)
-				printf ("OK\n");
-			else
-				printf ("Error\n");
-			return rcode;
-		}
-		break;
-
-	case 3:
-		if (strncmp (argv[1], "rs232", 3) == 0) {
-			rcode = do_rs232 (argv);
-			if (rcode == 0)
-				printf ("OK\n");
-			else
-				printf ("Error\n");
-			return rcode;
-#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S)
-		} else if (strncmp (argv[1], "backlight", 4) == 0) {
-			if (strncmp (argv[2], "on", 2) == 0) {
-				sm501_backlight (BL_ON);
-				return 0;
-			}
-			else if (strncmp (argv[2], "off", 3) == 0) {
-				sm501_backlight (BL_OFF);
-				return 0;
-			}
-#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */
-		}
-		break;
-
-#if defined(CONFIG_STK52XX)
-	case 4:
-		if (strcmp (argv[1], "led") == 0) {
-			return (do_led (argv));
-		}
-		break;
-#endif
-
-	default:
-		break;
-	}
-
-	printf ("Usage:\nfkt cmd [arg1] [arg2] ...\n");
-	return 1;
-}
-
-
-U_BOOT_CMD(
-	sound ,    5,    1,     cmd_sound,
-	"Sound sub-system",
-	"saw [duration] [freq] [channel]\n"
-	"    - generate sawtooth for 'duration' ms with frequency 'freq'\n"
-	"      on left \"l\" or right \"r\" channel\n"
-	"sound square [duration] [freq] [channel]\n"
-	"    - generate squarewave for 'duration' ms with frequency 'freq'\n"
-	"      on left \"l\" or right \"r\" channel\n"
-	"pcm1772 reg val"
-);
-
-U_BOOT_CMD(
-	wav ,    3,    1,     cmd_wav,
-	"play wav file",
-	"[addr] [bytes]\n"
-	"    - play wav file at address 'addr' with length 'bytes'"
-);
-
-U_BOOT_CMD(
-	beep ,    2,    1,     cmd_beep,
-	"play short beep",
-	"[channel]\n"
-	"    - play short beep on \"l\"eft or \"r\"ight channel"
-);
-#endif /* CONFIG_STK52XX  || CONFIG_FO300 */
-
-#if defined(CONFIG_STK52XX)
-U_BOOT_CMD(
-	fkt ,	4,	1,	cmd_fkt,
-	"Function test routines",
-	"led number on/off\n"
-	"     - 'number's like printed on STK52XX board\n"
-	"fkt can\n"
-	"     - loopback plug for X83 required\n"
-	"fkt rs232 number\n"
-	"     - loopback plug(s) for X2 required"
-#ifndef CONFIG_TQM5200S
-	"\n"
-	"fkt backlight on/off\n"
-	"     - switch backlight on or off"
-#endif /* !CONFIG_TQM5200S */
-);
-#elif defined(CONFIG_FO300)
-U_BOOT_CMD(
-	fkt ,	3,	1,	cmd_fkt,
-	"Function test routines",
-	"fkt can\n"
-	"     - loopback plug for X16/X29 required\n"
-	"fkt rs232 number\n"
-	"     - loopback plug(s) for X21/X22 required"
-);
-#endif
-#endif
diff --git a/board/tqc/tqm5200/mt48lc16m16a2-75.h b/board/tqc/tqm5200/mt48lc16m16a2-75.h
deleted file mode 100644
index 3d9979664f..0000000000
--- a/board/tqc/tqm5200/mt48lc16m16a2-75.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	0		/* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x00CD0000
-/* #define SDRAM_MODE	0x008D0000 */ /* CAS latency 2 */
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xD2322800
-/* #define SDRAM_CONFIG1	0xD2222800 */ /* CAS latency 2 */
-/*#define SDRAM_CONFIG1	0xD7322800 */ /* SDRAM controller bug workaround */
-#define SDRAM_CONFIG2	0x8AD70000
-/*#define SDRAM_CONFIG2	0xDDD70000 */ /* SDRAM controller bug workaround */
diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c
deleted file mode 100644
index cb99afdb90..0000000000
--- a/board/tqc/tqm5200/tqm5200.c
+++ /dev/null
@@ -1,875 +0,0 @@
-/*
- * (C) Copyright 2003-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2004-2006
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <console.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <libfdt.h>
-#include <netdev.h>
-#include <video.h>
-
-#ifdef CONFIG_VIDEO_SM501
-#include <sm501.h>
-#endif
-
-#if defined(CONFIG_MPC5200_DDR)
-#include "mt46v16m16-75.h"
-#else
-#include "mt48lc16m16a2-75.h"
-#endif
-
-#ifdef CONFIG_OF_LIBFDT
-#include <fdt_support.h>
-#endif /* CONFIG_OF_LIBFDT */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_PS2MULT
-void ps2mult_early_init(void);
-#endif
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) && \
-    defined(CONFIG_VIDEO)
-/*
- * EDID block has been generated using Phoenix EDID Designer 1.3.
- * This tool creates a text file containing:
- *
- * EDID BYTES:
- *
- * 0x   00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
- *     ------------------------------------------------
- *     00 | 00 FF FF FF FF FF FF 00 04 21 00 00 00 00 00 00
- *     10 | 01 00 01 03 00 00 00 00 00 00 00 00 00 00 00 00
- *     20 | 00 00 00 21 00 00 01 01 01 01 01 01 01 01 01 01
- *     30 | 01 01 01 01 01 01 64 00 00 00 00 00 00 00 00 00
- *     40 | 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00
- *     50 | 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00
- *     60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10
- *     70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 17
- *
- * Then this data has been manually converted to the char
- * array below.
- */
-static unsigned char edid_buf[128] = {
-	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
-	0x04, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x01, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x01, 0x01,
-	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x64, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17,
-};
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
-		hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
-		hi_addr_bit;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set mode register: extended mode */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
-	__asm__ volatile ("sync");
-
-	/* set mode register: reset DLL */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
-	__asm__ volatile ("sync");
-#endif
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
-		hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
-		hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* set mode register */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-	__asm__ volatile ("sync");
-
-	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-	__asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced dram_init does NOT make real use
- *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- *	      is something else than 0x00000000.
- */
-
-int dram_init(void)
-{
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-	uint svr, pvr;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set tap delay */
-	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
-	__asm__ volatile ("sync");
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20)) {
-		dramsize = 0;
-	}
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
-			__builtin_ffs(dramsize >> 20) - 1;
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-	}
-
-	/* let SDRAM CS1 start right after CS0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
-
-	/* find RAM size using SDRAM CS1 only */
-	if (!dramsize)
-		sdram_start(0);
-	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
-	if (!dramsize) {
-		sdram_start(1);
-		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
-	}
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize2 = test1;
-	} else {
-		dramsize2 = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize2 < (1 << 20)) {
-		dramsize2 = 0;
-	}
-
-	/* set SDRAM CS1 size according to the amount of RAM found */
-	if (dramsize2 > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
-			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
-	if (dramsize >= 0x13) {
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	} else {
-		dramsize = 0;
-	}
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
-	if (dramsize2 >= 0x13) {
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	} else {
-		dramsize2 = 0;
-	}
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	svr = get_svr();
-	pvr = get_pvr();
-	if ((SVR_MJREV(svr) >= 2) &&
-	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
-
-		*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
-		__asm__ volatile ("sync");
-	}
-
-#if defined(CONFIG_TQM5200_B)
-	gd->ram_size = dramsize + dramsize2;
-#else
-	gd->ram_size = dramsize;
-#endif /* CONFIG_TQM5200_B */
-
-	return 0;
-}
-
-int checkboard (void)
-{
-#if defined(CONFIG_TQM5200S)
-# define MODULE_NAME	"TQM5200S"
-#else
-# define MODULE_NAME	"TQM5200"
-#endif
-
-#if defined(CONFIG_STK52XX)
-# define CARRIER_NAME	"STK52xx"
-#elif defined(CONFIG_CAM5200)
-# define CARRIER_NAME	"CAM5200"
-#elif defined(CONFIG_FO300)
-# define CARRIER_NAME	"FO300"
-#elif defined(CONFIG_CHARON)
-# define CARRIER_NAME	"CHARON"
-#else
-# error "UNKNOWN"
-#endif
-
-	puts (	"Board: " MODULE_NAME " (TQ-Components GmbH)\n"
-		"       on a " CARRIER_NAME " carrier board\n");
-
-	return 0;
-}
-
-#undef MODULE_NAME
-#undef CARRIER_NAME
-
-void flash_preinit(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write
-	 * access for detection process.
-	 * Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
-	 */
-	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-}
-
-
-#ifdef	CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET)
-
-#if defined (CONFIG_MINIFAP)
-#define SM501_POWER_MODE0_GATE		0x00000040UL
-#define SM501_POWER_MODE1_GATE		0x00000048UL
-#define POWER_MODE_GATE_GPIO_PWM_I2C	0x00000040UL
-#define SM501_GPIO_DATA_DIR_HIGH	0x0001000CUL
-#define SM501_GPIO_DATA_HIGH		0x00010004UL
-#define SM501_GPIO_51			0x00080000UL
-#endif /* CONFIG MINIFAP */
-
-void init_ide_reset (void)
-{
-	debug ("init_ide_reset\n");
-
-#if defined (CONFIG_MINIFAP)
-	/* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
-
-	/* enable GPIO control (in both power modes) */
-	*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
-		POWER_MODE_GATE_GPIO_PWM_I2C;
-	*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
-		POWER_MODE_GATE_GPIO_PWM_I2C;
-	/* configure GPIO51 as output */
-	*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
-		SM501_GPIO_51;
-#else
-	/* Configure PSC1_4 as GPIO output for ATA reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
-	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
-
-	/* by default the ATA reset is de-asserted */
-	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
-#endif
-}
-
-void ide_set_reset (int idereset)
-{
-	debug ("ide_reset(%d)\n", idereset);
-
-#if defined (CONFIG_MINIFAP)
-	if (idereset) {
-		*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
-			~SM501_GPIO_51;
-	} else {
-		*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
-			SM501_GPIO_51;
-	}
-#else
-	if (idereset) {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
-	} else {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
-	}
-#endif
-}
-#endif
-
-#ifdef CONFIG_POST
-/*
- * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
- * is left open, no keypress is detected.
- */
-int post_hotkeys_pressed(void)
-{
-#ifdef CONFIG_STK52XX
-	struct mpc5xxx_gpio *gpio;
-
-	gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
-
-	/*
-	 * Configure PSC6_0 through PSC6_3 as GPIO.
-	 */
-	gpio->port_config &= ~(0x00700000);
-
-	/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
-	gpio->simple_gpioe |= 0x20000000;
-
-	/* Configure GPIO_IRDA_1 as input */
-	gpio->simple_ddr &= ~(0x20000000);
-
-	return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
-#else
-	return 0;
-#endif
-}
-#endif
-
-#ifdef CONFIG_BOARD_EARLY_INIT_R
-int board_early_init_r (void)
-{
-
-	extern int usb_cpu_init(void);
-
-#ifdef CONFIG_PS2MULT
-	ps2mult_early_init();
-#endif /* CONFIG_PS2MULT */
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
-	/* Low level USB init, required for proper kernel operation */
-	usb_cpu_init();
-#endif
-
-	return (0);
-}
-#endif
-
-#ifdef CONFIG_FO300
-int silent_boot (void)
-{
-	vu_long timer3_status;
-
-	/* Configure GPT3 as GPIO input */
-	*(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004;
-
-	/* Read in TIMER_3 pin status */
-	timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
-
-#ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
-	/* Force silent console mode if S1 switch
-	 * is in closed position (TIMER_3 pin status is LOW). */
-	if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
-		return 1;
-#else
-	/* Force silent console mode if S1 switch
-	 * is in open position (TIMER_3 pin status is HIGH). */
-	if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
-		return 1;
-#endif
-
-	return 0;
-}
-
-int board_early_init_f (void)
-{
-	if (silent_boot())
-		gd->flags |= GD_FLG_SILENT;
-
-	return 0;
-}
-#endif	/* CONFIG_FO300 */
-
-#if defined(CONFIG_CHARON)
-#include <i2c.h>
-#include <asm/io.h>
-
-/* The TFP410 registers */
-#define TFP410_REG_VEN_ID_L 0x00
-#define TFP410_REG_VEN_ID_H 0x01
-#define TFP410_REG_DEV_ID_L 0x02
-#define TFP410_REG_DEV_ID_H 0x03
-#define TFP410_REG_REV_ID 0x04
-
-#define TFP410_REG_CTL_1_MODE 0x08
-#define TFP410_REG_CTL_2_MODE 0x09
-#define TFP410_REG_CTL_3_MODE 0x0A
-
-#define TFP410_REG_CFG 0x0B
-
-#define TFP410_REG_DE_DLY 0x32
-#define TFP410_REG_DE_CTL 0x33
-#define TFP410_REG_DE_TOP 0x34
-#define TFP410_REG_DE_CNT_L 0x36
-#define TFP410_REG_DE_CNT_H 0x37
-#define TFP410_REG_DE_LIN_L 0x38
-#define TFP410_REG_DE_LIN_H 0x39
-
-#define TFP410_REG_H_RES_L 0x3A
-#define TFP410_REG_H_RES_H 0x3B
-#define TFP410_REG_V_RES_L 0x3C
-#define TFP410_REG_V_RES_H 0x3D
-
-static int tfp410_read_reg(int reg, uchar *buf)
-{
-	puts("Error reading the chip.\n");
-	return -ENOSYS;
-}
-
-static int tfp410_write_reg(int reg, uchar buf)
-{
-	puts("Error writing the chip.\n");
-	return -ENOSYS;
-}
-
-typedef struct _tfp410_config {
-	int	reg;
-	uchar	val;
-}TFP410_CONFIG;
-
-static TFP410_CONFIG tfp410_configtbl[] = {
-	{TFP410_REG_CTL_1_MODE, 0x37},
-	{TFP410_REG_CTL_2_MODE, 0x20},
-	{TFP410_REG_CTL_3_MODE, 0x80},
-	{TFP410_REG_DE_DLY, 0x90},
-	{TFP410_REG_DE_CTL, 0x00},
-	{TFP410_REG_DE_TOP, 0x23},
-	{TFP410_REG_DE_CNT_H, 0x02},
-	{TFP410_REG_DE_CNT_L, 0x80},
-	{TFP410_REG_DE_LIN_H, 0x01},
-	{TFP410_REG_DE_LIN_L, 0xe0},
-	{-1, 0},
-};
-
-static int charon_last_stage_init(void)
-{
-	volatile struct mpc5xxx_lpb *lpb =
-		(struct mpc5xxx_lpb *) MPC5XXX_LPB;
-	uchar	buf;
-	int	i = 0;
-
-	/* check version */
-	if (tfp410_read_reg(TFP410_REG_DEV_ID_H, &buf) != 0)
-		return -1;
-	if (!(buf & 0x04))
-		return -1;
-	if (tfp410_read_reg(TFP410_REG_DEV_ID_L, &buf) != 0)
-		return -1;
-	if (!(buf & 0x10))
-		return -1;
-	/* OK, now init the chip */
-	while (tfp410_configtbl[i].reg != -1) {
-		int ret;
-
-		ret = tfp410_write_reg(tfp410_configtbl[i].reg,
-				tfp410_configtbl[i].val);
-		if (ret != 0)
-			return -1;
-		i++;
-	}
-	printf("TFP410 initialized.\n");
-
-	/* set deadcycle for cs3 to 0 */
-	setbits_be32(&lpb->cs_deadcycle, 0xffffcfff);
-	return 0;
-}
-#endif
-
-int last_stage_init (void)
-{
-	/*
-	 * auto scan for really existing devices and re-set chip select
-	 * configuration.
-	 */
-	u16 save, tmp;
-	int restore;
-
-	/*
-	 * Check for SRAM and SRAM size
-	 */
-
-	/* save original SRAM content  */
-	save = *(volatile u16 *)CONFIG_SYS_CS2_START;
-	restore = 1;
-
-	/* write test pattern to SRAM */
-	*(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5;
-	__asm__ volatile ("sync");
-	/*
-	 * Put a different pattern on the data lines: otherwise they may float
-	 * long enough to read back what we wrote.
-	 */
-	tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
-	if (tmp == 0xA5A5)
-		puts ("!! possible error in SRAM detection\n");
-
-	if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) {
-		/* no SRAM at all, disable cs */
-		*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
-		*(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
-		*(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
-		restore = 0;
-		__asm__ volatile ("sync");
-	} else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
-		/* make sure that we access a mirrored address */
-		*(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111;
-		__asm__ volatile ("sync");
-		if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
-			/* SRAM size = 512 kByte */
-			*(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
-								0x80000);
-			__asm__ volatile ("sync");
-			puts ("SRAM:  512 kB\n");
-		}
-		else
-			puts ("!! possible error in SRAM detection\n");
-	} else {
-		puts ("SRAM:  1 MB\n");
-	}
-	/* restore origianl SRAM content  */
-	if (restore) {
-		*(volatile u16 *)CONFIG_SYS_CS2_START = save;
-		__asm__ volatile ("sync");
-	}
-
-#ifndef CONFIG_TQM5200S	/* The TQM5200S has no SM501 grafic controller */
-	/*
-	 * Check for Grafic Controller
-	 */
-
-	/* save origianl FB content  */
-	save = *(volatile u16 *)CONFIG_SYS_CS1_START;
-	restore = 1;
-
-	/* write test pattern to FB memory */
-	*(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
-	__asm__ volatile ("sync");
-	/*
-	 * Put a different pattern on the data lines: otherwise they may float
-	 * long enough to read back what we wrote.
-	 */
-	tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
-	if (tmp == 0xA5A5)
-		puts ("!! possible error in grafic controller detection\n");
-
-	if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
-		/* no grafic controller at all, disable cs */
-		*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
-		*(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
-		*(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
-		restore = 0;
-		__asm__ volatile ("sync");
-	} else {
-		puts ("VGA:   SMI501 (Voyager) with 8 MB\n");
-	}
-	/* restore origianl FB content  */
-	if (restore) {
-		*(volatile u16 *)CONFIG_SYS_CS1_START = save;
-		__asm__ volatile ("sync");
-	}
-
-#ifdef CONFIG_FO300
-	if (silent_boot()) {
-		setenv("bootdelay", "0");
-		disable_ctrlc(1);
-	}
-#endif
-#endif /* !CONFIG_TQM5200S */
-
-#if defined(CONFIG_CHARON)
-	charon_last_stage_init();
-#endif
-	return 0;
-}
-
-#ifdef CONFIG_VIDEO_SM501
-
-#ifdef CONFIG_FO300
-#define DISPLAY_WIDTH   800
-#else
-#define DISPLAY_WIDTH   640
-#endif
-#define DISPLAY_HEIGHT  480
-
-#ifdef CONFIG_VIDEO_SM501_8BPP
-#error CONFIG_VIDEO_SM501_8BPP not supported.
-#endif /* CONFIG_VIDEO_SM501_8BPP */
-
-#ifdef CONFIG_VIDEO_SM501_16BPP
-#error CONFIG_VIDEO_SM501_16BPP not supported.
-#endif /* CONFIG_VIDEO_SM501_16BPP */
-#ifdef CONFIG_VIDEO_SM501_32BPP
-static const SMI_REGS init_regs [] =
-{
-#if 0 /* CRT only */
-	{0x00004, 0x0},
-	{0x00048, 0x00021807},
-	{0x0004C, 0x10090a01},
-	{0x00054, 0x1},
-	{0x00040, 0x00021807},
-	{0x00044, 0x10090a01},
-	{0x00054, 0x0},
-	{0x80200, 0x00010000},
-	{0x80204, 0x0},
-	{0x80208, 0x0A000A00},
-	{0x8020C, 0x02fa027f},
-	{0x80210, 0x004a028b},
-	{0x80214, 0x020c01df},
-	{0x80218, 0x000201e9},
-	{0x80200, 0x00013306},
-#else  /* panel + CRT */
-#ifdef CONFIG_FO300
-	{0x00004, 0x0},
-	{0x00048, 0x00021807},
-	{0x0004C, 0x301a0a01},
-	{0x00054, 0x1},
-	{0x00040, 0x00021807},
-	{0x00044, 0x091a0a01},
-	{0x00054, 0x0},
-	{0x80000, 0x0f013106},
-	{0x80004, 0xc428bb17},
-	{0x8000C, 0x00000000},
-	{0x80010, 0x0C800C80},
-	{0x80014, 0x03200000},
-	{0x80018, 0x01e00000},
-	{0x8001C, 0x00000000},
-	{0x80020, 0x01e00320},
-	{0x80024, 0x042a031f},
-	{0x80028, 0x0086034a},
-	{0x8002C, 0x020c01df},
-	{0x80030, 0x000201ea},
-	{0x80200, 0x00010000},
-#else
-	{0x00004, 0x0},
-	{0x00048, 0x00021807},
-	{0x0004C, 0x091a0a01},
-	{0x00054, 0x1},
-	{0x00040, 0x00021807},
-	{0x00044, 0x091a0a01},
-	{0x00054, 0x0},
-	{0x80000, 0x0f013106},
-	{0x80004, 0xc428bb17},
-	{0x8000C, 0x00000000},
-	{0x80010, 0x0a000a00},
-	{0x80014, 0x02800000},
-	{0x80018, 0x01e00000},
-	{0x8001C, 0x00000000},
-	{0x80020, 0x01e00280},
-	{0x80024, 0x02fa027f},
-	{0x80028, 0x004a028b},
-	{0x8002C, 0x020c01df},
-	{0x80030, 0x000201e9},
-	{0x80200, 0x00010000},
-#endif /* #ifdef CONFIG_FO300 */
-#endif
-	{0, 0}
-};
-#endif /* CONFIG_VIDEO_SM501_32BPP */
-
-#ifdef CONFIG_CONSOLE_EXTRA_INFO
-/*
- * Return text to be printed besides the logo.
- */
-void video_get_info_str (int line_number, char *info)
-{
-	if (line_number == 1) {
-	strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
-#if defined (CONFIG_CHARON) || defined (CONFIG_FO300) || \
-	defined(CONFIG_STK52XX)
-	} else if (line_number == 2) {
-#if defined (CONFIG_CHARON)
-		strcpy (info, "        on a CHARON carrier board");
-#endif
-#if defined (CONFIG_STK52XX)
-		strcpy (info, "        on a STK52xx carrier board");
-#endif
-#if defined (CONFIG_FO300)
-		strcpy (info, "        on a FO300 carrier board");
-#endif
-#endif
-	}
-	else {
-		info [0] = '\0';
-	}
-}
-#endif
-
-/*
- * Returns SM501 register base address. First thing called in the
- * driver. Checks if SM501 is physically present.
- */
-unsigned int board_video_init (void)
-{
-	u16 save, tmp;
-	int restore, ret;
-
-	/*
-	 * Check for Grafic Controller
-	 */
-
-	/* save origianl FB content  */
-	save = *(volatile u16 *)CONFIG_SYS_CS1_START;
-	restore = 1;
-
-	/* write test pattern to FB memory */
-	*(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
-	__asm__ volatile ("sync");
-	/*
-	 * Put a different pattern on the data lines: otherwise they may float
-	 * long enough to read back what we wrote.
-	 */
-	tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
-	if (tmp == 0xA5A5)
-		puts ("!! possible error in grafic controller detection\n");
-
-	if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
-		/* no grafic controller found */
-		restore = 0;
-		ret = 0;
-	} else {
-		ret = SM501_MMIO_BASE;
-	}
-
-	if (restore) {
-		*(volatile u16 *)CONFIG_SYS_CS1_START = save;
-		__asm__ volatile ("sync");
-	}
-	return ret;
-}
-
-/*
- * Returns SM501 framebuffer address
- */
-unsigned int board_video_get_fb (void)
-{
-	return SM501_FB_BASE;
-}
-
-/*
- * Called after initializing the SM501 and before clearing the screen.
- */
-void board_validate_screen (unsigned int base)
-{
-}
-
-/*
- * Return a pointer to the initialization sequence.
- */
-const SMI_REGS *board_get_regs (void)
-{
-	return init_regs;
-}
-
-int board_get_width (void)
-{
-	return DISPLAY_WIDTH;
-}
-
-int board_get_height (void)
-{
-	return DISPLAY_HEIGHT;
-}
-
-#endif /* CONFIG_VIDEO_SM501 */
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-#if defined(CONFIG_VIDEO)
-	fdt_add_edid(blob, "smi,sm501", edid_buf);
-#endif
-
-	return 0;
-}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
-
-#if defined(CONFIG_RESET_PHY_R)
-#include <miiphy.h>
-
-void reset_phy(void)
-{
-	/* init Micrel KSZ8993 PHY */
-	miiphy_write("FEC", CONFIG_PHY_ADDR, 0x01, 0x09);
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
-	cpu_eth_init(bis); /* Built in FEC comes first */
-	return pci_eth_init(bis);
-}
diff --git a/board/v38b/Kconfig b/board/v38b/Kconfig
deleted file mode 100644
index 653bfc1c3b..0000000000
--- a/board/v38b/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_V38B
-
-config SYS_BOARD
-	default "v38b"
-
-config SYS_CONFIG_NAME
-	default "v38b"
-
-endif
diff --git a/board/v38b/MAINTAINERS b/board/v38b/MAINTAINERS
deleted file mode 100644
index d1a6ae6b2f..0000000000
--- a/board/v38b/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-V38B BOARD
-#M:	-
-S:	Maintained
-F:	board/v38b/
-F:	include/configs/v38b.h
-F:	configs/v38b_defconfig
diff --git a/board/v38b/Makefile b/board/v38b/Makefile
deleted file mode 100644
index a20a5ef0e9..0000000000
--- a/board/v38b/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= v38b.o ethaddr.o
diff --git a/board/v38b/ethaddr.c b/board/v38b/ethaddr.c
deleted file mode 100644
index 982998fadc..0000000000
--- a/board/v38b/ethaddr.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-
-/* For the V38B board the pin is GPIO_PSC_6 */
-#define GPIO_PIN	GPIO_PSC6_0
-
-#define NO_ERROR	0
-#define ERR_NO_NUMBER	1
-#define ERR_BAD_NUMBER	2
-
-static int is_high(void);
-static int check_device(void);
-static void io_out(int value);
-static void io_input(void);
-static void io_output(void);
-static void init_gpio(void);
-static void read_byte(unsigned char *data);
-static void write_byte(unsigned char command);
-
-void read_2501_memory(unsigned char *psernum, unsigned char *perr);
-void board_get_enetaddr(uchar *enetaddr);
-
-
-static int is_high()
-{
-	return (*((vu_long *) MPC5XXX_WU_GPIO_DATA_I) & GPIO_PIN);
-}
-
-static void io_out(int value)
-{
-	if (value)
-		*((vu_long *) MPC5XXX_WU_GPIO_DATA_O) |= GPIO_PIN;
-	else
-		*((vu_long *) MPC5XXX_WU_GPIO_DATA_O) &= ~GPIO_PIN;
-}
-
-static void io_input()
-{
-	*((vu_long *) MPC5XXX_WU_GPIO_DIR) &= ~GPIO_PIN;
-	udelay(3);	/* allow input to settle */
-}
-
-static void io_output()
-{
-	*((vu_long *) MPC5XXX_WU_GPIO_DIR) |= GPIO_PIN;
-}
-
-static void init_gpio()
-{
-	*((vu_long *) MPC5XXX_WU_GPIO_ENABLE) |= GPIO_PIN;	/* Enable appropriate pin */
-}
-
-void read_2501_memory(unsigned char *psernum, unsigned char *perr)
-{
-#define NBYTES 28
-	unsigned char crcval, i;
-	unsigned char buf[NBYTES];
-
-	*perr = 0;
-	crcval = 0;
-
-	for (i = 0; i < NBYTES; i++)
-		buf[i] = 0;
-
-	if (!check_device())
-		*perr = ERR_NO_NUMBER;
-	else {
-		*perr = NO_ERROR;
-		write_byte(0xCC);		/* skip ROM (0xCC) */
-		write_byte(0xF0);		/* Read memory command 0xF0 */
-		write_byte(0x00);		/* Address TA1=0, TA2=0 */
-		write_byte(0x00);
-		read_byte(&crcval);		/* Read CRC of address and command */
-
-		for (i = 0; i < NBYTES; i++)
-			read_byte(&buf[i]);
-	}
-	if (strncmp((const char *) &buf[11], "MAREL IEEE 802.3", 16)) {
-		*perr = ERR_BAD_NUMBER;
-		psernum[0] = 0x00;
-		psernum[1] = 0xE0;
-		psernum[2] = 0xEE;
-		psernum[3] = 0xFF;
-		psernum[4] = 0xFF;
-		psernum[5] = 0xFF;
-	} else {
-		psernum[0] = 0x00;
-		psernum[1] = 0xE0;
-		psernum[2] = 0xEE;
-		psernum[3] = buf[7];
-		psernum[4] = buf[6];
-		psernum[5] = buf[5];
-	}
-}
-
-static int check_device()
-{
-	int found;
-
-	io_output();
-	io_out(0);
-	udelay(500);  /* must be at least 480 us low pulse */
-
-	io_input();
-	udelay(60);
-
-	found = (is_high() == 0) ? 1 : 0;
-	udelay(500);  /* must be at least 480 us low pulse */
-
-	return found;
-}
-
-static void write_byte(unsigned char command)
-{
-	char i;
-
-	for (i = 0; i < 8; i++) {
-		/* 1 us to 15 us low pulse starts bit slot */
-		/* Start with high pulse for 3 us */
-		io_input();
-		udelay(3);
-
-		io_out(0);
-		io_output();
-		udelay(3);
-
-		if (command & 0x01) {
-			/* 60 us high for 1-bit */
-			io_input();
-			udelay(60);
-		} else
-			/* 60 us low for 0-bit */
-			udelay(60);
-		/*  Leave pin as input */
-		io_input();
-
-		command = command >> 1;
-	}
-}
-
-static void read_byte(unsigned char *data)
-{
-	unsigned char i, rdat = 0;
-
-	for (i = 0; i < 8; i++) {
-		/* read one bit from one-wire device */
-
-		/* 1 - 15 us low starts bit slot */
-		io_out(0);
-		io_output();
-		udelay(0);
-
-		/* allow line to be pulled high */
-		io_input();
-
-		/* delay 10 us */
-		udelay(10);
-
-		/* now sample input status */
-		if (is_high())
-			rdat = (rdat >> 1) | 0x80;
-		else
-			rdat = rdat >> 1;
-
-		udelay(60);	/* at least 60 us */
-	}
-	/* copy the return value */
-	*data = rdat;
-}
-
-void board_get_enetaddr(uchar *enetaddr)
-{
-	unsigned char sn[6], err = NO_ERROR;
-
-	init_gpio();
-
-	read_2501_memory(sn, &err);
-
-	if (err == NO_ERROR) {
-		sprintf((char *)enetaddr, "%02x:%02x:%02x:%02x:%02x:%02x",
-				sn[0], sn[1], sn[2], sn[3], sn[4], sn[5]);
-		printf("MAC address: %s\n", enetaddr);
-		setenv("ethaddr", (char *)enetaddr);
-	} else {
-		sprintf((char *)enetaddr, "00:01:02:03:04:05");
-		printf("Error reading MAC address.\n");
-		printf("Setting default to %s\n", enetaddr);
-		setenv("ethaddr", (char *)enetaddr);
-	}
-}
diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c
deleted file mode 100644
index e680b7b8ff..0000000000
--- a/board/v38b/v38b.c
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- * (C) Copyright 2003-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <net.h>
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start(int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set mode register: extended mode */
-	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
-	__asm__ volatile ("sync");
-
-	/* set mode register: reset DLL */
-	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
-	__asm__ volatile ("sync");
-#endif /* SDRAM_DDR */
-
-	/* precharge all banks */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* auto refresh */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* set mode register */
-	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-	__asm__ volatile ("sync");
-
-	/* normal operation */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-	__asm__ volatile ("sync");
-}
-#endif /* !CONFIG_SYS_RAMBOOT */
-
-
-int dram_init(void)
-{
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-	uint svr, pvr;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e;	/* 2G at 0x0 */
-	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set tap delay */
-	*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
-	__asm__ volatile ("sync");
-#endif /* SDRAM_DDR */
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else
-		dramsize = test2;
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0)
-		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
-	else
-		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-
-	/* let SDRAM CS1 start right after CS0 */
-	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
-
-	/* find RAM size using SDRAM CS1 only */
-	if (!dramsize)
-		sdram_start(0);
-	test2 = test1 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	if (!dramsize) {
-		sdram_start(1);
-		test2 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	}
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize2 = test1;
-	} else
-		dramsize2 = test2;
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize2 < (1 << 20))
-		dramsize2 = 0;
-
-	/* set SDRAM CS1 size according to the amount of RAM found */
-	if (dramsize2 > 0)
-		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize
-			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
-	else
-		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = *(vu_long *) MPC5XXX_SDRAM_CS0CFG & 0xFF;
-	if (dramsize >= 0x13)
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	else
-		dramsize = 0;
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = *(vu_long *) MPC5XXX_SDRAM_CS1CFG & 0xFF;
-	if (dramsize2 >= 0x13)
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	else
-		dramsize2 = 0;
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	svr = get_svr();
-	pvr = get_pvr();
-	if ((SVR_MJREV(svr) >= 2) &&
-		(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
-
-		*(vu_long *) MPC5XXX_SDRAM_SDELAY = 0x04;
-		__asm__ volatile ("sync");
-	}
-
-	gd->ram_size = dramsize + dramsize2;
-
-	return 0;
-}
-
-
-int checkboard (void)
-{
-	puts("Board: MarelV38B\n");
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-#ifdef CONFIG_HW_WATCHDOG
-	/*
-	 * Enable and configure the direction (output) of PSC3_9 - watchdog
-	 * reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's
-	 * Manual.
-	 */
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
-	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
-#endif /* CONFIG_HW_WATCHDOG */
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write access for the
-	 * detection process.  Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
-	 */
-	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-
-	/*
-	 * Enable GPIO_WKUP_7 to "read the status of the actual power
-	 * situation". Default direction is input, so no need to set it
-	 * explicitly.
-	 */
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WKUP_7;
-	return 0;
-}
-
-extern void board_get_enetaddr(uchar *enetaddr);
-int misc_init_r(void)
-{
-	uchar enetaddr[6];
-
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
-		board_get_enetaddr(enetaddr);
-		eth_setenv_enetaddr("ethaddr", enetaddr);
-	}
-
-	return 0;
-}
-
-#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET)
-void init_ide_reset(void)
-{
-	debug("init_ide_reset\n");
-
-	/* Configure PSC1_4 as GPIO output for ATA reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
-	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
-	/* Deassert reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
-}
-
-
-void ide_set_reset(int idereset)
-{
-	debug("ide_reset(%d)\n", idereset);
-
-	if (idereset) {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
-		/* Make a delay. MPC5200 spec says 25 usec min */
-		udelay(500000);
-	} else
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
-}
-#endif
-
-
-#ifdef CONFIG_HW_WATCHDOG
-void hw_watchdog_reset(void)
-{
-	/*
-	 * MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog
-	 * we need a positive or negative transition on WDI i.e., our PSC3_9.
-	 */
-	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O ^= GPIO_PSC3_9;
-}
-#endif /* CONFIG_HW_WATCHDOG */
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 412bf24fb2..07b0e3b228 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1232,7 +1232,7 @@ config CMD_DIAG
 
 config CMD_IRQ
 	bool "irq - Show information about interrupts"
-	depends on !ARM && !MIPS && !SH && !MPC512X
+	depends on !ARM && !MIPS && !SH
 	help
 	  This enables two commands:
 
diff --git a/cmd/reginfo.c b/cmd/reginfo.c
index e09b24c901..4dccf24389 100644
--- a/cmd/reginfo.c
+++ b/cmd/reginfo.c
@@ -11,8 +11,6 @@
 #include <mpc8xx.h>
 #elif defined (CONFIG_4xx)
 extern void ppc4xx_reginfo(void);
-#elif defined (CONFIG_MPC5200)
-#include <mpc5xxx.h>
 #elif defined (CONFIG_MPC86xx)
 extern void mpc86xx_reginfo(void);
 #elif defined(CONFIG_MPC85xx)
@@ -77,59 +75,6 @@ static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc,
 
 #elif defined (CONFIG_4xx)
 	ppc4xx_reginfo();
-#elif defined(CONFIG_MPC5200)
-	puts ("\nMPC5200 registers\n");
-	printf ("MBAR=%08x\n", CONFIG_SYS_MBAR);
-	puts ("Memory map registers\n");
-	printf ("\tCS0: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
-		*(volatile ulong*)MPC5XXX_CS0_START,
-		*(volatile ulong*)MPC5XXX_CS0_STOP,
-		*(volatile ulong*)MPC5XXX_CS0_CFG,
-		(*(volatile ulong*)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0);
-	printf ("\tCS1: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
-		*(volatile ulong*)MPC5XXX_CS1_START,
-		*(volatile ulong*)MPC5XXX_CS1_STOP,
-		*(volatile ulong*)MPC5XXX_CS1_CFG,
-		(*(volatile ulong*)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0);
-	printf ("\tCS2: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
-		*(volatile ulong*)MPC5XXX_CS2_START,
-		*(volatile ulong*)MPC5XXX_CS2_STOP,
-		*(volatile ulong*)MPC5XXX_CS2_CFG,
-		(*(volatile ulong*)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0);
-	printf ("\tCS3: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
-		*(volatile ulong*)MPC5XXX_CS3_START,
-		*(volatile ulong*)MPC5XXX_CS3_STOP,
-		*(volatile ulong*)MPC5XXX_CS3_CFG,
-		(*(volatile ulong*)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0);
-	printf ("\tCS4: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
-		*(volatile ulong*)MPC5XXX_CS4_START,
-		*(volatile ulong*)MPC5XXX_CS4_STOP,
-		*(volatile ulong*)MPC5XXX_CS4_CFG,
-		(*(volatile ulong*)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0);
-	printf ("\tCS5: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
-		*(volatile ulong*)MPC5XXX_CS5_START,
-		*(volatile ulong*)MPC5XXX_CS5_STOP,
-		*(volatile ulong*)MPC5XXX_CS5_CFG,
-		(*(volatile ulong*)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0);
-	printf ("\tCS6: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
-		*(volatile ulong*)MPC5XXX_CS6_START,
-		*(volatile ulong*)MPC5XXX_CS6_STOP,
-		*(volatile ulong*)MPC5XXX_CS6_CFG,
-		(*(volatile ulong*)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0);
-	printf ("\tCS7: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
-		*(volatile ulong*)MPC5XXX_CS7_START,
-		*(volatile ulong*)MPC5XXX_CS7_STOP,
-		*(volatile ulong*)MPC5XXX_CS7_CFG,
-		(*(volatile ulong*)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0);
-	printf ("\tBOOTCS: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
-		*(volatile ulong*)MPC5XXX_BOOTCS_START,
-		*(volatile ulong*)MPC5XXX_BOOTCS_STOP,
-		*(volatile ulong*)MPC5XXX_BOOTCS_CFG,
-		(*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0);
-	printf ("\tSDRAMCS0: %08lX\n",
-		*(volatile ulong*)MPC5XXX_SDRAM_CS0CFG);
-	printf ("\tSDRAMCS1: %08lX\n",
-		*(volatile ulong*)MPC5XXX_SDRAM_CS1CFG);
 #elif defined(CONFIG_MPC86xx)
 	mpc86xx_reginfo();
 
diff --git a/common/Kconfig b/common/Kconfig
index c49199bb1a..27dde11b14 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -464,7 +464,7 @@ config BOARD_LATE_INIT
 
 config DISPLAY_CPUINFO
 	bool "Display information about the CPU during start up"
-	default y if ARM || NIOS2 || X86 || XTENSA || MPC5xxx
+	default y if ARM || NIOS2 || X86 || XTENSA
 	help
 	  Display information about the CPU that U-Boot is running on
 	  when U-Boot starts up. The function print_cpuinfo() is called
diff --git a/common/board_f.c b/common/board_f.c
index 85a9fb7f9d..d5afc87839 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -551,7 +551,7 @@ static int setup_board_part1(void)
 		defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 	bd->bi_immr_base = CONFIG_SYS_IMMR;	/* base  of IMMR register     */
 #endif
-#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K)
+#if defined(CONFIG_M68K)
 	bd->bi_mbar_base = CONFIG_SYS_MBAR;	/* base of internal registers */
 #endif
 #if defined(CONFIG_MPC83xx)
@@ -575,13 +575,6 @@ static int setup_board_part2(void)
 	bd->bi_sccfreq = gd->arch.scc_clk;
 	bd->bi_vco = gd->arch.vco_out;
 #endif /* CONFIG_CPM2 */
-#if defined(CONFIG_MPC512X)
-	bd->bi_ipsfreq = gd->arch.ips_clk;
-#endif /* CONFIG_MPC512X */
-#if defined(CONFIG_MPC5xxx)
-	bd->bi_ipbfreq = gd->arch.ipb_clk;
-	bd->bi_pcifreq = gd->pci_clk;
-#endif /* CONFIG_MPC5xxx */
 #if defined(CONFIG_M68K) && defined(CONFIG_PCI)
 	bd->bi_pcifreq = gd->pci_clk;
 #endif
diff --git a/configs/MiniFAP_defconfig b/configs/MiniFAP_defconfig
deleted file mode 100644
index b9cbafc887..0000000000
--- a/configs/MiniFAP_defconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-CONFIG_PPC=y
-CONFIG_VIDEO=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TQM5200=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="MINIFAP"
-CONFIG_BOOTDELAY=5
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_LOOPW=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_BSP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_DIAG=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_CONSOLE_EXTRA_INFO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/O2D300_defconfig b/configs/O2D300_defconfig
deleted file mode 100644
index c0e9541b87..0000000000
--- a/configs/O2D300_defconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_O2D300=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_FAT=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_OF_LIBFDT=y
diff --git a/configs/O2DNT2_RAMBOOT_defconfig b/configs/O2DNT2_RAMBOOT_defconfig
deleted file mode 100644
index 8cff44cf36..0000000000
--- a/configs/O2DNT2_RAMBOOT_defconfig
+++ /dev/null
@@ -1,21 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_O2DNT2=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000"
-CONFIG_BOOTDELAY=5
-CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press password to stop\n"
-CONFIG_AUTOBOOT_STOP_STR="++++++++++"
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_FAT=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_OF_LIBFDT=y
diff --git a/configs/O2DNT2_defconfig b/configs/O2DNT2_defconfig
deleted file mode 100644
index f29abb83bc..0000000000
--- a/configs/O2DNT2_defconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_O2DNT2=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press password to stop\n"
-CONFIG_AUTOBOOT_STOP_STR="++++++++++"
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_FAT=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_OF_LIBFDT=y
diff --git a/configs/O2D_defconfig b/configs/O2D_defconfig
deleted file mode 100644
index 534cfe12e2..0000000000
--- a/configs/O2D_defconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_O2D=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_FAT=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_OF_LIBFDT=y
diff --git a/configs/O2I_defconfig b/configs/O2I_defconfig
deleted file mode 100644
index acf42abe29..0000000000
--- a/configs/O2I_defconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_O2I=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_FAT=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_OF_LIBFDT=y
diff --git a/configs/O2MNT_O2M110_defconfig b/configs/O2MNT_O2M110_defconfig
deleted file mode 100644
index de647c76b9..0000000000
--- a/configs/O2MNT_O2M110_defconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_O2MNT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M110\""
-CONFIG_BOOTDELAY=5
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_FAT=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_OF_LIBFDT=y
diff --git a/configs/O2MNT_O2M112_defconfig b/configs/O2MNT_O2M112_defconfig
deleted file mode 100644
index b243e9cc0e..0000000000
--- a/configs/O2MNT_O2M112_defconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_O2MNT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M112\""
-CONFIG_BOOTDELAY=5
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_FAT=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_OF_LIBFDT=y
diff --git a/configs/O2MNT_O2M113_defconfig b/configs/O2MNT_O2M113_defconfig
deleted file mode 100644
index 1584058289..0000000000
--- a/configs/O2MNT_O2M113_defconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_O2MNT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M113\""
-CONFIG_BOOTDELAY=5
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_FAT=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_OF_LIBFDT=y
diff --git a/configs/O2MNT_defconfig b/configs/O2MNT_defconfig
deleted file mode 100644
index 20bd31466e..0000000000
--- a/configs/O2MNT_defconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_O2MNT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_FAT=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_OF_LIBFDT=y
diff --git a/configs/O3DNT_defconfig b/configs/O3DNT_defconfig
deleted file mode 100644
index ea769e7edc..0000000000
--- a/configs/O3DNT_defconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_O3DNT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BSP=y
-CONFIG_CMD_FAT=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200S_HIGHBOOT_defconfig b/configs/TQM5200S_HIGHBOOT_defconfig
deleted file mode 100644
index 5e6f9c951f..0000000000
--- a/configs/TQM5200S_HIGHBOOT_defconfig
+++ /dev/null
@@ -1,28 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TQM5200=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000"
-CONFIG_BOOTDELAY=5
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_LOOPW=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_BSP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_DIAG=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200S_defconfig b/configs/TQM5200S_defconfig
deleted file mode 100644
index d0c352faa1..0000000000
--- a/configs/TQM5200S_defconfig
+++ /dev/null
@@ -1,28 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TQM5200=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S"
-CONFIG_BOOTDELAY=5
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_LOOPW=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_BSP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_DIAG=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200_B_HIGHBOOT_defconfig b/configs/TQM5200_B_HIGHBOOT_defconfig
deleted file mode 100644
index ed74408b98..0000000000
--- a/configs/TQM5200_B_HIGHBOOT_defconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-CONFIG_PPC=y
-CONFIG_VIDEO=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TQM5200=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,SYS_TEXT_BASE=0xFFF00000"
-CONFIG_BOOTDELAY=5
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_LOOPW=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_BSP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_DIAG=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_CONSOLE_EXTRA_INFO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200_B_defconfig b/configs/TQM5200_B_defconfig
deleted file mode 100644
index cc9968cacb..0000000000
--- a/configs/TQM5200_B_defconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-CONFIG_PPC=y
-CONFIG_VIDEO=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TQM5200=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B"
-CONFIG_BOOTDELAY=5
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_LOOPW=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_BSP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_DIAG=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_CONSOLE_EXTRA_INFO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200_STK100_defconfig b/configs/TQM5200_STK100_defconfig
deleted file mode 100644
index 35d486033b..0000000000
--- a/configs/TQM5200_STK100_defconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-CONFIG_PPC=y
-CONFIG_VIDEO=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TQM5200=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="STK52XX_REV100"
-CONFIG_BOOTDELAY=5
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_LOOPW=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_BSP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_DIAG=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_CONSOLE_EXTRA_INFO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200_defconfig b/configs/TQM5200_defconfig
deleted file mode 100644
index 783c39a052..0000000000
--- a/configs/TQM5200_defconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-CONFIG_PPC=y
-CONFIG_VIDEO=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TQM5200=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_LOOPW=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_BSP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_DIAG=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_CONSOLE_EXTRA_INFO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/a3m071_defconfig b/configs/a3m071_defconfig
deleted file mode 100644
index a461b809c6..0000000000
--- a/configs/a3m071_defconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_A3M071=y
-CONFIG_FIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SPL=y
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_OS_BASE=0xfc200000
-CONFIG_HUSH_PARSER=y
-CONFIG_LOOPW=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_LINK_LOCAL=y
-CONFIG_CMD_BSP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_UBI=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_LIB_RAND=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/a4m072_defconfig b/configs/a4m072_defconfig
deleted file mode 100644
index 4fbffb6edc..0000000000
--- a/configs/a4m072_defconfig
+++ /dev/null
@@ -1,25 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_A4M072=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SILENT_CONSOLE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="asdfg"
-CONFIG_CMD_IDE=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DISPLAY=y
-CONFIG_CMD_FAT=y
-CONFIG_MAC_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_BAUDRATE=9600
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/a4m2k_defconfig b/configs/a4m2k_defconfig
deleted file mode 100644
index 3100da6c6e..0000000000
--- a/configs/a4m2k_defconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_A3M071=y
-CONFIG_FIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="A4M2K"
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SPL=y
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_OS_BASE=0xfc200000
-CONFIG_HUSH_PARSER=y
-CONFIG_LOOPW=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_LINK_LOCAL=y
-CONFIG_CMD_BSP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_UBI=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_LIB_RAND=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/ac14xx_defconfig b/configs/ac14xx_defconfig
deleted file mode 100644
index 6855331860..0000000000
--- a/configs/ac14xx_defconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC512X=y
-CONFIG_TARGET_AC14XX=y
-CONFIG_FIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_PROMPT="ac14xx> "
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_JFFS2=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_OF_LIBFDT=y
diff --git a/configs/aria_defconfig b/configs/aria_defconfig
deleted file mode 100644
index 0613dd16fb..0000000000
--- a/configs/aria_defconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC512X=y
-CONFIG_TARGET_ARIA=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_JFFS2=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_OF_LIBFDT=y
diff --git a/configs/cam5200_defconfig b/configs/cam5200_defconfig
deleted file mode 100644
index d8a419cda2..0000000000
--- a/configs/cam5200_defconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TQM5200=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B"
-CONFIG_BOOTDELAY=5
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_LOOPW=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_BSP=y
-CONFIG_CMD_JFFS2=y
-CONFIG_MAC_PARTITION=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_OF_LIBFDT=y
diff --git a/configs/cam5200_niosflash_defconfig b/configs/cam5200_niosflash_defconfig
deleted file mode 100644
index d7577a44ff..0000000000
--- a/configs/cam5200_niosflash_defconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TQM5200=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH"
-CONFIG_BOOTDELAY=5
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_LOOPW=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_BSP=y
-CONFIG_CMD_JFFS2=y
-CONFIG_MAC_PARTITION=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_OF_LIBFDT=y
diff --git a/configs/canmb_defconfig b/configs/canmb_defconfig
deleted file mode 100644
index 87eb205d0c..0000000000
--- a/configs/canmb_defconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_CMD_IMMAP=y
-CONFIG_TARGET_CANMB=y
-CONFIG_BOOTDELAY=5
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DATE=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
diff --git a/configs/charon_defconfig b/configs/charon_defconfig
deleted file mode 100644
index 2e4ad658e0..0000000000
--- a/configs/charon_defconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-CONFIG_PPC=y
-CONFIG_VIDEO=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_CHARON=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_LOOPW=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_BSP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_DIAG=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_CONSOLE_EXTRA_INFO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/cm5200_defconfig b/configs/cm5200_defconfig
deleted file mode 100644
index 860d23e553..0000000000
--- a/configs/cm5200_defconfig
+++ /dev/null
@@ -1,28 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_CM5200=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_ASKENV=y
-CONFIG_LOOPW=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_BSP=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_DIAG=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_BAUDRATE=57600
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/digsy_mtc_RAMBOOT_defconfig b/configs/digsy_mtc_RAMBOOT_defconfig
deleted file mode 100644
index cda75d6e03..0000000000
--- a/configs/digsy_mtc_RAMBOOT_defconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-CONFIG_PPC=y
-CONFIG_VIDEO=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_DIGSY_MTC=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000"
-CONFIG_BOOTDELAY=1
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_LOOPW=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_DIAG=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/digsy_mtc_defconfig b/configs/digsy_mtc_defconfig
deleted file mode 100644
index da9cec81a3..0000000000
--- a/configs/digsy_mtc_defconfig
+++ /dev/null
@@ -1,29 +0,0 @@
-CONFIG_PPC=y
-CONFIG_VIDEO=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_DIGSY_MTC=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=1
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR=" "
-CONFIG_LOOPW=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_DIAG=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/digsy_mtc_rev5_RAMBOOT_defconfig b/configs/digsy_mtc_rev5_RAMBOOT_defconfig
deleted file mode 100644
index 1bba630083..0000000000
--- a/configs/digsy_mtc_rev5_RAMBOOT_defconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-CONFIG_PPC=y
-CONFIG_VIDEO=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_DIGSY_MTC=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000,DIGSY_REV5"
-CONFIG_BOOTDELAY=1
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_LOOPW=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_DIAG=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/digsy_mtc_rev5_defconfig b/configs/digsy_mtc_rev5_defconfig
deleted file mode 100644
index 3491fdd5f1..0000000000
--- a/configs/digsy_mtc_rev5_defconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-CONFIG_PPC=y
-CONFIG_VIDEO=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_DIGSY_MTC=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="DIGSY_REV5"
-CONFIG_BOOTDELAY=1
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_LOOPW=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_DIAG=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/fo300_defconfig b/configs/fo300_defconfig
deleted file mode 100644
index 24470f311a..0000000000
--- a/configs/fo300_defconfig
+++ /dev/null
@@ -1,35 +0,0 @@
-CONFIG_PPC=y
-CONFIG_VIDEO=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TQM5200=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="FO300"
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_LOOPW=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_BSP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_DIAG=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/inka4x0_defconfig b/configs/inka4x0_defconfig
deleted file mode 100644
index c263cf61c5..0000000000
--- a/configs/inka4x0_defconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_INKA4X0=y
-CONFIG_BOOTDELAY=1
-CONFIG_LOOPW=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/ipek01_defconfig b/configs/ipek01_defconfig
deleted file mode 100644
index f86170d346..0000000000
--- a/configs/ipek01_defconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-CONFIG_PPC=y
-CONFIG_VIDEO=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_IPEK01=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_LOOPW=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_IRQ=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_CONSOLE_EXTRA_INFO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/jupiter_defconfig b/configs/jupiter_defconfig
deleted file mode 100644
index 8e4e44702d..0000000000
--- a/configs/jupiter_defconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_JUPITER=y
-CONFIG_BOOTDELAY=5
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_SNTP=y
-CONFIG_MAC_PARTITION=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
diff --git a/configs/mecp5123_defconfig b/configs/mecp5123_defconfig
deleted file mode 100644
index 3937fe8b44..0000000000
--- a/configs/mecp5123_defconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC512X=y
-CONFIG_TARGET_MECP5123=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_BAUDRATE=9600
-CONFIG_OF_LIBFDT=y
diff --git a/configs/motionpro_defconfig b/configs/motionpro_defconfig
deleted file mode 100644
index c4006bca5f..0000000000
--- a/configs/motionpro_defconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_CMD_IMMAP=y
-CONFIG_TARGET_MOTIONPRO=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
-CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_IDE=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_BEDBUG=y
-CONFIG_LED_STATUS=y
-CONFIG_LED_STATUS0=y
-CONFIG_LED_STATUS_BIT=0
-CONFIG_LED_STATUS_STATE=1
-CONFIG_LED_STATUS_FREQ=10
-CONFIG_LED_STATUS1=y
-CONFIG_LED_STATUS_BIT1=1
-CONFIG_LED_STATUS_FREQ1=10
-CONFIG_LED_STATUS_BOOT_ENABLE=y
-CONFIG_LED_STATUS_BOOT=0
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_OF_LIBFDT=y
diff --git a/configs/mpc5121ads_defconfig b/configs/mpc5121ads_defconfig
deleted file mode 100644
index 5bb78076ad..0000000000
--- a/configs/mpc5121ads_defconfig
+++ /dev/null
@@ -1,25 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC512X=y
-CONFIG_TARGET_MPC5121ADS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/mpc5121ads_rev2_defconfig b/configs/mpc5121ads_rev2_defconfig
deleted file mode 100644
index e28fa19227..0000000000
--- a/configs/mpc5121ads_rev2_defconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC512X=y
-CONFIG_TARGET_MPC5121ADS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="MPC5121ADS_REV2"
-CONFIG_BOOTDELAY=5
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/munices_defconfig b/configs/munices_defconfig
deleted file mode 100644
index 0e2b188a51..0000000000
--- a/configs/munices_defconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_CMD_IMMAP=y
-CONFIG_TARGET_MUNICES=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_OF_LIBFDT=y
diff --git a/configs/pcm030_LOWBOOT_defconfig b/configs/pcm030_LOWBOOT_defconfig
deleted file mode 100644
index 0ef8750d66..0000000000
--- a/configs/pcm030_LOWBOOT_defconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_PCM030=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000"
-CONFIG_BOOTDELAY=3
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_JFFS2=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/pcm030_defconfig b/configs/pcm030_defconfig
deleted file mode 100644
index 3869991f9e..0000000000
--- a/configs/pcm030_defconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_PCM030=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_PROMPT="uboot> "
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_JFFS2=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/pdm360ng_defconfig b/configs/pdm360ng_defconfig
deleted file mode 100644
index 4ef0df1aa8..0000000000
--- a/configs/pdm360ng_defconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-CONFIG_PPC=y
-CONFIG_VIDEO=y
-CONFIG_MPC512X=y
-CONFIG_TARGET_PDM360NG=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/v38b_defconfig b/configs/v38b_defconfig
deleted file mode 100644
index c75e547b7f..0000000000
--- a/configs/v38b_defconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_V38B=y
-CONFIG_BOOTDELAY=3
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_DIAG=y
-CONFIG_CMD_IRQ=y
-CONFIG_MAC_PARTITION=y
-CONFIG_LED_STATUS=y
-CONFIG_LED_STATUS0=y
-CONFIG_LED_STATUS_BIT=16
-CONFIG_LED_STATUS_STATE=1
-CONFIG_LED_STATUS_BOOT_ENABLE=y
-CONFIG_LED_STATUS_BOOT=0
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/doc/README.generic_usb_ohci b/doc/README.generic_usb_ohci
index ba7cea83ca..61300c3575 100644
--- a/doc/README.generic_usb_ohci
+++ b/doc/README.generic_usb_ohci
@@ -36,8 +36,8 @@ Endianness issues
 ------------------
 
 The USB bus operates in little endian, but unfortunately there are
-OHCI controllers that operate in big endian such as ppc4xx and
-mpc5xxx. For these the config option
+OHCI controllers that operate in big endian such as ppc4xx. For these the
+config option
 
 	CONFIG_SYS_OHCI_BE_CONTROLLER
 
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 200f670806..e43e3c0fa9 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -106,13 +106,9 @@ sbc35_a9g20      arm         arm926ejs      f6b42c14    2015-05-13  Albin Tonner
 sc3              powerpc     ppc4xx         27e72156    2015-05-10  Heiko Schocher <hs@denx.de>
 T4240EMU         powerpc     mpc85xx        7fc63cca    2015-05-05  York Sun <yorksun@freescale.com>
 korat            powerpc     ppc4xx         5043045d    2015-03-17  Larry Johnson <lrj@acm.org>
-galaxy5200       powerpc     mpc5xxx        41eb4e5c    2015-03-17  Eric Millbrandt <emillbrandt@dekaresearch.com>
 W7OLMC           powerpc     ppc4xx         6beecd5d    2015-03-17  Erik Theisen <etheisen@mindspring.com>
 W7OLMG           powerpc     ppc4xx         6beecd5d    2015-03-17  Erik Theisen <etheisen@mindspring.com>
-aev              powerpc     mpc5xxx        470ee8b1    2015-03-17
-TB5200           powerpc     mpc5xxx        470ee8b1    2015-03-17
 JSE              powerpc     ppc4xx         2da8137b    2015-03-17  Stephen Williams <steve@icarus.com>
-BC3450           powerpc     mpc5xxx        f8296d69    2015-03-17
 hawkboard        arm         arm926ejs      cb957cda    2015-02-24  Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
 tnetv107x        arm         arm1176        50b82c4b    2015-02-24  Chan-Taek Park <c-park@ti.com>
 a320evb          arm         arm920t        29fc6f24    2015-02-24  Po-Yu Chuang <ratbert@faraday-tech.com>
@@ -120,13 +116,6 @@ cm4008           arm         arm920t        a2f39e83    2015-02-24  Greg Ungerer
 cm41xx           arm         arm920t        a2f39e83    2015-02-24
 dkb              arm         arm926ejs      346cfba4    2015-02-24  Lei Wen <leiwen@marvell.com>
 jadecpu          arm         arm926ejs      41fbbbbc    2015-02-24  Matthias Weisser <weisserm@arcor.de>
-icecube_5200     powerpc     mpc5xxx        37b608a5    2015-01-23  Wolfgang Denk <wd@denx.de>
-Lite5200         powerpc     mpc5xxx        37b608a5    2015-01-23
-cpci5200         powerpc     mpc5xxx        37b608a5    2015-01-23  Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-mecp5200         powerpc     mpc5xxx        37b608a5    2015-01-23  Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-pf5200           powerpc     mpc5xxx        37b608a5    2015-01-23  Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-PM520            powerpc     mpc5xxx        a258e732    2015-01-23  Josef Wagner <Wagner@Microsys.de>
-Total5200        powerpc     mpc5xxx        ad734f7d    2015-01-23
 CATcenter        powerpc     ppc4xx         5344cc1a    2015-01-23
 PPChameleonEVB   powerpc     ppc4xx         5344cc1a    2015-01-23  Andrea "llandre" Marson <andrea.marson@dave-tech.it>
 P2020DS          powerpc     mpc85xx        168dcc6c    2015-01-23
@@ -200,9 +189,6 @@ SPD823TS         powerpc     mpc8xx         72ba368f    2015-01-05  Wolfgang Den
 KUP4K            powerpc     mpc8xx         4317d070    2015-01-05  Klaus Heydeck <heydeck@kieback-peter.de>
 KUP4X            powerpc     mpc8xx         4317d070    2015-01-05  Klaus Heydeck <heydeck@kieback-peter.de>
 ELPT860          powerpc     mpc8xx         3c5b20f1    2015-01-05  The LEOX team <team@leox.org>
-hmi1001          powerpc     mpc5xxx        ceaf499b    2015-01-05
-mucmc52          powerpc     mpc5xxx        ceaf499b    2015-01-05  Heiko Schocher <hs@denx.de>
-uc101            powerpc     mpc5xxx        ceaf499b    2015-01-05  Heiko Schocher <hs@denx.de>
 uc100            powerpc     mpc8xx         ceaf499b    2015-01-05  Stefan Roese <sr@denx.de>
 FPS850L          powerpc     mpc8xx         5d2a5ef7    2015-01-05  Wolfgang Denk <wd@denx.de>
 FPS860L          powerpc     mpc8xx         5d2a5ef7    2015-01-05  Wolfgang Denk <wd@denx.de>
@@ -211,9 +197,6 @@ SM850            powerpc     mpc8xx         5d2a5ef7    2015-01-05  Wolfgang Den
 TK885D           powerpc     mpc8xx         5d2a5ef7    2015-01-05
 virtlab2         powerpc     mpc8xx         5d2a5ef7    2015-01-05  Wolfgang Denk <wd@denx.de>
 hermes           powerpc     mpc8xx         36da51e     2014-12-08  Wolfgang Denk <wd@denx.de>
-PRS200		 powerpc     mpc5200	    ecfdcee	2014-11-12
-MCC200		 powerpc     mpc5200	    ecfdcee     2014-11-12
-TOP5200		 powerpc     mpc5200	    d58a945	2014-10-28  Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
 TOP860		 powerpc     mpc860	    d58a945	2014-10-28  Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
 TOP9000		 arm	     at91sam9xeXXX  d58a945	2014-10-28  Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
 TQM8272          powerpc     mpc8260        f06f9a1     2014-10-27  Wolfgang Denk <wd@denx.de>
@@ -228,8 +211,6 @@ DB64360		 powerpc     74xx_7xx	    03b0040	2014-10-27
 DB64460		 powerpc     74xx_7xx	    03b0040	2014-10-27
 p3m750		 powerpc     74xx_7xx	    03b0040	2014-10-27  Stefan Roese <sr@denx.de>
 p3m7448		 powerpc     74xx_7xx	    03b0040	2014-10-27  Stefan Roese <sr@denx.de>
-MVBC_P           powerpc     mpc5xxx        af55e35	2014-10-10  Andre Schwarz <andre.schwarz@matrix-vision.de>
-MVSMR            powerpc     mpc5xxx        af55e35	2014-10-10  Andre Schwarz <andre.schwarz@matrix-vision.de>
 MERGERBOX        powerpc     mpc83xx        e7a5656	2014-10-10  Andre Schwarz <andre.schwarz@matrix-vision.de>
 MVBLM7           powerpc     mpc83xx        e7a5656	2014-10-10  Andre Schwarz <andre.schwarz@matrix-vision.de>
 bluestone        powerpc     ppc4xx         9ed3246	2014-10-10  Tirumala Marri <tmarri@apm.com>
@@ -373,8 +354,6 @@ CP850            powerpc     MPC852         333d86d     2010-10-19  Wolfgang Den
 logodl           ARM         PXA2xx         059e778     2010-10-18  August Hoeraendl <august.hoerandl@gmx.at>
 CCM              powerpc     MPC860         dff07e1     2010-10-06  Wolfgang Grandegger <wg@denx.de>
 PCU_E            powerpc     MPC860T        544d97e     2010-10-06  Wolfgang Denk <wd@denx.de>
-spieval          powerpc     MPC5200        69434e4     2010-09-19
-smmaco4          powerpc     MPC5200        9ddc3af     2010-09-19
 HMI10            powerpc     MPC823         77efe35     2010-09-19  Wolfgang Denk <wd@denx.de>
 GTH              powerpc     MPC860         0fe247b     2010-07-17  Thomas Lange <thomas@corelatus.se>
 AmigaOneG3SE     powerpc     74xx_7xx       953b7e6     2010-06-23
diff --git a/doc/README.serial_multi b/doc/README.serial_multi
index ad61d4261b..c9049fd01d 100644
--- a/doc/README.serial_multi
+++ b/doc/README.serial_multi
@@ -52,29 +52,3 @@ PPC4XX Specific
 	setenv stdout serial0
 	setenv stderr serial0
 	setenv stdin serial0
-
-MPC5xxx Specific
-================
-
-Up to two PSCs can be used as console.
-
-Support for hardware handshake has not been implemented yet.
-
-*) The first (default) console port is defined by:
-	#define CONFIG_PSC_CONSOLE <PSC number>
-
-*) The second (alternative) console port is defined by:
-	#define CONFIG_PSC_CONSOLE2 <PSC number>
-
-*) Commands to switch to the second console:
-	setenv stdout serial1
-	setenv stderr serial1
-	setenv stdin serial1
-
-*) Commands to switch to the first console:
-	setenv stdout serial0
-	setenv stderr serial0
-	setenv stdin serial0
-
-*) If a file descriptor is set to "serial" then the
-   current serial device will be used.
diff --git a/drivers/bootcount/bootcount.c b/drivers/bootcount/bootcount.c
index 38f8653603..8c1d10e26e 100644
--- a/drivers/bootcount/bootcount.c
+++ b/drivers/bootcount/bootcount.c
@@ -14,16 +14,6 @@
  */
 #if !defined(CONFIG_SYS_BOOTCOUNT_ADDR)
 
-#if defined(CONFIG_MPC5xxx)
-#define CONFIG_SYS_BOOTCOUNT_ADDR	(MPC5XXX_CDM_BRDCRMB)
-#define CONFIG_SYS_BOOTCOUNT_SINGLEWORD
-#endif /* defined(CONFIG_MPC5xxx) */
-
-#if defined(CONFIG_MPC512X)
-#define CONFIG_SYS_BOOTCOUNT_ADDR	(&((immap_t *)CONFIG_SYS_IMMR)->clk.bcr)
-#define CONFIG_SYS_BOOTCOUNT_SINGLEWORD
-#endif /* defined(CONFIG_MPC512X) */
-
 #if defined(CONFIG_8xx)
 #define CONFIG_SYS_BOOTCOUNT_ADDR (((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + \
 				CPM_BOOTCOUNT_ADDR)
diff --git a/drivers/input/keyboard.c b/drivers/input/keyboard.c
index 7af5868dea..84ee015cb3 100644
--- a/drivers/input/keyboard.c
+++ b/drivers/input/keyboard.c
@@ -20,7 +20,7 @@ static struct input_config config;
 
 static int kbd_read_keys(struct input_config *config)
 {
-#if defined(CONFIG_MPC5xxx) || defined(CONFIG_ARCH_MPC8540) || \
+#if defined(CONFIG_ARCH_MPC8540) || \
 		defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
 	/* no ISR is used, so received chars must be polled */
 	ps2ser_check();
diff --git a/drivers/input/ps2ser.c b/drivers/input/ps2ser.c
index bcbe52af15..0b5ce06853 100644
--- a/drivers/input/ps2ser.c
+++ b/drivers/input/ps2ser.c
@@ -29,25 +29,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define PS2SER_BAUD	57600
 
-#ifdef CONFIG_MPC5xxx
-#if CONFIG_PS2SERIAL == 1
-#define PSC_BASE MPC5XXX_PSC1
-#elif CONFIG_PS2SERIAL == 2
-#define PSC_BASE MPC5XXX_PSC2
-#elif CONFIG_PS2SERIAL == 3
-#define PSC_BASE MPC5XXX_PSC3
-#elif CONFIG_PS2SERIAL == 4
-#define PSC_BASE MPC5XXX_PSC4
-#elif CONFIG_PS2SERIAL == 5
-#define PSC_BASE MPC5XXX_PSC5
-#elif CONFIG_PS2SERIAL == 6
-#define PSC_BASE MPC5XXX_PSC6
-#else
-#error CONFIG_PS2SERIAL must be in 1 ... 6
-#endif
-
-#else
-
 #if CONFIG_PS2SERIAL == 1
 #define COM_BASE (CONFIG_SYS_CCSRBAR+0x4500)
 #elif CONFIG_PS2SERIAL == 2
@@ -56,8 +37,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #error CONFIG_PS2SERIAL must be in 1 ... 2
 #endif
 
-#endif /* CONFIG_MPC5xxx / other */
-
 static int	ps2ser_getc_hw(void);
 static void	ps2ser_interrupt(void *dev_id);
 
@@ -68,45 +47,6 @@ static atomic_t	ps2buf_cnt;
 static int	ps2buf_in_idx;
 static int	ps2buf_out_idx;
 
-#ifdef CONFIG_MPC5xxx
-int ps2ser_init(void)
-{
-	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-	unsigned long baseclk;
-	int div;
-
-	/* reset PSC */
-	psc->command = PSC_SEL_MODE_REG_1;
-
-	/* select clock sources */
-	psc->psc_clock_select = 0;
-	baseclk = (gd->arch.ipb_clk + 16) / 32;
-
-	/* switch to UART mode */
-	psc->sicr = 0;
-
-	/* configure parity, bit length and so on */
-	psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
-	psc->mode = PSC_MODE_ONE_STOP;
-
-	/* set up UART divisor */
-	div = (baseclk + (PS2SER_BAUD/2)) / PS2SER_BAUD;
-	psc->ctur = (div >> 8) & 0xff;
-	psc->ctlr = div & 0xff;
-
-	/* disable all interrupts */
-	psc->psc_imr = 0;
-
-	/* reset and enable Rx/Tx */
-	psc->command = PSC_RST_RX;
-	psc->command = PSC_RST_TX;
-	psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE;
-
-	return (0);
-}
-
-#else
-
 int ps2ser_init(void)
 {
 	NS16550_t com_port = (NS16550_t)COM_BASE;
@@ -122,45 +62,23 @@ int ps2ser_init(void)
 	return (0);
 }
 
-#endif /* CONFIG_MPC5xxx / other */
-
 void ps2ser_putc(int chr)
 {
-#ifdef CONFIG_MPC5xxx
-	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#else
 	NS16550_t com_port = (NS16550_t)COM_BASE;
-#endif
 	debug(">>>> 0x%02x\n", chr);
 
-#ifdef CONFIG_MPC5xxx
-	while (!(psc->psc_status & PSC_SR_TXRDY));
-
-	psc->psc_buffer_8 = chr;
-#else
 	while ((com_port->lsr & UART_LSR_THRE) == 0);
 	com_port->thr = chr;
-#endif
 }
 
 static int ps2ser_getc_hw(void)
 {
-#ifdef CONFIG_MPC5xxx
-	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#else
 	NS16550_t com_port = (NS16550_t)COM_BASE;
-#endif
 	int res = -1;
 
-#ifdef CONFIG_MPC5xxx
-	if (psc->psc_status & PSC_SR_RXRDY) {
-		res = (psc->psc_buffer_8);
-	}
-#else
 	if (com_port->lsr & UART_LSR_DR) {
 		res = com_port->rbr;
 	}
-#endif
 
 	return res;
 }
@@ -206,21 +124,13 @@ int ps2ser_check(void)
 
 static void ps2ser_interrupt(void *dev_id)
 {
-#ifdef CONFIG_MPC5xxx
-	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#else
 	NS16550_t com_port = (NS16550_t)COM_BASE;
-#endif
 	int chr;
 	int status;
 
 	do {
 		chr = ps2ser_getc_hw();
-#ifdef CONFIG_MPC5xxx
-		status = psc->psc_status;
-#else
 		status = com_port->lsr;
-#endif
 		if (chr < 0) continue;
 
 		if (atomic_read(&ps2buf_cnt) < PS2BUF_SIZE) {
@@ -230,11 +140,7 @@ static void ps2ser_interrupt(void *dev_id)
 		} else {
 			printf ("ps2ser.c: buffer overflow\n");
 		}
-#ifdef CONFIG_MPC5xxx
-	} while (status & PSC_SR_RXRDY);
-#else
 	} while (status & UART_LSR_DR);
-#endif
 	if (atomic_read(&ps2buf_cnt)) {
 		ps2mult_callback(atomic_read(&ps2buf_cnt));
 	}
diff --git a/drivers/misc/fsl_iim.c b/drivers/misc/fsl_iim.c
index 2feb1823e4..3c9f029eda 100644
--- a/drivers/misc/fsl_iim.c
+++ b/drivers/misc/fsl_iim.c
@@ -13,9 +13,7 @@
 #include <fuse.h>
 #include <linux/errno.h>
 #include <asm/io.h>
-#ifndef CONFIG_MPC512X
 #include <asm/arch/imx-regs.h>
-#endif
 #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
 #include <asm/arch/clock.h>
 #endif
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index a7b76f4218..ce8ba99c82 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -33,11 +33,11 @@ config NAND_DENALI_SPARE_AREA_SKIP_BYTES
 	  used to preserve the bad block marker in the OOB area.
 
 config NAND_VF610_NFC
-	bool "Support for Freescale NFC for VF610/MPC5125"
+	bool "Support for Freescale NFC for VF610"
 	select SYS_NAND_SELF_INIT
 	help
 	  Enables support for NAND Flash Controller on some Freescale
-	  processors like the VF610, MPC5125, MCF54418 or Kinetis K70.
+	  processors like the VF610, MCF54418 or Kinetis K70.
 	  The driver supports a maximum 2k page size. The driver
 	  currently does not support hardware ECC.
 
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 5d5f9f5267..c3d4a996f3 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -53,7 +53,6 @@ obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
 obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
 obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o
 obj-$(CONFIG_NAND_LPC32XX_SLC) += lpc32xx_nand_slc.o
-obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
 obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
 obj-$(CONFIG_NAND_MXC) += mxc_nand.o
 obj-$(CONFIG_NAND_MXS) += mxs_nand.o
diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c
deleted file mode 100644
index 7faabddbf2..0000000000
--- a/drivers/mtd/nand/mpc5121_nfc.c
+++ /dev/null
@@ -1,656 +0,0 @@
-/*
- * Copyright 2004-2008 Freescale Semiconductor, Inc.
- * Copyright 2009 Semihalf.
- * (C) Copyright 2009 Stefan Roese <sr@denx.de>
- *
- * Based on original driver from Freescale Semiconductor
- * written by John Rigby <jrigby@freescale.com> on basis
- * of drivers/mtd/nand/mxc_nand.c. Reworked and extended
- * Piotr Ziecik <kosmo@semihalf.com>.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <malloc.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/nand_ecc.h>
-#include <linux/compat.h>
-
-#include <linux/errno.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <nand.h>
-
-#define DRV_NAME		"mpc5121_nfc"
-
-/* Timeouts */
-#define NFC_RESET_TIMEOUT	1000	/* 1 ms */
-#define NFC_TIMEOUT		2000	/* 2000 us */
-
-/* Addresses for NFC MAIN RAM BUFFER areas */
-#define NFC_MAIN_AREA(n)	((n) *  0x200)
-
-/* Addresses for NFC SPARE BUFFER areas */
-#define NFC_SPARE_BUFFERS	8
-#define NFC_SPARE_LEN		0x40
-#define NFC_SPARE_AREA(n)	(0x1000 + ((n) * NFC_SPARE_LEN))
-
-/* MPC5121 NFC registers */
-#define NFC_BUF_ADDR		0x1E04
-#define NFC_FLASH_ADDR		0x1E06
-#define NFC_FLASH_CMD		0x1E08
-#define NFC_CONFIG		0x1E0A
-#define NFC_ECC_STATUS1		0x1E0C
-#define NFC_ECC_STATUS2		0x1E0E
-#define NFC_SPAS		0x1E10
-#define NFC_WRPROT		0x1E12
-#define NFC_NF_WRPRST		0x1E18
-#define NFC_CONFIG1		0x1E1A
-#define NFC_CONFIG2		0x1E1C
-#define NFC_UNLOCKSTART_BLK0	0x1E20
-#define NFC_UNLOCKEND_BLK0	0x1E22
-#define NFC_UNLOCKSTART_BLK1	0x1E24
-#define NFC_UNLOCKEND_BLK1	0x1E26
-#define NFC_UNLOCKSTART_BLK2	0x1E28
-#define NFC_UNLOCKEND_BLK2	0x1E2A
-#define NFC_UNLOCKSTART_BLK3	0x1E2C
-#define NFC_UNLOCKEND_BLK3	0x1E2E
-
-/* Bit Definitions: NFC_BUF_ADDR */
-#define NFC_RBA_MASK		(7 << 0)
-#define NFC_ACTIVE_CS_SHIFT	5
-#define NFC_ACTIVE_CS_MASK	(3 << NFC_ACTIVE_CS_SHIFT)
-
-/* Bit Definitions: NFC_CONFIG */
-#define NFC_BLS_UNLOCKED	(1 << 1)
-
-/* Bit Definitions: NFC_CONFIG1 */
-#define NFC_ECC_4BIT		(1 << 0)
-#define NFC_FULL_PAGE_DMA	(1 << 1)
-#define NFC_SPARE_ONLY		(1 << 2)
-#define NFC_ECC_ENABLE		(1 << 3)
-#define NFC_INT_MASK		(1 << 4)
-#define NFC_BIG_ENDIAN		(1 << 5)
-#define NFC_RESET		(1 << 6)
-#define NFC_CE			(1 << 7)
-#define NFC_ONE_CYCLE		(1 << 8)
-#define NFC_PPB_32		(0 << 9)
-#define NFC_PPB_64		(1 << 9)
-#define NFC_PPB_128		(2 << 9)
-#define NFC_PPB_256		(3 << 9)
-#define NFC_PPB_MASK		(3 << 9)
-#define NFC_FULL_PAGE_INT	(1 << 11)
-
-/* Bit Definitions: NFC_CONFIG2 */
-#define NFC_COMMAND		(1 << 0)
-#define NFC_ADDRESS		(1 << 1)
-#define NFC_INPUT		(1 << 2)
-#define NFC_OUTPUT		(1 << 3)
-#define NFC_ID			(1 << 4)
-#define NFC_STATUS		(1 << 5)
-#define NFC_CMD_FAIL		(1 << 15)
-#define NFC_INT			(1 << 15)
-
-/* Bit Definitions: NFC_WRPROT */
-#define NFC_WPC_LOCK_TIGHT	(1 << 0)
-#define NFC_WPC_LOCK		(1 << 1)
-#define NFC_WPC_UNLOCK		(1 << 2)
-
-struct mpc5121_nfc_prv {
-	struct nand_chip chip;
-	int irq;
-	void __iomem *regs;
-	struct clk *clk;
-	uint column;
-	int spareonly;
-	int chipsel;
-};
-
-int mpc5121_nfc_chip = 0;
-
-static void mpc5121_nfc_done(struct mtd_info *mtd);
-
-/* Read NFC register */
-static inline u16 nfc_read(struct mtd_info *mtd, uint reg)
-{
-	struct nand_chip *chip = mtd_to_nand(mtd);
-	struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
-
-	return in_be16(prv->regs + reg);
-}
-
-/* Write NFC register */
-static inline void nfc_write(struct mtd_info *mtd, uint reg, u16 val)
-{
-	struct nand_chip *chip = mtd_to_nand(mtd);
-	struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
-
-	out_be16(prv->regs + reg, val);
-}
-
-/* Set bits in NFC register */
-static inline void nfc_set(struct mtd_info *mtd, uint reg, u16 bits)
-{
-	nfc_write(mtd, reg, nfc_read(mtd, reg) | bits);
-}
-
-/* Clear bits in NFC register */
-static inline void nfc_clear(struct mtd_info *mtd, uint reg, u16 bits)
-{
-	nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits);
-}
-
-/* Invoke address cycle */
-static inline void mpc5121_nfc_send_addr(struct mtd_info *mtd, u16 addr)
-{
-	nfc_write(mtd, NFC_FLASH_ADDR, addr);
-	nfc_write(mtd, NFC_CONFIG2, NFC_ADDRESS);
-	mpc5121_nfc_done(mtd);
-}
-
-/* Invoke command cycle */
-static inline void mpc5121_nfc_send_cmd(struct mtd_info *mtd, u16 cmd)
-{
-	nfc_write(mtd, NFC_FLASH_CMD, cmd);
-	nfc_write(mtd, NFC_CONFIG2, NFC_COMMAND);
-	mpc5121_nfc_done(mtd);
-}
-
-/* Send data from NFC buffers to NAND flash */
-static inline void mpc5121_nfc_send_prog_page(struct mtd_info *mtd)
-{
-	nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
-	nfc_write(mtd, NFC_CONFIG2, NFC_INPUT);
-	mpc5121_nfc_done(mtd);
-}
-
-/* Receive data from NAND flash */
-static inline void mpc5121_nfc_send_read_page(struct mtd_info *mtd)
-{
-	nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
-	nfc_write(mtd, NFC_CONFIG2, NFC_OUTPUT);
-	mpc5121_nfc_done(mtd);
-}
-
-/* Receive ID from NAND flash */
-static inline void mpc5121_nfc_send_read_id(struct mtd_info *mtd)
-{
-	nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
-	nfc_write(mtd, NFC_CONFIG2, NFC_ID);
-	mpc5121_nfc_done(mtd);
-}
-
-/* Receive status from NAND flash */
-static inline void mpc5121_nfc_send_read_status(struct mtd_info *mtd)
-{
-	nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
-	nfc_write(mtd, NFC_CONFIG2, NFC_STATUS);
-	mpc5121_nfc_done(mtd);
-}
-
-static void mpc5121_nfc_done(struct mtd_info *mtd)
-{
-	int max_retries = NFC_TIMEOUT;
-
-	while (1) {
-		max_retries--;
-		if (nfc_read(mtd, NFC_CONFIG2) & NFC_INT)
-			break;
-		udelay(1);
-	}
-
-	if (max_retries <= 0)
-		printk(KERN_WARNING DRV_NAME
-		       ": Timeout while waiting for completion.\n");
-}
-
-/* Do address cycle(s) */
-static void mpc5121_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
-{
-	struct nand_chip *chip = mtd_to_nand(mtd);
-	u32 pagemask = chip->pagemask;
-
-	if (column != -1) {
-		mpc5121_nfc_send_addr(mtd, column);
-		if (mtd->writesize > 512)
-			mpc5121_nfc_send_addr(mtd, column >> 8);
-	}
-
-	if (page != -1) {
-		do {
-			mpc5121_nfc_send_addr(mtd, page & 0xFF);
-			page >>= 8;
-			pagemask >>= 8;
-		} while (pagemask);
-	}
-}
-
-/* Control chip select signals */
-
-/*
- * Selecting the active device:
- *
- * This is different than the linux version. Switching between chips
- * is done via board_nand_select_device(). The Linux select_chip
- * function used here in U-Boot has only 2 valid chip numbers:
- * 	0 select
- * 	-1 deselect
- */
-
-/*
- * Implement it as a weak default, so that boards with a specific
- * chip-select routine can use their own function.
- */
-void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
-{
-	if (chip < 0) {
-		nfc_clear(mtd, NFC_CONFIG1, NFC_CE);
-		return;
-	}
-
-	nfc_clear(mtd, NFC_BUF_ADDR, NFC_ACTIVE_CS_MASK);
-	nfc_set(mtd, NFC_BUF_ADDR, (chip << NFC_ACTIVE_CS_SHIFT) &
-		NFC_ACTIVE_CS_MASK);
-	nfc_set(mtd, NFC_CONFIG1, NFC_CE);
-}
-void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
-	__attribute__((weak, alias("__mpc5121_nfc_select_chip")));
-
-void board_nand_select_device(struct nand_chip *nand, int chip)
-{
-	/*
-	 * Only save this chip number in global variable here. This
-	 * will be used later in mpc5121_nfc_select_chip().
-	 */
-	mpc5121_nfc_chip = chip;
-}
-
-/* Read NAND Ready/Busy signal */
-static int mpc5121_nfc_dev_ready(struct mtd_info *mtd)
-{
-	/*
-	 * NFC handles ready/busy signal internally. Therefore, this function
-	 * always returns status as ready.
-	 */
-	return 1;
-}
-
-/* Write command to NAND flash */
-static void mpc5121_nfc_command(struct mtd_info *mtd, unsigned command,
-				int column, int page)
-{
-	struct nand_chip *chip = mtd_to_nand(mtd);
-	struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
-
-	prv->column = (column >= 0) ? column : 0;
-	prv->spareonly = 0;
-
-	switch (command) {
-	case NAND_CMD_PAGEPROG:
-		mpc5121_nfc_send_prog_page(mtd);
-		break;
-		/*
-		 * NFC does not support sub-page reads and writes,
-		 * so emulate them using full page transfers.
-		 */
-	case NAND_CMD_READ0:
-		column = 0;
-		break;
-
-	case NAND_CMD_READ1:
-		prv->column += 256;
-		command = NAND_CMD_READ0;
-		column = 0;
-		break;
-
-	case NAND_CMD_READOOB:
-		prv->spareonly = 1;
-		command = NAND_CMD_READ0;
-		column = 0;
-		break;
-
-	case NAND_CMD_SEQIN:
-		mpc5121_nfc_command(mtd, NAND_CMD_READ0, column, page);
-		column = 0;
-		break;
-
-	case NAND_CMD_ERASE1:
-	case NAND_CMD_ERASE2:
-	case NAND_CMD_READID:
-	case NAND_CMD_STATUS:
-	case NAND_CMD_RESET:
-		break;
-
-	default:
-		return;
-	}
-
-	mpc5121_nfc_send_cmd(mtd, command);
-	mpc5121_nfc_addr_cycle(mtd, column, page);
-
-	switch (command) {
-	case NAND_CMD_READ0:
-		if (mtd->writesize > 512)
-			mpc5121_nfc_send_cmd(mtd, NAND_CMD_READSTART);
-		mpc5121_nfc_send_read_page(mtd);
-		break;
-
-	case NAND_CMD_READID:
-		mpc5121_nfc_send_read_id(mtd);
-		break;
-
-	case NAND_CMD_STATUS:
-		mpc5121_nfc_send_read_status(mtd);
-		if (chip->options & NAND_BUSWIDTH_16)
-			prv->column = 1;
-		else
-			prv->column = 0;
-		break;
-	}
-}
-
-/* Copy data from/to NFC spare buffers. */
-static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset,
-				   u8 * buffer, uint size, int wr)
-{
-	struct nand_chip *nand = mtd_to_nand(mtd);
-	struct mpc5121_nfc_prv *prv = nand_get_controller_data(nand);
-	uint o, s, sbsize, blksize;
-
-	/*
-	 * NAND spare area is available through NFC spare buffers.
-	 * The NFC divides spare area into (page_size / 512) chunks.
-	 * Each chunk is placed into separate spare memory area, using
-	 * first (spare_size / num_of_chunks) bytes of the buffer.
-	 *
-	 * For NAND device in which the spare area is not divided fully
-	 * by the number of chunks, number of used bytes in each spare
-	 * buffer is rounded down to the nearest even number of bytes,
-	 * and all remaining bytes are added to the last used spare area.
-	 *
-	 * For more information read section 26.6.10 of MPC5121e
-	 * Microcontroller Reference Manual, Rev. 3.
-	 */
-
-	/* Calculate number of valid bytes in each spare buffer */
-	sbsize = (mtd->oobsize / (mtd->writesize / 512)) & ~1;
-
-	while (size) {
-		/* Calculate spare buffer number */
-		s = offset / sbsize;
-		if (s > NFC_SPARE_BUFFERS - 1)
-			s = NFC_SPARE_BUFFERS - 1;
-
-		/*
-		 * Calculate offset to requested data block in selected spare
-		 * buffer and its size.
-		 */
-		o = offset - (s * sbsize);
-		blksize = min(sbsize - o, size);
-
-		if (wr)
-			memcpy_toio(prv->regs + NFC_SPARE_AREA(s) + o,
-				    buffer, blksize);
-		else
-			memcpy_fromio(buffer,
-				      prv->regs + NFC_SPARE_AREA(s) + o,
-				      blksize);
-
-		buffer += blksize;
-		offset += blksize;
-		size -= blksize;
-	};
-}
-
-/* Copy data from/to NFC main and spare buffers */
-static void mpc5121_nfc_buf_copy(struct mtd_info *mtd, u_char * buf, int len,
-				 int wr)
-{
-	struct nand_chip *chip = mtd_to_nand(mtd);
-	struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
-	uint c = prv->column;
-	uint l;
-
-	/* Handle spare area access */
-	if (prv->spareonly || c >= mtd->writesize) {
-		/* Calculate offset from beginning of spare area */
-		if (c >= mtd->writesize)
-			c -= mtd->writesize;
-
-		prv->column += len;
-		mpc5121_nfc_copy_spare(mtd, c, buf, len, wr);
-		return;
-	}
-
-	/*
-	 * Handle main area access - limit copy length to prevent
-	 * crossing main/spare boundary.
-	 */
-	l = min((uint) len, mtd->writesize - c);
-	prv->column += l;
-
-	if (wr)
-		memcpy_toio(prv->regs + NFC_MAIN_AREA(0) + c, buf, l);
-	else
-		memcpy_fromio(buf, prv->regs + NFC_MAIN_AREA(0) + c, l);
-
-	/* Handle crossing main/spare boundary */
-	if (l != len) {
-		buf += l;
-		len -= l;
-		mpc5121_nfc_buf_copy(mtd, buf, len, wr);
-	}
-}
-
-/* Read data from NFC buffers */
-static void mpc5121_nfc_read_buf(struct mtd_info *mtd, u_char * buf, int len)
-{
-	mpc5121_nfc_buf_copy(mtd, buf, len, 0);
-}
-
-/* Write data to NFC buffers */
-static void mpc5121_nfc_write_buf(struct mtd_info *mtd,
-				  const u_char * buf, int len)
-{
-	mpc5121_nfc_buf_copy(mtd, (u_char *) buf, len, 1);
-}
-
-/* Read byte from NFC buffers */
-static u8 mpc5121_nfc_read_byte(struct mtd_info *mtd)
-{
-	u8 tmp;
-
-	mpc5121_nfc_read_buf(mtd, &tmp, sizeof(tmp));
-
-	return tmp;
-}
-
-/* Read word from NFC buffers */
-static u16 mpc5121_nfc_read_word(struct mtd_info *mtd)
-{
-	u16 tmp;
-
-	mpc5121_nfc_read_buf(mtd, (u_char *) & tmp, sizeof(tmp));
-
-	return tmp;
-}
-
-/*
- * Read NFC configuration from Reset Config Word
- *
- * NFC is configured during reset in basis of information stored
- * in Reset Config Word. There is no other way to set NAND block
- * size, spare size and bus width.
- */
-static int mpc5121_nfc_read_hw_config(struct mtd_info *mtd)
-{
-	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	struct nand_chip *chip = mtd_to_nand(mtd);
-	uint rcw_pagesize = 0;
-	uint rcw_sparesize = 0;
-	uint rcw_width;
-	uint rcwh;
-	uint romloc, ps;
-
-	rcwh = in_be32(&(im->reset.rcwh));
-
-	/* Bit 6: NFC bus width */
-	rcw_width = ((rcwh >> 6) & 0x1) ? 2 : 1;
-
-	/* Bit 7: NFC Page/Spare size */
-	ps = (rcwh >> 7) & 0x1;
-
-	/* Bits [22:21]: ROM Location */
-	romloc = (rcwh >> 21) & 0x3;
-
-	/* Decode RCW bits */
-	switch ((ps << 2) | romloc) {
-	case 0x00:
-	case 0x01:
-		rcw_pagesize = 512;
-		rcw_sparesize = 16;
-		break;
-	case 0x02:
-	case 0x03:
-		rcw_pagesize = 4096;
-		rcw_sparesize = 128;
-		break;
-	case 0x04:
-	case 0x05:
-		rcw_pagesize = 2048;
-		rcw_sparesize = 64;
-		break;
-	case 0x06:
-	case 0x07:
-		rcw_pagesize = 4096;
-		rcw_sparesize = 218;
-		break;
-	}
-
-	mtd->writesize = rcw_pagesize;
-	mtd->oobsize = rcw_sparesize;
-	if (rcw_width == 2)
-		chip->options |= NAND_BUSWIDTH_16;
-
-	debug(KERN_NOTICE DRV_NAME ": Configured for "
-	      "%u-bit NAND, page size %u with %u spare.\n",
-	      rcw_width * 8, rcw_pagesize, rcw_sparesize);
-	return 0;
-}
-
-int board_nand_init(struct nand_chip *chip)
-{
-	struct mpc5121_nfc_prv *prv;
-	struct mtd_info *mtd;
-	int resettime = 0;
-	int retval = 0;
-	int rev;
-
-	/*
-	 * Check SoC revision. This driver supports only NFC
-	 * in MPC5121 revision 2.
-	 */
-	rev = (mfspr(SPRN_SVR) >> 4) & 0xF;
-	if (rev != 2) {
-		printk(KERN_ERR DRV_NAME
-		       ": SoC revision %u is not supported!\n", rev);
-		return -ENXIO;
-	}
-
-	prv = malloc(sizeof(*prv));
-	if (!prv) {
-		printk(KERN_ERR DRV_NAME ": Memory exhausted!\n");
-		return -ENOMEM;
-	}
-
-	mtd = &chip->mtd;
-	nand_set_controller_data(chip, prv);
-
-	/* Read NFC configuration from Reset Config Word */
-	retval = mpc5121_nfc_read_hw_config(mtd);
-	if (retval) {
-		printk(KERN_ERR DRV_NAME ": Unable to read NFC config!\n");
-		return retval;
-	}
-
-	prv->regs = (void __iomem *)CONFIG_SYS_NAND_BASE;
-	chip->dev_ready = mpc5121_nfc_dev_ready;
-	chip->cmdfunc = mpc5121_nfc_command;
-	chip->read_byte = mpc5121_nfc_read_byte;
-	chip->read_word = mpc5121_nfc_read_word;
-	chip->read_buf = mpc5121_nfc_read_buf;
-	chip->write_buf = mpc5121_nfc_write_buf;
-	chip->select_chip = mpc5121_nfc_select_chip;
-	chip->bbt_options = NAND_BBT_USE_FLASH;
-	chip->ecc.mode = NAND_ECC_SOFT;
-
-	/* Reset NAND Flash controller */
-	nfc_set(mtd, NFC_CONFIG1, NFC_RESET);
-	while (nfc_read(mtd, NFC_CONFIG1) & NFC_RESET) {
-		if (resettime++ >= NFC_RESET_TIMEOUT) {
-			printk(KERN_ERR DRV_NAME
-			       ": Timeout while resetting NFC!\n");
-			retval = -EINVAL;
-			goto error;
-		}
-
-		udelay(1);
-	}
-
-	/* Enable write to NFC memory */
-	nfc_write(mtd, NFC_CONFIG, NFC_BLS_UNLOCKED);
-
-	/* Enable write to all NAND pages */
-	nfc_write(mtd, NFC_UNLOCKSTART_BLK0, 0x0000);
-	nfc_write(mtd, NFC_UNLOCKEND_BLK0, 0xFFFF);
-	nfc_write(mtd, NFC_WRPROT, NFC_WPC_UNLOCK);
-
-	/*
-	 * Setup NFC:
-	 *      - Big Endian transfers,
-	 *      - Interrupt after full page read/write.
-	 */
-	nfc_write(mtd, NFC_CONFIG1, NFC_BIG_ENDIAN | NFC_INT_MASK |
-		  NFC_FULL_PAGE_INT);
-
-	/* Set spare area size */
-	nfc_write(mtd, NFC_SPAS, mtd->oobsize >> 1);
-
-	/* Detect NAND chips */
-	if (nand_scan(mtd, 1)) {
-		printk(KERN_ERR DRV_NAME ": NAND Flash not found !\n");
-		retval = -ENXIO;
-		goto error;
-	}
-
-	/* Set erase block size */
-	switch (mtd->erasesize / mtd->writesize) {
-	case 32:
-		nfc_set(mtd, NFC_CONFIG1, NFC_PPB_32);
-		break;
-
-	case 64:
-		nfc_set(mtd, NFC_CONFIG1, NFC_PPB_64);
-		break;
-
-	case 128:
-		nfc_set(mtd, NFC_CONFIG1, NFC_PPB_128);
-		break;
-
-	case 256:
-		nfc_set(mtd, NFC_CONFIG1, NFC_PPB_256);
-		break;
-
-	default:
-		printk(KERN_ERR DRV_NAME ": Unsupported NAND flash!\n");
-		retval = -ENXIO;
-		goto error;
-	}
-
-	return 0;
-error:
-	return retval;
-}
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 0aaac6bd81..03ed224cea 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -39,8 +39,6 @@ obj-$(CONFIG_LAN91C96) += lan91c96.o
 obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o
 obj-$(CONFIG_MACB) += macb.o
 obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
-obj-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
-obj-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o
 obj-$(CONFIG_MVGBE) += mvgbe.o
 obj-$(CONFIG_MVNETA) += mvneta.o
 obj-$(CONFIG_MVPP2) += mvpp2.o
diff --git a/drivers/net/mpc512x_fec.c b/drivers/net/mpc512x_fec.c
deleted file mode 100644
index a18b959425..0000000000
--- a/drivers/net/mpc512x_fec.c
+++ /dev/null
@@ -1,769 +0,0 @@
-/*
- * (C) Copyright 2003-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Derived from the MPC8xx FEC driver.
- * Adapted for MPC512x by Grzegorz Bernacki <gjb@semihalf.com>
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <netdev.h>
-#include <miiphy.h>
-#include <asm/io.h>
-#include "mpc512x_fec.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define DEBUG 0
-
-#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
-#error "CONFIG_MII has to be defined!"
-#endif
-
-int fec512x_miiphy_read(struct mii_dev *bus, int phyAddr, int devad,
-			int regAddr);
-int fec512x_miiphy_write(struct mii_dev *bus, int phyAddr, int devad,
-			 int regAddr, u16 data);
-int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis);
-
-static uchar rx_buff[FEC_BUFFER_SIZE];
-static int rx_buff_idx = 0;
-
-/********************************************************************/
-#if (DEBUG & 0x2)
-static void mpc512x_fec_phydump (char *devname)
-{
-	u16 phyStatus, i;
-	u8 phyAddr = CONFIG_PHY_ADDR;
-	u8 reg_mask[] = {
-		/* regs to print: 0...8, 21,27,31 */
-		1, 1, 1, 1,  1, 1, 1, 1,     1, 0, 0, 0,  0, 0, 0, 0,
-		0, 0, 0, 0,  0, 1, 0, 0,     0, 0, 0, 1,  0, 0, 0, 1,
-	};
-
-	for (i = 0; i < 32; i++) {
-		if (reg_mask[i]) {
-			miiphy_read (devname, phyAddr, i, &phyStatus);
-			printf ("Mii reg %d: 0x%04x\n", i, phyStatus);
-		}
-	}
-}
-#endif
-
-/********************************************************************/
-static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec)
-{
-	int ix;
-
-	/*
-	 * Receive BDs init
-	 */
-	for (ix = 0; ix < FEC_RBD_NUM; ix++) {
-		fec->bdBase->rbd[ix].dataPointer =
-				(u32)&fec->bdBase->recv_frames[ix];
-		fec->bdBase->rbd[ix].status = FEC_RBD_EMPTY;
-		fec->bdBase->rbd[ix].dataLength = 0;
-	}
-
-	/*
-	 * have the last RBD to close the ring
-	 */
-	fec->bdBase->rbd[ix - 1].status |= FEC_RBD_WRAP;
-	fec->rbdIndex = 0;
-
-	/*
-	 * Trasmit BDs init
-	 */
-	for (ix = 0; ix < FEC_TBD_NUM; ix++) {
-		fec->bdBase->tbd[ix].status = 0;
-	}
-
-	/*
-	 * Have the last TBD to close the ring
-	 */
-	fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP;
-
-	/*
-	 * Initialize some indices
-	 */
-	fec->tbdIndex = 0;
-	fec->usedTbdIndex = 0;
-	fec->cleanTbdNum = FEC_TBD_NUM;
-
-	return 0;
-}
-
-/********************************************************************/
-static void mpc512x_fec_rbd_clean (mpc512x_fec_priv *fec, volatile FEC_RBD * pRbd)
-{
-	/*
-	 * Reset buffer descriptor as empty
-	 */
-	if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
-		pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
-	else
-		pRbd->status = FEC_RBD_EMPTY;
-
-	pRbd->dataLength = 0;
-
-	/*
-	 * Increment BD count
-	 */
-	fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
-
-	/*
-	 * Now, we have an empty RxBD, notify FEC
-	 * Set Descriptor polling active
-	 */
-	out_be32(&fec->eth->r_des_active, 0x01000000);
-}
-
-/********************************************************************/
-static void mpc512x_fec_tbd_scrub (mpc512x_fec_priv *fec)
-{
-	volatile FEC_TBD *pUsedTbd;
-
-#if (DEBUG & 0x1)
-	printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
-		fec->cleanTbdNum, fec->usedTbdIndex);
-#endif
-
-	/*
-	 * process all the consumed TBDs
-	 */
-	while (fec->cleanTbdNum < FEC_TBD_NUM) {
-		pUsedTbd = &fec->bdBase->tbd[fec->usedTbdIndex];
-		if (pUsedTbd->status & FEC_TBD_READY) {
-#if (DEBUG & 0x20)
-			printf ("Cannot clean TBD %d, in use\n", fec->usedTbdIndex);
-#endif
-			return;
-		}
-
-		/*
-		 * clean this buffer descriptor
-		 */
-		if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
-			pUsedTbd->status = FEC_TBD_WRAP;
-		else
-			pUsedTbd->status = 0;
-
-		/*
-		 * update some indeces for a correct handling of the TBD ring
-		 */
-		fec->cleanTbdNum++;
-		fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
-	}
-}
-
-/********************************************************************/
-static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, unsigned char *mac)
-{
-	u8 currByte;			/* byte for which to compute the CRC */
-	int byte;			/* loop - counter */
-	int bit;			/* loop - counter */
-	u32 crc = 0xffffffff;		/* initial value */
-
-	/*
-	 * The algorithm used is the following:
-	 * we loop on each of the six bytes of the provided address,
-	 * and we compute the CRC by left-shifting the previous
-	 * value by one position, so that each bit in the current
-	 * byte of the address may contribute the calculation. If
-	 * the latter and the MSB in the CRC are different, then
-	 * the CRC value so computed is also ex-ored with the
-	 * "polynomium generator". The current byte of the address
-	 * is also shifted right by one bit at each iteration.
-	 * This is because the CRC generatore in hardware is implemented
-	 * as a shift-register with as many ex-ores as the radixes
-	 * in the polynomium. This suggests that we represent the
-	 * polynomiumm itself as a 32-bit constant.
-	 */
-	for (byte = 0; byte < 6; byte++) {
-		currByte = mac[byte];
-		for (bit = 0; bit < 8; bit++) {
-			if ((currByte & 0x01) ^ (crc & 0x01)) {
-				crc >>= 1;
-				crc = crc ^ 0xedb88320;
-			} else {
-				crc >>= 1;
-			}
-			currByte >>= 1;
-		}
-	}
-
-	crc = crc >> 26;
-
-	/*
-	 * Set individual hash table register
-	 */
-	if (crc >= 32) {
-		out_be32(&fec->eth->iaddr1, (1 << (crc - 32)));
-		out_be32(&fec->eth->iaddr2, 0);
-	} else {
-		out_be32(&fec->eth->iaddr1, 0);
-		out_be32(&fec->eth->iaddr2, (1 << crc));
-	}
-
-	/*
-	 * Set physical address
-	 */
-	out_be32(&fec->eth->paddr1, (mac[0] << 24) + (mac[1] << 16) +
-				    (mac[2] <<  8) + mac[3]);
-	out_be32(&fec->eth->paddr2, (mac[4] << 24) + (mac[5] << 16) +
-				     0x8808);
-}
-
-/********************************************************************/
-static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
-{
-	mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
-
-#if (DEBUG & 0x1)
-	printf ("mpc512x_fec_init... Begin\n");
-#endif
-
-	mpc512x_fec_set_hwaddr (fec, dev->enetaddr);
-	out_be32(&fec->eth->gaddr1, 0x00000000);
-	out_be32(&fec->eth->gaddr2, 0x00000000);
-
-	mpc512x_fec_init_phy (dev, bis);
-
-	/* Set interrupt mask register */
-	out_be32(&fec->eth->imask, 0x00000000);
-
-	/* Clear FEC-Lite interrupt event register(IEVENT) */
-	out_be32(&fec->eth->ievent, 0xffffffff);
-
-	/* Set transmit fifo watermark register(X_WMRK), default = 64 */
-	out_be32(&fec->eth->x_wmrk, 0x0);
-
-	/* Set Opcode/Pause Duration Register */
-	out_be32(&fec->eth->op_pause, 0x00010020);
-
-	/* Frame length=1522; MII mode */
-	out_be32(&fec->eth->r_cntrl, (FEC_MAX_FRAME_LEN << 16) | 0x24);
-
-	/* Half-duplex, heartbeat disabled */
-	out_be32(&fec->eth->x_cntrl, 0x00000000);
-
-	/* Enable MIB counters */
-	out_be32(&fec->eth->mib_control, 0x0);
-
-	/* Setup recv fifo start and buff size */
-	out_be32(&fec->eth->r_fstart, 0x500);
-	out_be32(&fec->eth->r_buff_size, FEC_BUFFER_SIZE);
-
-	/* Setup BD base addresses */
-	out_be32(&fec->eth->r_des_start, (u32)fec->bdBase->rbd);
-	out_be32(&fec->eth->x_des_start, (u32)fec->bdBase->tbd);
-
-	/* DMA Control */
-	out_be32(&fec->eth->dma_control, 0xc0000000);
-
-	/* Enable FEC */
-	setbits_be32(&fec->eth->ecntrl, 0x00000006);
-
-	/* Initilize addresses and status words of BDs */
-	mpc512x_fec_bd_init (fec);
-
-	 /* Descriptor polling active */
-	out_be32(&fec->eth->r_des_active, 0x01000000);
-
-#if (DEBUG & 0x1)
-	printf("mpc512x_fec_init... Done \n");
-#endif
-	return 1;
-}
-
-/********************************************************************/
-int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
-{
-	mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
-	const u8 phyAddr = CONFIG_PHY_ADDR;	/* Only one PHY */
-	int timeout = 1;
-	u16 phyStatus;
-
-#if (DEBUG & 0x1)
-	printf ("mpc512x_fec_init_phy... Begin\n");
-#endif
-
-	/*
-	 * Clear FEC-Lite interrupt event register(IEVENT)
-	 */
-	out_be32(&fec->eth->ievent, 0xffffffff);
-
-	/*
-	 * Set interrupt mask register
-	 */
-	out_be32(&fec->eth->imask, 0x00000000);
-
-	if (fec->xcv_type != SEVENWIRE) {
-		/*
-		 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
-		 * and do not drop the Preamble.
-		 */
-		out_be32(&fec->eth->mii_speed,
-			 (((gd->arch.ips_clk / 1000000) / 5) + 1) << 1);
-
-		/*
-		 * Reset PHY, then delay 300ns
-		 */
-		miiphy_write (dev->name, phyAddr, 0x0, 0x8000);
-		udelay (1000);
-
-		if (fec->xcv_type == MII10) {
-		/*
-		 * Force 10Base-T, FDX operation
-		 */
-#if (DEBUG & 0x2)
-			printf ("Forcing 10 Mbps ethernet link... ");
-#endif
-			miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
-
-			miiphy_write (dev->name, phyAddr, 0x0, 0x0180);
-
-			timeout = 20;
-			do {    /* wait for link status to go down */
-				udelay (10000);
-				if ((timeout--) == 0) {
-#if (DEBUG & 0x2)
-					printf ("hmmm, should not have waited...");
-#endif
-					break;
-				}
-				miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
-#if (DEBUG & 0x2)
-				printf ("=");
-#endif
-			} while ((phyStatus & 0x0004)); /* !link up */
-
-			timeout = 1000;
-			do {    /* wait for link status to come back up */
-				udelay (10000);
-				if ((timeout--) == 0) {
-					printf ("failed. Link is down.\n");
-					break;
-				}
-				miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
-#if (DEBUG & 0x2)
-				printf ("+");
-#endif
-			} while (!(phyStatus & 0x0004)); /* !link up */
-
-#if (DEBUG & 0x2)
-			printf ("done.\n");
-#endif
-		} else {	/* MII100 */
-			/*
-			 * Set the auto-negotiation advertisement register bits
-			 */
-			miiphy_write (dev->name, phyAddr, 0x4, 0x01e1);
-
-			/*
-			 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
-			 */
-			miiphy_write (dev->name, phyAddr, 0x0, 0x1200);
-
-			/*
-			 * Wait for AN completion
-			 */
-			timeout = 2500;
-			do {
-				udelay (1000);
-
-				if ((timeout--) == 0) {
-#if (DEBUG & 0x2)
-					printf ("PHY auto neg 0 failed...\n");
-#endif
-					return -1;
-				}
-
-				if (miiphy_read (dev->name, phyAddr, 0x1, &phyStatus) != 0) {
-#if (DEBUG & 0x2)
-					printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
-#endif
-					return -1;
-				}
-			} while (!(phyStatus & 0x0004));
-
-#if (DEBUG & 0x2)
-			printf ("PHY auto neg complete! \n");
-#endif
-		}
-	}
-
-#if (DEBUG & 0x2)
-	if (fec->xcv_type != SEVENWIRE)
-		mpc512x_fec_phydump (dev->name);
-#endif
-
-#if (DEBUG & 0x1)
-	printf ("mpc512x_fec_init_phy... Done \n");
-#endif
-	return 1;
-}
-
-/********************************************************************/
-static void mpc512x_fec_halt (struct eth_device *dev)
-{
-	mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
-	int counter = 0xffff;
-
-#if (DEBUG & 0x2)
-	if (fec->xcv_type != SEVENWIRE)
-		mpc512x_fec_phydump (dev->name);
-#endif
-
-	/*
-	 * mask FEC chip interrupts
-	 */
-	out_be32(&fec->eth->imask, 0);
-
-	/*
-	 * issue graceful stop command to the FEC transmitter if necessary
-	 */
-	setbits_be32(&fec->eth->x_cntrl, 0x00000001);
-
-	/*
-	 * wait for graceful stop to register
-	 */
-	while ((counter--) && (!(in_be32(&fec->eth->ievent) & 0x10000000)))
-		;
-
-	/*
-	 * Disable the Ethernet Controller
-	 */
-	clrbits_be32(&fec->eth->ecntrl, 0x00000002);
-
-	/*
-	 * Issue a reset command to the FEC chip
-	 */
-	setbits_be32(&fec->eth->ecntrl, 0x1);
-
-	/*
-	 * wait at least 16 clock cycles
-	 */
-	udelay (10);
-#if (DEBUG & 0x3)
-	printf ("Ethernet task stopped\n");
-#endif
-}
-
-/********************************************************************/
-
-static int mpc512x_fec_send(struct eth_device *dev, void *eth_data,
-			    int data_length)
-{
-	/*
-	 * This routine transmits one frame.  This routine only accepts
-	 * 6-byte Ethernet addresses.
-	 */
-	mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
-	volatile FEC_TBD *pTbd;
-
-#if (DEBUG & 0x20)
-	printf("tbd status: 0x%04x\n", fec->tbdBase[fec->tbdIndex].status);
-#endif
-
-	/*
-	 * Clear Tx BD ring at first
-	 */
-	mpc512x_fec_tbd_scrub (fec);
-
-	/*
-	 * Check for valid length of data.
-	 */
-	if ((data_length > 1500) || (data_length <= 0)) {
-		return -1;
-	}
-
-	/*
-	 * Check the number of vacant TxBDs.
-	 */
-	if (fec->cleanTbdNum < 1) {
-#if (DEBUG & 0x20)
-		printf ("No available TxBDs ...\n");
-#endif
-		return -1;
-	}
-
-	/*
-	 * Get the first TxBD to send the mac header
-	 */
-	pTbd = &fec->bdBase->tbd[fec->tbdIndex];
-	pTbd->dataLength = data_length;
-	pTbd->dataPointer = (u32)eth_data;
-	pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
-	fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
-
-	/* Activate transmit Buffer Descriptor polling */
-	out_be32(&fec->eth->x_des_active, 0x01000000);
-
-#if (DEBUG & 0x8)
-	printf ( "+" );
-#endif
-
-	fec->cleanTbdNum -= 1;
-
-	/*
-	 * wait until frame is sent .
-	 */
-	while (pTbd->status & FEC_TBD_READY) {
-		udelay (10);
-#if (DEBUG & 0x8)
-		printf ("TDB status = %04x\n", pTbd->status);
-#endif
-	}
-
-	return 0;
-}
-
-
-/********************************************************************/
-static int mpc512x_fec_recv (struct eth_device *dev)
-{
-	/*
-	 * This command pulls one frame from the card
-	 */
-	mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
-	volatile FEC_RBD *pRbd = &fec->bdBase->rbd[fec->rbdIndex];
-	unsigned long ievent;
-	int frame_length = 0;
-
-#if (DEBUG & 0x1)
-	printf ("mpc512x_fec_recv %d Start...\n", fec->rbdIndex);
-#endif
-#if (DEBUG & 0x8)
-	printf( "-" );
-#endif
-
-	/*
-	 * Check if any critical events have happened
-	 */
-	ievent = in_be32(&fec->eth->ievent);
-	out_be32(&fec->eth->ievent, ievent);
-	if (ievent & 0x20060000) {
-		/* BABT, Rx/Tx FIFO errors */
-		mpc512x_fec_halt (dev);
-		mpc512x_fec_init (dev, NULL);
-		return 0;
-	}
-	if (ievent & 0x80000000) {
-		/* Heartbeat error */
-		setbits_be32(&fec->eth->x_cntrl, 0x00000001);
-	}
-	if (ievent & 0x10000000) {
-		/* Graceful stop complete */
-		if (in_be32(&fec->eth->x_cntrl) & 0x00000001) {
-			mpc512x_fec_halt (dev);
-			clrbits_be32(&fec->eth->x_cntrl, 0x00000001);
-			mpc512x_fec_init (dev, NULL);
-		}
-	}
-
-	if (!(pRbd->status & FEC_RBD_EMPTY)) {
-		if (!(pRbd->status & FEC_RBD_ERR) &&
-			((pRbd->dataLength - 4) > 14)) {
-
-			/*
-			 * Get buffer size
-			 */
-			if (pRbd->status & FEC_RBD_LAST)
-				frame_length = pRbd->dataLength - 4;
-			else
-				frame_length = pRbd->dataLength;
-#if (DEBUG & 0x20)
-			{
-				int i;
-				printf ("recv data length 0x%08x data hdr: ",
-					pRbd->dataLength);
-				for (i = 0; i < 14; i++)
-					printf ("%x ", *((u8*)pRbd->dataPointer + i));
-				printf("\n");
-			}
-#endif
-			/*
-			 *  Fill the buffer and pass it to upper layers
-			 */
-			memcpy (&rx_buff[rx_buff_idx], (void*)pRbd->dataPointer,
-				frame_length - rx_buff_idx);
-			rx_buff_idx = frame_length;
-
-			if (pRbd->status & FEC_RBD_LAST) {
-				net_process_received_packet((uchar *)rx_buff,
-							    frame_length);
-				rx_buff_idx = 0;
-			}
-		}
-
-		/*
-		 * Reset buffer descriptor as empty
-		 */
-		mpc512x_fec_rbd_clean (fec, pRbd);
-	}
-
-	/* Try to fill Buffer Descriptors */
-	out_be32(&fec->eth->r_des_active, 0x01000000);
-
-	return frame_length;
-}
-
-/********************************************************************/
-int mpc512x_fec_initialize (bd_t * bis)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	mpc512x_fec_priv *fec;
-	struct eth_device *dev;
-	void * bd;
-
-	fec = (mpc512x_fec_priv *) malloc (sizeof(*fec));
-	dev = (struct eth_device *) malloc (sizeof(*dev));
-	memset (dev, 0, sizeof *dev);
-
-	fec->eth = &im->fec;
-
-# ifndef CONFIG_FEC_10MBIT
-	fec->xcv_type = MII100;
-# else
-	fec->xcv_type = MII10;
-# endif
-	dev->priv = (void *)fec;
-	dev->iobase = (int)&im->fec;
-	dev->init = mpc512x_fec_init;
-	dev->halt = mpc512x_fec_halt;
-	dev->send = mpc512x_fec_send;
-	dev->recv = mpc512x_fec_recv;
-
-	strcpy(dev->name, "FEC");
-	eth_register (dev);
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-	int retval;
-	struct mii_dev *mdiodev = mdio_alloc();
-	if (!mdiodev)
-		return -ENOMEM;
-	strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
-	mdiodev->read = fec512x_miiphy_read;
-	mdiodev->write = fec512x_miiphy_write;
-
-	retval = mdio_register(mdiodev);
-	if (retval < 0)
-		return retval;
-#endif
-
-	/* Clean up space FEC's MIB and FIFO RAM ...*/
-	memset ((void *)&im->fec.mib,  0x00, sizeof(im->fec.mib));
-	memset ((void *)&im->fec.fifo, 0x00, sizeof(im->fec.fifo));
-
-	/*
-	 * Malloc space for BDs  (must be quad word-aligned)
-	 * this pointer is lost, so cannot be freed
-	 */
-	bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f);
-	fec->bdBase = (mpc512x_buff_descs*)((u32)bd & 0xfffffff0);
-	memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f);
-
-	/*
-	 * Set interrupt mask register
-	 */
-	out_be32(&fec->eth->imask, 0x00000000);
-
-	/*
-	 * Clear FEC-Lite interrupt event register(IEVENT)
-	 */
-	out_be32(&fec->eth->ievent, 0xffffffff);
-
-	return 1;
-}
-
-/* MII-interface related functions */
-/********************************************************************/
-int fec512x_miiphy_read(struct mii_dev *bus, int phyAddr, int devad,
-			int regAddr)
-{
-	u16 retVal = 0;
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile fec512x_t *eth = &im->fec;
-	u32 reg;		/* convenient holder for the PHY register */
-	u32 phy;		/* convenient holder for the PHY */
-	int timeout = 0xffff;
-
-	/*
-	 * reading from any PHY's register is done by properly
-	 * programming the FEC's MII data register.
-	 */
-	reg = regAddr << FEC_MII_DATA_RA_SHIFT;
-	phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
-
-	out_be32(&eth->mii_data, FEC_MII_DATA_ST |
-				 FEC_MII_DATA_OP_RD |
-				 FEC_MII_DATA_TA |
-				 phy | reg);
-
-	/*
-	 * wait for the related interrupt
-	 */
-	while ((timeout--) && (!(in_be32(&eth->ievent) & 0x00800000)))
-		;
-
-	if (timeout == 0) {
-#if (DEBUG & 0x2)
-		printf ("Read MDIO failed...\n");
-#endif
-		return -1;
-	}
-
-	/*
-	 * clear mii interrupt bit
-	 */
-	out_be32(&eth->ievent, 0x00800000);
-
-	/*
-	 * it's now safe to read the PHY's register
-	 */
-	retVal = (u16) in_be32(&eth->mii_data);
-
-	return retVal;
-}
-
-/********************************************************************/
-int fec512x_miiphy_write(struct mii_dev *bus, int phyAddr, int devad,
-			 int regAddr, u16 data)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile fec512x_t *eth = &im->fec;
-	u32 reg;		/* convenient holder for the PHY register */
-	u32 phy;		/* convenient holder for the PHY */
-	int timeout = 0xffff;
-
-	reg = regAddr << FEC_MII_DATA_RA_SHIFT;
-	phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
-
-	out_be32(&eth->mii_data, FEC_MII_DATA_ST |
-				 FEC_MII_DATA_OP_WR |
-				 FEC_MII_DATA_TA |
-				 phy | reg | data);
-
-	/*
-	 * wait for the MII interrupt
-	 */
-	while ((timeout--) && (!(in_be32(&eth->ievent) & 0x00800000)))
-		;
-
-	if (timeout == 0) {
-#if (DEBUG & 0x2)
-		printf ("Write MDIO failed...\n");
-#endif
-		return -1;
-	}
-
-	/*
-	 * clear MII interrupt bit
-	 */
-	out_be32(&eth->ievent, 0x00800000);
-
-	return 0;
-}
diff --git a/drivers/net/mpc512x_fec.h b/drivers/net/mpc512x_fec.h
deleted file mode 100644
index a083cca2f8..0000000000
--- a/drivers/net/mpc512x_fec.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * (C) Copyright 2003 - 2009
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Derived from the MPC8xx driver's header file.
- */
-
-#ifndef __MPC512X_FEC_H
-#define __MPC512X_FEC_H
-
-#include <common.h>
-
-/* Receive & Transmit Buffer Descriptor definitions */
-typedef struct BufferDescriptor {
-	u16 status;
-	u16 dataLength;
-	u32 dataPointer;
-} FEC_RBD;
-
-typedef struct {
-	u16 status;
-	u16 dataLength;
-	u32 dataPointer;
-} FEC_TBD;
-
-/* private structure */
-typedef enum {
-	SEVENWIRE,			/* 7-wire       */
-	MII10,				/* MII 10Mbps   */
-	MII100				/* MII 100Mbps  */
-} xceiver_type;
-
-/* BD Numer definitions */
-#define FEC_TBD_NUM		48	/* The user can adjust this value */
-#define FEC_RBD_NUM		32	/* The user can adjust this value */
-
-/* packet size limit */
-#define FEC_MAX_FRAME_LEN	1522	/* recommended default value */
-
-/* Buffer size must be evenly divisible by 16 */
-#define FEC_BUFFER_SIZE		((FEC_MAX_FRAME_LEN + 0x10) & (~0xf))
-
-typedef struct {
-	u8 frame[FEC_BUFFER_SIZE];
-} mpc512x_frame;
-
-typedef struct {
-	FEC_RBD rbd[FEC_RBD_NUM];			/* RBD ring */
-	FEC_TBD tbd[FEC_TBD_NUM];			/* TBD ring */
-	mpc512x_frame recv_frames[FEC_RBD_NUM];		/* receive buff */
-} mpc512x_buff_descs;
-
-typedef struct {
-	volatile fec512x_t *eth;
-	xceiver_type xcv_type;		/* transceiver type */
-	mpc512x_buff_descs *bdBase;	/* BD rings and recv buffer */
-	u16 rbdIndex;			/* next receive BD to read */
-	u16 tbdIndex;			/* next transmit BD to send */
-	u16 usedTbdIndex;		/* next transmit BD to clean */
-	u16 cleanTbdNum;		/* the number of available transmit BDs */
-} mpc512x_fec_priv;
-
-/* RBD bits definitions */
-#define FEC_RBD_EMPTY		0x8000	/* Buffer is empty */
-#define FEC_RBD_WRAP		0x2000	/* Last BD in ring */
-#define FEC_RBD_LAST		0x0800	/* Buffer is last in frame(useless) */
-#define FEC_RBD_MISS		0x0100	/* Miss bit for prom mode */
-#define FEC_RBD_BC		0x0080	/* The received frame is broadcast frame */
-#define FEC_RBD_MC		0x0040	/* The received frame is multicast frame */
-#define FEC_RBD_LG		0x0020	/* Frame length violation */
-#define FEC_RBD_NO		0x0010	/* Nonoctet align frame */
-#define FEC_RBD_SH		0x0008	/* Short frame */
-#define FEC_RBD_CR		0x0004	/* CRC error */
-#define FEC_RBD_OV		0x0002	/* Receive FIFO overrun */
-#define FEC_RBD_TR		0x0001	/* Frame is truncated */
-#define FEC_RBD_ERR		(FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \
-				FEC_RBD_OV | FEC_RBD_TR)
-
-/* TBD bits definitions */
-#define FEC_TBD_READY		0x8000	/* Buffer is ready */
-#define FEC_TBD_WRAP		0x2000	/* Last BD in ring */
-#define FEC_TBD_LAST		0x0800	/* Buffer is last in frame */
-#define FEC_TBD_TC		0x0400	/* Transmit the CRC */
-#define FEC_TBD_ABC		0x0200	/* Append bad CRC */
-
-/* MII-related definitios */
-#define FEC_MII_DATA_ST		0x40000000	/* Start of frame delimiter */
-#define FEC_MII_DATA_OP_RD	0x20000000	/* Perform a read operation */
-#define FEC_MII_DATA_OP_WR	0x10000000	/* Perform a write operation */
-#define FEC_MII_DATA_PA_MSK	0x0f800000	/* PHY Address field mask */
-#define FEC_MII_DATA_RA_MSK	0x007c0000	/* PHY Register field mask */
-#define FEC_MII_DATA_TA		0x00020000	/* Turnaround */
-#define FEC_MII_DATA_DATAMSK	0x0000ffff	/* PHY data field */
-
-#define FEC_MII_DATA_RA_SHIFT	18	/* MII Register address bits */
-#define FEC_MII_DATA_PA_SHIFT	23	/* MII PHY address bits */
-
-#endif	/* __MPC512X_FEC_H */
diff --git a/drivers/net/mpc5xxx_fec.c b/drivers/net/mpc5xxx_fec.c
deleted file mode 100644
index d75e858a38..0000000000
--- a/drivers/net/mpc5xxx_fec.c
+++ /dev/null
@@ -1,1031 +0,0 @@
-/*
- * (C) Copyright 2003-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * This file is based on mpc4200fec.c,
- * (C) Copyright Motorola, Inc., 2000
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <mpc5xxx_sdma.h>
-#include <malloc.h>
-#include <net.h>
-#include <netdev.h>
-#include <miiphy.h>
-#include "mpc5xxx_fec.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* #define DEBUG	0x28 */
-
-#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
-#error "CONFIG_MII has to be defined!"
-#endif
-
-#if (DEBUG & 0x60)
-static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec);
-static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec);
-#endif /* DEBUG */
-
-typedef struct {
-    uint8 data[1500];           /* actual data */
-    int length;                 /* actual length */
-    int used;                   /* buffer in use or not */
-    uint8 head[16];             /* MAC header(6 + 6 + 2) + 2(aligned) */
-} NBUF;
-
-int fec5xxx_miiphy_read(struct mii_dev *bus, int phyAddr, int devad,
-			int regAddr);
-int fec5xxx_miiphy_write(struct mii_dev *bus, int phyAddr, int devad,
-			 int regAddr, u16 data);
-
-static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis);
-
-/********************************************************************/
-#if (DEBUG & 0x2)
-static void mpc5xxx_fec_phydump (char *devname)
-{
-	uint16 phyStatus, i;
-	uint8 phyAddr = CONFIG_PHY_ADDR;
-	uint8 reg_mask[] = {
-#if CONFIG_PHY_TYPE == 0x79c874	/* AMD Am79C874 */
-		/* regs to print: 0...7, 16...19, 21, 23, 24 */
-		1, 1, 1, 1,  1, 1, 1, 1,     0, 0, 0, 0,  0, 0, 0, 0,
-		1, 1, 1, 1,  0, 1, 0, 1,     1, 0, 0, 0,  0, 0, 0, 0,
-#else
-		/* regs to print: 0...8, 16...20 */
-		1, 1, 1, 1,  1, 1, 1, 1,     1, 0, 0, 0,  0, 0, 0, 0,
-		1, 1, 1, 1,  1, 0, 0, 0,     0, 0, 0, 0,  0, 0, 0, 0,
-#endif
-	};
-
-	for (i = 0; i < 32; i++) {
-		if (reg_mask[i]) {
-			miiphy_read(devname, phyAddr, i, &phyStatus);
-			printf("Mii reg %d: 0x%04x\n", i, phyStatus);
-		}
-	}
-}
-#endif
-
-/********************************************************************/
-static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
-{
-	int ix;
-	char *data;
-	static int once = 0;
-
-	for (ix = 0; ix < FEC_RBD_NUM; ix++) {
-		if (!once) {
-			data = (char *)malloc(FEC_MAX_PKT_SIZE);
-			if (data == NULL) {
-				printf ("RBD INIT FAILED\n");
-				return -1;
-			}
-			fec->rbdBase[ix].dataPointer = (uint32)data;
-		}
-		fec->rbdBase[ix].status = FEC_RBD_EMPTY;
-		fec->rbdBase[ix].dataLength = 0;
-	}
-	once ++;
-
-	/*
-	 * have the last RBD to close the ring
-	 */
-	fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
-	fec->rbdIndex = 0;
-
-	return 0;
-}
-
-/********************************************************************/
-static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
-{
-	int ix;
-
-	for (ix = 0; ix < FEC_TBD_NUM; ix++) {
-		fec->tbdBase[ix].status = 0;
-	}
-
-	/*
-	 * Have the last TBD to close the ring
-	 */
-	fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
-
-	/*
-	 * Initialize some indices
-	 */
-	fec->tbdIndex = 0;
-	fec->usedTbdIndex = 0;
-	fec->cleanTbdNum = FEC_TBD_NUM;
-}
-
-/********************************************************************/
-static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd)
-{
-	/*
-	 * Reset buffer descriptor as empty
-	 */
-	if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
-		pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
-	else
-		pRbd->status = FEC_RBD_EMPTY;
-
-	pRbd->dataLength = 0;
-
-	/*
-	 * Now, we have an empty RxBD, restart the SmartDMA receive task
-	 */
-	SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
-
-	/*
-	 * Increment BD count
-	 */
-	fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
-}
-
-/********************************************************************/
-static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
-{
-	volatile FEC_TBD *pUsedTbd;
-
-#if (DEBUG & 0x1)
-	printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
-		fec->cleanTbdNum, fec->usedTbdIndex);
-#endif
-
-	/*
-	 * process all the consumed TBDs
-	 */
-	while (fec->cleanTbdNum < FEC_TBD_NUM) {
-		pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
-		if (pUsedTbd->status & FEC_TBD_READY) {
-#if (DEBUG & 0x20)
-			printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
-#endif
-			return;
-		}
-
-		/*
-		 * clean this buffer descriptor
-		 */
-		if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
-			pUsedTbd->status = FEC_TBD_WRAP;
-		else
-			pUsedTbd->status = 0;
-
-		/*
-		 * update some indeces for a correct handling of the TBD ring
-		 */
-		fec->cleanTbdNum++;
-		fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
-	}
-}
-
-/********************************************************************/
-static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
-{
-	uint8 currByte;			/* byte for which to compute the CRC */
-	int byte;			/* loop - counter */
-	int bit;			/* loop - counter */
-	uint32 crc = 0xffffffff;	/* initial value */
-
-	/*
-	 * The algorithm used is the following:
-	 * we loop on each of the six bytes of the provided address,
-	 * and we compute the CRC by left-shifting the previous
-	 * value by one position, so that each bit in the current
-	 * byte of the address may contribute the calculation. If
-	 * the latter and the MSB in the CRC are different, then
-	 * the CRC value so computed is also ex-ored with the
-	 * "polynomium generator". The current byte of the address
-	 * is also shifted right by one bit at each iteration.
-	 * This is because the CRC generatore in hardware is implemented
-	 * as a shift-register with as many ex-ores as the radixes
-	 * in the polynomium. This suggests that we represent the
-	 * polynomiumm itself as a 32-bit constant.
-	 */
-	for (byte = 0; byte < 6; byte++) {
-		currByte = mac[byte];
-		for (bit = 0; bit < 8; bit++) {
-			if ((currByte & 0x01) ^ (crc & 0x01)) {
-				crc >>= 1;
-				crc = crc ^ 0xedb88320;
-			} else {
-				crc >>= 1;
-			}
-			currByte >>= 1;
-		}
-	}
-
-	crc = crc >> 26;
-
-	/*
-	 * Set individual hash table register
-	 */
-	if (crc >= 32) {
-		fec->eth->iaddr1 = (1 << (crc - 32));
-		fec->eth->iaddr2 = 0;
-	} else {
-		fec->eth->iaddr1 = 0;
-		fec->eth->iaddr2 = (1 << crc);
-	}
-
-	/*
-	 * Set physical address
-	 */
-	fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
-	fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
-}
-
-/********************************************************************/
-static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
-{
-	mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
-	struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
-
-#if (DEBUG & 0x1)
-	printf ("mpc5xxx_fec_init... Begin\n");
-#endif
-
-	mpc5xxx_fec_init_phy(dev, bis);
-
-	/*
-	 * Call board-specific PHY fixups (if any)
-	 */
-#ifdef CONFIG_RESET_PHY_R
-	reset_phy();
-#endif
-
-	/*
-	 * Initialize RxBD/TxBD rings
-	 */
-	mpc5xxx_fec_rbd_init(fec);
-	mpc5xxx_fec_tbd_init(fec);
-
-	/*
-	 * Clear FEC-Lite interrupt event register(IEVENT)
-	 */
-	fec->eth->ievent = 0xffffffff;
-
-	/*
-	 * Set interrupt mask register
-	 */
-	fec->eth->imask = 0x00000000;
-
-	/*
-	 * Set FEC-Lite receive control register(R_CNTRL):
-	 */
-	if (fec->xcv_type == SEVENWIRE) {
-		/*
-		 * Frame length=1518; 7-wire mode
-		 */
-		fec->eth->r_cntrl = 0x05ee0020;	/*0x05ee0000;FIXME */
-	} else {
-		/*
-		 * Frame length=1518; MII mode;
-		 */
-		fec->eth->r_cntrl = 0x05ee0024;	/*0x05ee0004;FIXME */
-	}
-
-	fec->eth->x_cntrl = 0x00000000;	/* half-duplex, heartbeat disabled */
-
-	/*
-	 * Set Opcode/Pause Duration Register
-	 */
-	fec->eth->op_pause = 0x00010020;	/*FIXME 0xffff0020; */
-
-	/*
-	 * Set Rx FIFO alarm and granularity value
-	 */
-	fec->eth->rfifo_cntrl = 0x0c000000
-				| (fec->eth->rfifo_cntrl & ~0x0f000000);
-	fec->eth->rfifo_alarm = 0x0000030c;
-#if (DEBUG & 0x22)
-	if (fec->eth->rfifo_status & 0x00700000 ) {
-		printf("mpc5xxx_fec_init() RFIFO error\n");
-	}
-#endif
-
-	/*
-	 * Set Tx FIFO granularity value
-	 */
-	fec->eth->tfifo_cntrl = 0x0c000000
-				| (fec->eth->tfifo_cntrl & ~0x0f000000);
-#if (DEBUG & 0x2)
-	printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
-	printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
-#endif
-
-	/*
-	 * Set transmit fifo watermark register(X_WMRK), default = 64
-	 */
-	fec->eth->tfifo_alarm = 0x00000080;
-	fec->eth->x_wmrk = 0x2;
-
-	/*
-	 * Set individual address filter for unicast address
-	 * and set physical address registers.
-	 */
-	mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr);
-
-	/*
-	 * Set multicast address filter
-	 */
-	fec->eth->gaddr1 = 0x00000000;
-	fec->eth->gaddr2 = 0x00000000;
-
-	/*
-	 * Turn ON cheater FSM: ????
-	 */
-	fec->eth->xmit_fsm = 0x03000000;
-
-	/*
-	 * Turn off COMM bus prefetch in the MPC5200 BestComm. It doesn't
-	 * work w/ the current receive task.
-	 */
-	 sdma->PtdCntrl |= 0x00000001;
-
-	/*
-	 * Set priority of different initiators
-	 */
-	sdma->IPR0 = 7;		/* always */
-	sdma->IPR3 = 6;		/* Eth RX */
-	sdma->IPR4 = 5;		/* Eth Tx */
-
-	/*
-	 * Clear SmartDMA task interrupt pending bits
-	 */
-	SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
-
-	/*
-	 * Initialize SmartDMA parameters stored in SRAM
-	 */
-	*(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase;
-	*(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase;
-	*(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase;
-	*(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase;
-
-	/*
-	 * Enable FEC-Lite controller
-	 */
-	fec->eth->ecntrl |= 0x00000006;
-
-#if (DEBUG & 0x2)
-	if (fec->xcv_type != SEVENWIRE)
-		mpc5xxx_fec_phydump (dev->name);
-#endif
-
-	/*
-	 * Enable SmartDMA receive task
-	 */
-	SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
-
-#if (DEBUG & 0x1)
-	printf("mpc5xxx_fec_init... Done \n");
-#endif
-
-	return 1;
-}
-
-/********************************************************************/
-static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
-{
-	mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
-	const uint8 phyAddr = CONFIG_PHY_ADDR;	/* Only one PHY */
-	static int initialized = 0;
-
-	if(initialized)
-		return 0;
-	initialized = 1;
-
-#if (DEBUG & 0x1)
-	printf ("mpc5xxx_fec_init_phy... Begin\n");
-#endif
-
-	/*
-	 * Initialize GPIO pins
-	 */
-	if (fec->xcv_type == SEVENWIRE) {
-		/*  10MBit with 7-wire operation */
-		/* 7-wire only */
-		*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
-	} else {
-		/* 100MBit with MD operation */
-		*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
-	}
-
-	/*
-	 * Clear FEC-Lite interrupt event register(IEVENT)
-	 */
-	fec->eth->ievent = 0xffffffff;
-
-	/*
-	 * Set interrupt mask register
-	 */
-	fec->eth->imask = 0x00000000;
-
-/*
- * In original Promess-provided code PHY initialization is disabled with the
- * following comment: "Phy initialization is DISABLED for now.  There was a
- * problem with running 100 Mbps on PRO board". Thus we temporarily disable
- * PHY initialization for the Motion-PRO board, until a proper fix is found.
- */
-
-	if (fec->xcv_type != SEVENWIRE) {
-		/*
-		 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
-		 * and do not drop the Preamble.
-		 * No MII for 7-wire mode
-		 */
-		fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
-	}
-
-	if (fec->xcv_type != SEVENWIRE) {
-		/*
-		 * Initialize PHY(LXT971A):
-		 *
-		 *   Generally, on power up, the LXT971A reads its configuration
-		 *   pins to check for forced operation, If not cofigured for
-		 *   forced operation, it uses auto-negotiation/parallel detection
-		 *   to automatically determine line operating conditions.
-		 *   If the PHY device on the other side of the link supports
-		 *   auto-negotiation, the LXT971A auto-negotiates with it
-		 *   using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
-		 *   support auto-negotiation, the LXT971A automatically detects
-		 *   the presence of either link pulses(10Mbps PHY) or Idle
-		 *   symbols(100Mbps) and sets its operating conditions accordingly.
-		 *
-		 *   When auto-negotiation is controlled by software, the following
-		 *   steps are recommended.
-		 *
-		 * Note:
-		 *   The physical address is dependent on hardware configuration.
-		 *
-		 */
-		int timeout = 1;
-		uint16 phyStatus;
-
-		/*
-		 * Reset PHY, then delay 300ns
-		 */
-		miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
-		udelay(1000);
-
-		if (fec->xcv_type == MII10) {
-			/*
-			 * Force 10Base-T, FDX operation
-			 */
-#if (DEBUG & 0x2)
-			printf("Forcing 10 Mbps ethernet link... ");
-#endif
-			miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
-			/*
-			miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100);
-			*/
-			miiphy_write(dev->name, phyAddr, 0x0, 0x0180);
-
-			timeout = 20;
-			do {	/* wait for link status to go down */
-				udelay(10000);
-				if ((timeout--) == 0) {
-#if (DEBUG & 0x2)
-					printf("hmmm, should not have waited...");
-#endif
-					break;
-				}
-				miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
-#if (DEBUG & 0x2)
-				printf("=");
-#endif
-			} while ((phyStatus & 0x0004));	/* !link up */
-
-			timeout = 1000;
-			do {	/* wait for link status to come back up */
-				udelay(10000);
-				if ((timeout--) == 0) {
-					printf("failed. Link is down.\n");
-					break;
-				}
-				miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
-#if (DEBUG & 0x2)
-				printf("+");
-#endif
-			} while (!(phyStatus & 0x0004));	/* !link up */
-
-#if (DEBUG & 0x2)
-			printf ("done.\n");
-#endif
-		} else {	/* MII100 */
-			/*
-			 * Set the auto-negotiation advertisement register bits
-			 */
-			miiphy_write(dev->name, phyAddr, 0x4, 0x01e1);
-
-			/*
-			 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
-			 */
-			miiphy_write(dev->name, phyAddr, 0x0, 0x1200);
-
-			/*
-			 * Wait for AN completion
-			 */
-			timeout = 5000;
-			do {
-				udelay(1000);
-
-				if ((timeout--) == 0) {
-#if (DEBUG & 0x2)
-					printf("PHY auto neg 0 failed...\n");
-#endif
-					return -1;
-				}
-
-				if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) {
-#if (DEBUG & 0x2)
-					printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
-#endif
-					return -1;
-				}
-			} while (!(phyStatus & 0x0004));
-
-#if (DEBUG & 0x2)
-			printf("PHY auto neg complete! \n");
-#endif
-		}
-
-	}
-
-#if (DEBUG & 0x2)
-	if (fec->xcv_type != SEVENWIRE)
-		mpc5xxx_fec_phydump (dev->name);
-#endif
-
-
-#if (DEBUG & 0x1)
-	printf("mpc5xxx_fec_init_phy... Done \n");
-#endif
-
-	return 1;
-}
-
-/********************************************************************/
-static void mpc5xxx_fec_halt(struct eth_device *dev)
-{
-	struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
-	mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
-	int counter = 0xffff;
-
-#if (DEBUG & 0x2)
-	if (fec->xcv_type != SEVENWIRE)
-		mpc5xxx_fec_phydump (dev->name);
-#endif
-
-	/*
-	 * mask FEC chip interrupts
-	 */
-	fec->eth->imask = 0;
-
-	/*
-	 * issue graceful stop command to the FEC transmitter if necessary
-	 */
-	fec->eth->x_cntrl |= 0x00000001;
-
-	/*
-	 * wait for graceful stop to register
-	 */
-	while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
-
-	/*
-	 * Disable SmartDMA tasks
-	 */
-	SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
-	SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
-
-	/*
-	 * Turn on COMM bus prefetch in the MPC5200 BestComm after we're
-	 * done. It doesn't work w/ the current receive task.
-	 */
-	 sdma->PtdCntrl &= ~0x00000001;
-
-	/*
-	 * Disable the Ethernet Controller
-	 */
-	fec->eth->ecntrl &= 0xfffffffd;
-
-	/*
-	 * Clear FIFO status registers
-	 */
-	fec->eth->rfifo_status &= 0x00700000;
-	fec->eth->tfifo_status &= 0x00700000;
-
-	fec->eth->reset_cntrl = 0x01000000;
-
-	/*
-	 * Issue a reset command to the FEC chip
-	 */
-	fec->eth->ecntrl |= 0x1;
-
-	/*
-	 * wait at least 16 clock cycles
-	 */
-	udelay(10);
-
-	/* don't leave the MII speed set to zero */
-	if (fec->xcv_type != SEVENWIRE) {
-		/*
-		 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
-		 * and do not drop the Preamble.
-		 * No MII for 7-wire mode
-		 */
-		fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
-	}
-
-#if (DEBUG & 0x3)
-	printf("Ethernet task stopped\n");
-#endif
-}
-
-#if (DEBUG & 0x60)
-/********************************************************************/
-
-static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
-{
-	uint16 phyAddr = CONFIG_PHY_ADDR;
-	uint16 phyStatus;
-
-	if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
-		|| (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
-
-		miiphy_read(devname, phyAddr, 0x1, &phyStatus);
-		printf("\nphyStatus: 0x%04x\n", phyStatus);
-		printf("ecntrl:   0x%08x\n", fec->eth->ecntrl);
-		printf("ievent:   0x%08x\n", fec->eth->ievent);
-		printf("x_status: 0x%08x\n", fec->eth->x_status);
-		printf("tfifo: status  0x%08x\n", fec->eth->tfifo_status);
-
-		printf("       control 0x%08x\n", fec->eth->tfifo_cntrl);
-		printf("       lrfp    0x%08x\n", fec->eth->tfifo_lrf_ptr);
-		printf("       lwfp    0x%08x\n", fec->eth->tfifo_lwf_ptr);
-		printf("       alarm   0x%08x\n", fec->eth->tfifo_alarm);
-		printf("       readptr 0x%08x\n", fec->eth->tfifo_rdptr);
-		printf("       writptr 0x%08x\n", fec->eth->tfifo_wrptr);
-	}
-}
-
-static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
-{
-	uint16 phyAddr = CONFIG_PHY_ADDR;
-	uint16 phyStatus;
-
-	if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
-		|| (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
-
-		miiphy_read(devname, phyAddr, 0x1, &phyStatus);
-		printf("\nphyStatus: 0x%04x\n", phyStatus);
-		printf("ecntrl:   0x%08x\n", fec->eth->ecntrl);
-		printf("ievent:   0x%08x\n", fec->eth->ievent);
-		printf("x_status: 0x%08x\n", fec->eth->x_status);
-		printf("rfifo: status  0x%08x\n", fec->eth->rfifo_status);
-
-		printf("       control 0x%08x\n", fec->eth->rfifo_cntrl);
-		printf("       lrfp    0x%08x\n", fec->eth->rfifo_lrf_ptr);
-		printf("       lwfp    0x%08x\n", fec->eth->rfifo_lwf_ptr);
-		printf("       alarm   0x%08x\n", fec->eth->rfifo_alarm);
-		printf("       readptr 0x%08x\n", fec->eth->rfifo_rdptr);
-		printf("       writptr 0x%08x\n", fec->eth->rfifo_wrptr);
-	}
-}
-#endif /* DEBUG */
-
-/********************************************************************/
-
-static int mpc5xxx_fec_send(struct eth_device *dev, void *eth_data,
-		int data_length)
-{
-	/*
-	 * This routine transmits one frame.  This routine only accepts
-	 * 6-byte Ethernet addresses.
-	 */
-	mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
-	volatile FEC_TBD *pTbd;
-
-#if (DEBUG & 0x20)
-	printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
-	tfifo_print(dev->name, fec);
-#endif
-
-	/*
-	 * Clear Tx BD ring at first
-	 */
-	mpc5xxx_fec_tbd_scrub(fec);
-
-	/*
-	 * Check for valid length of data.
-	 */
-	if ((data_length > 1500) || (data_length <= 0)) {
-		return -1;
-	}
-
-	/*
-	 * Check the number of vacant TxBDs.
-	 */
-	if (fec->cleanTbdNum < 1) {
-#if (DEBUG & 0x20)
-		printf("No available TxBDs ...\n");
-#endif
-		return -1;
-	}
-
-	/*
-	 * Get the first TxBD to send the mac header
-	 */
-	pTbd = &fec->tbdBase[fec->tbdIndex];
-	pTbd->dataLength = data_length;
-	pTbd->dataPointer = (uint32)eth_data;
-	pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
-	fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
-
-#if (DEBUG & 0x100)
-	printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
-#endif
-
-	/*
-	 * Kick the MII i/f
-	 */
-	if (fec->xcv_type != SEVENWIRE) {
-		uint16 phyStatus;
-		miiphy_read(dev->name, 0, 0x1, &phyStatus);
-	}
-
-	/*
-	 * Enable SmartDMA transmit task
-	 */
-
-#if (DEBUG & 0x20)
-	tfifo_print(dev->name, fec);
-#endif
-	SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
-#if (DEBUG & 0x20)
-	tfifo_print(dev->name, fec);
-#endif
-#if (DEBUG & 0x8)
-	printf( "+" );
-#endif
-
-	fec->cleanTbdNum -= 1;
-
-#if (DEBUG & 0x129) && (DEBUG & 0x80000000)
-	printf ("smartDMA ethernet Tx task enabled\n");
-#endif
-	/*
-	 * wait until frame is sent .
-	 */
-	while (pTbd->status & FEC_TBD_READY) {
-		udelay(10);
-#if (DEBUG & 0x8)
-		printf ("TDB status = %04x\n", pTbd->status);
-#endif
-	}
-
-	return 0;
-}
-
-
-/********************************************************************/
-static int mpc5xxx_fec_recv(struct eth_device *dev)
-{
-	/*
-	 * This command pulls one frame from the card
-	 */
-	mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
-	volatile FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
-	unsigned long ievent;
-	int frame_length, len = 0;
-	NBUF *frame;
-	uchar buff[FEC_MAX_PKT_SIZE];
-
-#if (DEBUG & 0x1)
-	printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
-#endif
-#if (DEBUG & 0x8)
-	printf( "-" );
-#endif
-
-	/*
-	 * Check if any critical events have happened
-	 */
-	ievent = fec->eth->ievent;
-	fec->eth->ievent = ievent;
-	if (ievent & 0x20060000) {
-		/* BABT, Rx/Tx FIFO errors */
-		mpc5xxx_fec_halt(dev);
-		mpc5xxx_fec_init(dev, NULL);
-		return 0;
-	}
-	if (ievent & 0x80000000) {
-		/* Heartbeat error */
-		fec->eth->x_cntrl |= 0x00000001;
-	}
-	if (ievent & 0x10000000) {
-		/* Graceful stop complete */
-		if (fec->eth->x_cntrl & 0x00000001) {
-			mpc5xxx_fec_halt(dev);
-			fec->eth->x_cntrl &= ~0x00000001;
-			mpc5xxx_fec_init(dev, NULL);
-		}
-	}
-
-	if (!(pRbd->status & FEC_RBD_EMPTY)) {
-		if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
-			((pRbd->dataLength - 4) > 14)) {
-
-			/*
-			 * Get buffer address and size
-			 */
-			frame = (NBUF *)pRbd->dataPointer;
-			frame_length = pRbd->dataLength - 4;
-
-#if (DEBUG & 0x20)
-			{
-				int i;
-				printf("recv data hdr:");
-				for (i = 0; i < 14; i++)
-					printf("%x ", *(frame->head + i));
-				printf("\n");
-			}
-#endif
-			/*
-			 *  Fill the buffer and pass it to upper layers
-			 */
-			memcpy(buff, frame->head, 14);
-			memcpy(buff + 14, frame->data, frame_length);
-			net_process_received_packet(buff, frame_length);
-			len = frame_length;
-		}
-		/*
-		 * Reset buffer descriptor as empty
-		 */
-		mpc5xxx_fec_rbd_clean(fec, pRbd);
-	}
-	SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
-	return len;
-}
-
-
-/********************************************************************/
-int mpc5xxx_fec_initialize(bd_t * bis)
-{
-	mpc5xxx_fec_priv *fec;
-	struct eth_device *dev;
-	char *tmp, *end;
-	char env_enetaddr[6];
-	int i;
-
-	fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
-	dev = (struct eth_device *)malloc(sizeof(*dev));
-	memset(dev, 0, sizeof *dev);
-
-	fec->eth = (ethernet_regs *)MPC5XXX_FEC;
-	fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
-	fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
-#if defined(CONFIG_MPC5xxx_FEC_MII100)
-	fec->xcv_type = MII100;
-#elif defined(CONFIG_MPC5xxx_FEC_MII10)
-	fec->xcv_type = MII10;
-#elif defined(CONFIG_MPC5xxx_FEC_SEVENWIRE)
-	fec->xcv_type = SEVENWIRE;
-#else
-#error fec->xcv_type not initialized.
-#endif
-	if (fec->xcv_type != SEVENWIRE) {
-		/*
-		 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
-		 * and do not drop the Preamble.
-		 * No MII for 7-wire mode
-		 */
-		fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
-	}
-
-	dev->priv = (void *)fec;
-	dev->iobase = MPC5XXX_FEC;
-	dev->init = mpc5xxx_fec_init;
-	dev->halt = mpc5xxx_fec_halt;
-	dev->send = mpc5xxx_fec_send;
-	dev->recv = mpc5xxx_fec_recv;
-
-	strcpy(dev->name, "FEC");
-	eth_register(dev);
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-	int retval;
-	struct mii_dev *mdiodev = mdio_alloc();
-	if (!mdiodev)
-		return -ENOMEM;
-	strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
-	mdiodev->read = fec5xxx_miiphy_read;
-	mdiodev->write = fec5xxx_miiphy_write;
-
-	retval = mdio_register(mdiodev);
-	if (retval < 0)
-		return retval;
-#endif
-
-	/*
-	 * Try to set the mac address now. The fec mac address is
-	 * a garbage after reset. When not using fec for booting
-	 * the Linux fec driver will try to work with this garbage.
-	 */
-	tmp = getenv("ethaddr");
-	if (tmp) {
-		for (i=0; i<6; i++) {
-			env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
-			if (tmp)
-				tmp = (*end) ? end+1 : end;
-		}
-		mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
-	}
-
-	return 1;
-}
-
-/* MII-interface related functions */
-/********************************************************************/
-int fec5xxx_miiphy_read(struct mii_dev *bus, int phyAddr, int devad,
-			int regAddr)
-{
-	uint16 retVal = 0;
-	ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
-	uint32 reg;		/* convenient holder for the PHY register */
-	uint32 phy;		/* convenient holder for the PHY */
-	int timeout = 0xffff;
-
-	/*
-	 * reading from any PHY's register is done by properly
-	 * programming the FEC's MII data register.
-	 */
-	reg = regAddr << FEC_MII_DATA_RA_SHIFT;
-	phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
-
-	eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
-
-	/*
-	 * wait for the related interrupt
-	 */
-	while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
-
-	if (timeout == 0) {
-#if (DEBUG & 0x2)
-		printf ("Read MDIO failed...\n");
-#endif
-		return -1;
-	}
-
-	/*
-	 * clear mii interrupt bit
-	 */
-	eth->ievent = 0x00800000;
-
-	/*
-	 * it's now safe to read the PHY's register
-	 */
-	retVal = (uint16) eth->mii_data;
-
-	return retVal;
-}
-
-/********************************************************************/
-int fec5xxx_miiphy_write(struct mii_dev *bus, int phyAddr, int devad,
-			 int regAddr, u16 data)
-{
-	ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
-	uint32 reg;		/* convenient holder for the PHY register */
-	uint32 phy;		/* convenient holder for the PHY */
-	int timeout = 0xffff;
-
-	reg = regAddr << FEC_MII_DATA_RA_SHIFT;
-	phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
-
-	eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
-			FEC_MII_DATA_TA | phy | reg | data);
-
-	/*
-	 * wait for the MII interrupt
-	 */
-	while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
-
-	if (timeout == 0) {
-#if (DEBUG & 0x2)
-		printf ("Write MDIO failed...\n");
-#endif
-		return -1;
-	}
-
-	/*
-	 * clear MII interrupt bit
-	 */
-	eth->ievent = 0x00800000;
-
-	return 0;
-}
diff --git a/drivers/net/mpc5xxx_fec.h b/drivers/net/mpc5xxx_fec.h
deleted file mode 100644
index 16c3e8e918..0000000000
--- a/drivers/net/mpc5xxx_fec.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * This file is based on mpc4200fec.h
- * (C) Copyright Motorola, Inc., 2000
- *
- * odin ethernet header file
- */
-
-#ifndef __MPC5XXX_FEC_H
-#define __MPC5XXX_FEC_H
-
-typedef unsigned long uint32;
-typedef unsigned short uint16;
-typedef unsigned char uint8;
-
-typedef struct ethernet_register_set {
-
-/* [10:2]addr = 00 */
-
-/*  Control and status Registers (offset 000-1FF) */
-
-	volatile uint32 fec_id;			/* MBAR_ETH + 0x000 */
-	volatile uint32 ievent;			/* MBAR_ETH + 0x004 */
-	volatile uint32 imask;			/* MBAR_ETH + 0x008 */
-
-	volatile uint32 RES0[1];		/* MBAR_ETH + 0x00C */
-	volatile uint32 r_des_active;		/* MBAR_ETH + 0x010 */
-	volatile uint32 x_des_active;		/* MBAR_ETH + 0x014 */
-	volatile uint32 r_des_active_cl;	/* MBAR_ETH + 0x018 */
-	volatile uint32 x_des_active_cl;	/* MBAR_ETH + 0x01C */
-	volatile uint32 ivent_set;		/* MBAR_ETH + 0x020 */
-	volatile uint32 ecntrl;			/* MBAR_ETH + 0x024 */
-
-	volatile uint32 RES1[6];		/* MBAR_ETH + 0x028-03C */
-	volatile uint32 mii_data;		/* MBAR_ETH + 0x040 */
-	volatile uint32 mii_speed;		/* MBAR_ETH + 0x044 */
-	volatile uint32 mii_status;		/* MBAR_ETH + 0x048 */
-
-	volatile uint32 RES2[5];		/* MBAR_ETH + 0x04C-05C */
-	volatile uint32 mib_data;		/* MBAR_ETH + 0x060 */
-	volatile uint32 mib_control;		/* MBAR_ETH + 0x064 */
-
-	volatile uint32 RES3[6];		/* MBAR_ETH + 0x068-7C */
-	volatile uint32 r_activate;		/* MBAR_ETH + 0x080 */
-	volatile uint32 r_cntrl;		/* MBAR_ETH + 0x084 */
-	volatile uint32 r_hash;			/* MBAR_ETH + 0x088 */
-	volatile uint32 r_data;			/* MBAR_ETH + 0x08C */
-	volatile uint32 ar_done;		/* MBAR_ETH + 0x090 */
-	volatile uint32 r_test;			/* MBAR_ETH + 0x094 */
-	volatile uint32 r_mib;			/* MBAR_ETH + 0x098 */
-	volatile uint32 r_da_low;		/* MBAR_ETH + 0x09C */
-	volatile uint32 r_da_high;		/* MBAR_ETH + 0x0A0 */
-
-	volatile uint32 RES4[7];		/* MBAR_ETH + 0x0A4-0BC */
-	volatile uint32 x_activate;		/* MBAR_ETH + 0x0C0 */
-	volatile uint32 x_cntrl;		/* MBAR_ETH + 0x0C4 */
-	volatile uint32 backoff;		/* MBAR_ETH + 0x0C8 */
-	volatile uint32 x_data;			/* MBAR_ETH + 0x0CC */
-	volatile uint32 x_status;		/* MBAR_ETH + 0x0D0 */
-	volatile uint32 x_mib;			/* MBAR_ETH + 0x0D4 */
-	volatile uint32 x_test;			/* MBAR_ETH + 0x0D8 */
-	volatile uint32 fdxfc_da1;		/* MBAR_ETH + 0x0DC */
-	volatile uint32 fdxfc_da2;		/* MBAR_ETH + 0x0E0 */
-	volatile uint32 paddr1;			/* MBAR_ETH + 0x0E4 */
-	volatile uint32 paddr2;			/* MBAR_ETH + 0x0E8 */
-	volatile uint32 op_pause;		/* MBAR_ETH + 0x0EC */
-
-	volatile uint32 RES5[4];		/* MBAR_ETH + 0x0F0-0FC */
-	volatile uint32 instr_reg;		/* MBAR_ETH + 0x100 */
-	volatile uint32 context_reg;		/* MBAR_ETH + 0x104 */
-	volatile uint32 test_cntrl;		/* MBAR_ETH + 0x108 */
-	volatile uint32 acc_reg;		/* MBAR_ETH + 0x10C */
-	volatile uint32 ones;			/* MBAR_ETH + 0x110 */
-	volatile uint32 zeros;			/* MBAR_ETH + 0x114 */
-	volatile uint32 iaddr1;			/* MBAR_ETH + 0x118 */
-	volatile uint32 iaddr2;			/* MBAR_ETH + 0x11C */
-	volatile uint32 gaddr1;			/* MBAR_ETH + 0x120 */
-	volatile uint32 gaddr2;			/* MBAR_ETH + 0x124 */
-	volatile uint32 random;			/* MBAR_ETH + 0x128 */
-	volatile uint32 rand1;			/* MBAR_ETH + 0x12C */
-	volatile uint32 tmp;			/* MBAR_ETH + 0x130 */
-
-	volatile uint32 RES6[3];		/* MBAR_ETH + 0x134-13C */
-	volatile uint32 fifo_id;		/* MBAR_ETH + 0x140 */
-	volatile uint32 x_wmrk;			/* MBAR_ETH + 0x144 */
-	volatile uint32 fcntrl;			/* MBAR_ETH + 0x148 */
-	volatile uint32 r_bound;		/* MBAR_ETH + 0x14C */
-	volatile uint32 r_fstart;		/* MBAR_ETH + 0x150 */
-	volatile uint32 r_count;		/* MBAR_ETH + 0x154 */
-	volatile uint32 r_lag;			/* MBAR_ETH + 0x158 */
-	volatile uint32 r_read;			/* MBAR_ETH + 0x15C */
-	volatile uint32 r_write;		/* MBAR_ETH + 0x160 */
-	volatile uint32 x_count;		/* MBAR_ETH + 0x164 */
-	volatile uint32 x_lag;			/* MBAR_ETH + 0x168 */
-	volatile uint32 x_retry;		/* MBAR_ETH + 0x16C */
-	volatile uint32 x_write;		/* MBAR_ETH + 0x170 */
-	volatile uint32 x_read;			/* MBAR_ETH + 0x174 */
-
-	volatile uint32 RES7[2];		/* MBAR_ETH + 0x178-17C */
-	volatile uint32 fm_cntrl;		/* MBAR_ETH + 0x180 */
-	volatile uint32 rfifo_data;		/* MBAR_ETH + 0x184 */
-	volatile uint32 rfifo_status;		/* MBAR_ETH + 0x188 */
-	volatile uint32 rfifo_cntrl;		/* MBAR_ETH + 0x18C */
-	volatile uint32 rfifo_lrf_ptr;		/* MBAR_ETH + 0x190 */
-	volatile uint32 rfifo_lwf_ptr;		/* MBAR_ETH + 0x194 */
-	volatile uint32 rfifo_alarm;		/* MBAR_ETH + 0x198 */
-	volatile uint32 rfifo_rdptr;		/* MBAR_ETH + 0x19C */
-	volatile uint32 rfifo_wrptr;		/* MBAR_ETH + 0x1A0 */
-	volatile uint32 tfifo_data;		/* MBAR_ETH + 0x1A4 */
-	volatile uint32 tfifo_status;		/* MBAR_ETH + 0x1A8 */
-	volatile uint32 tfifo_cntrl;		/* MBAR_ETH + 0x1AC */
-	volatile uint32 tfifo_lrf_ptr;		/* MBAR_ETH + 0x1B0 */
-	volatile uint32 tfifo_lwf_ptr;		/* MBAR_ETH + 0x1B4 */
-	volatile uint32 tfifo_alarm;		/* MBAR_ETH + 0x1B8 */
-	volatile uint32 tfifo_rdptr;		/* MBAR_ETH + 0x1BC */
-	volatile uint32 tfifo_wrptr;		/* MBAR_ETH + 0x1C0 */
-
-	volatile uint32 reset_cntrl;		/* MBAR_ETH + 0x1C4 */
-	volatile uint32 xmit_fsm;		/* MBAR_ETH + 0x1C8 */
-
-	volatile uint32 RES8[3];		/* MBAR_ETH + 0x1CC-1D4 */
-	volatile uint32 rdes_data0;		/* MBAR_ETH + 0x1D8 */
-	volatile uint32 rdes_data1;		/* MBAR_ETH + 0x1DC */
-	volatile uint32 r_length;		/* MBAR_ETH + 0x1E0 */
-	volatile uint32 x_length;		/* MBAR_ETH + 0x1E4 */
-	volatile uint32 x_addr;			/* MBAR_ETH + 0x1E8 */
-	volatile uint32 cdes_data;		/* MBAR_ETH + 0x1EC */
-	volatile uint32 status;			/* MBAR_ETH + 0x1F0 */
-	volatile uint32 dma_control;		/* MBAR_ETH + 0x1F4 */
-	volatile uint32 des_cmnd;		/* MBAR_ETH + 0x1F8 */
-	volatile uint32 data;			/* MBAR_ETH + 0x1FC */
-
-/*  MIB COUNTERS (Offset 200-2FF) */
-
-	volatile uint32 rmon_t_drop;		/* MBAR_ETH + 0x200 */
-	volatile uint32 rmon_t_packets;		/* MBAR_ETH + 0x204 */
-	volatile uint32 rmon_t_bc_pkt;		/* MBAR_ETH + 0x208 */
-	volatile uint32 rmon_t_mc_pkt;		/* MBAR_ETH + 0x20C */
-	volatile uint32 rmon_t_crc_align;	/* MBAR_ETH + 0x210 */
-	volatile uint32 rmon_t_undersize;	/* MBAR_ETH + 0x214 */
-	volatile uint32 rmon_t_oversize;	/* MBAR_ETH + 0x218 */
-	volatile uint32 rmon_t_frag;		/* MBAR_ETH + 0x21C */
-	volatile uint32 rmon_t_jab;		/* MBAR_ETH + 0x220 */
-	volatile uint32 rmon_t_col;		/* MBAR_ETH + 0x224 */
-	volatile uint32 rmon_t_p64;		/* MBAR_ETH + 0x228 */
-	volatile uint32 rmon_t_p65to127;	/* MBAR_ETH + 0x22C */
-	volatile uint32 rmon_t_p128to255;	/* MBAR_ETH + 0x230 */
-	volatile uint32 rmon_t_p256to511;	/* MBAR_ETH + 0x234 */
-	volatile uint32 rmon_t_p512to1023;	/* MBAR_ETH + 0x238 */
-	volatile uint32 rmon_t_p1024to2047;	/* MBAR_ETH + 0x23C */
-	volatile uint32 rmon_t_p_gte2048;	/* MBAR_ETH + 0x240 */
-	volatile uint32 rmon_t_octets;		/* MBAR_ETH + 0x244 */
-	volatile uint32 ieee_t_drop;		/* MBAR_ETH + 0x248 */
-	volatile uint32 ieee_t_frame_ok;	/* MBAR_ETH + 0x24C */
-	volatile uint32 ieee_t_1col;		/* MBAR_ETH + 0x250 */
-	volatile uint32 ieee_t_mcol;		/* MBAR_ETH + 0x254 */
-	volatile uint32 ieee_t_def;		/* MBAR_ETH + 0x258 */
-	volatile uint32 ieee_t_lcol;		/* MBAR_ETH + 0x25C */
-	volatile uint32 ieee_t_excol;		/* MBAR_ETH + 0x260 */
-	volatile uint32 ieee_t_macerr;		/* MBAR_ETH + 0x264 */
-	volatile uint32 ieee_t_cserr;		/* MBAR_ETH + 0x268 */
-	volatile uint32 ieee_t_sqe;		/* MBAR_ETH + 0x26C */
-	volatile uint32 t_fdxfc;		/* MBAR_ETH + 0x270 */
-	volatile uint32 ieee_t_octets_ok;	/* MBAR_ETH + 0x274 */
-
-	volatile uint32 RES9[2];		/* MBAR_ETH + 0x278-27C */
-	volatile uint32 rmon_r_drop;		/* MBAR_ETH + 0x280 */
-	volatile uint32 rmon_r_packets;		/* MBAR_ETH + 0x284 */
-	volatile uint32 rmon_r_bc_pkt;		/* MBAR_ETH + 0x288 */
-	volatile uint32 rmon_r_mc_pkt;		/* MBAR_ETH + 0x28C */
-	volatile uint32 rmon_r_crc_align;	/* MBAR_ETH + 0x290 */
-	volatile uint32 rmon_r_undersize;	/* MBAR_ETH + 0x294 */
-	volatile uint32 rmon_r_oversize;	/* MBAR_ETH + 0x298 */
-	volatile uint32 rmon_r_frag;		/* MBAR_ETH + 0x29C */
-	volatile uint32 rmon_r_jab;		/* MBAR_ETH + 0x2A0 */
-
-	volatile uint32 rmon_r_resvd_0;		/* MBAR_ETH + 0x2A4 */
-
-	volatile uint32 rmon_r_p64;		/* MBAR_ETH + 0x2A8 */
-	volatile uint32 rmon_r_p65to127;	/* MBAR_ETH + 0x2AC */
-	volatile uint32 rmon_r_p128to255;	/* MBAR_ETH + 0x2B0 */
-	volatile uint32 rmon_r_p256to511;	/* MBAR_ETH + 0x2B4 */
-	volatile uint32 rmon_r_p512to1023;	/* MBAR_ETH + 0x2B8 */
-	volatile uint32 rmon_r_p1024to2047;	/* MBAR_ETH + 0x2BC */
-	volatile uint32 rmon_r_p_gte2048;	/* MBAR_ETH + 0x2C0 */
-	volatile uint32 rmon_r_octets;		/* MBAR_ETH + 0x2C4 */
-	volatile uint32 ieee_r_drop;		/* MBAR_ETH + 0x2C8 */
-	volatile uint32 ieee_r_frame_ok;	/* MBAR_ETH + 0x2CC */
-	volatile uint32 ieee_r_crc;		/* MBAR_ETH + 0x2D0 */
-	volatile uint32 ieee_r_align;		/* MBAR_ETH + 0x2D4 */
-	volatile uint32 r_macerr;		/* MBAR_ETH + 0x2D8 */
-	volatile uint32 r_fdxfc;		/* MBAR_ETH + 0x2DC */
-	volatile uint32 ieee_r_octets_ok;	/* MBAR_ETH + 0x2E0 */
-
-	volatile uint32 RES10[6];		/* MBAR_ETH + 0x2E4-2FC */
-
-	volatile uint32 RES11[64];		/* MBAR_ETH + 0x300-3FF */
-} ethernet_regs;
-
-/* Receive & Transmit Buffer Descriptor definitions */
-typedef struct BufferDescriptor {
-	uint16 status;
-	uint16 dataLength;
-	uint32 dataPointer;
-} FEC_RBD;
-typedef struct {
-	uint16 status;
-	uint16 dataLength;
-	uint32 dataPointer;
-} FEC_TBD;
-
-/* private structure */
-typedef enum {
-	SEVENWIRE,			/* 7-wire       */
-	MII10,				/* MII 10Mbps   */
-	MII100				/* MII 100Mbps  */
-} xceiver_type;
-
-typedef struct {
-	ethernet_regs *eth;
-	xceiver_type xcv_type;		/* transceiver type */
-	FEC_RBD *rbdBase;		/* RBD ring */
-	FEC_TBD *tbdBase;		/* TBD ring */
-	uint16 rbdIndex;		/* next receive BD to read */
-	uint16 tbdIndex;		/* next transmit BD to send */
-	uint16 usedTbdIndex;		/* next transmit BD to clean */
-	uint16 cleanTbdNum;		/* the number of available transmit BDs */
-} mpc5xxx_fec_priv;
-
-/* Ethernet parameter area */
-#define FEC_TBD_BASE		(FEC_PARAM_BASE + 0x00)
-#define FEC_TBD_NEXT		(FEC_PARAM_BASE + 0x04)
-#define FEC_RBD_BASE		(FEC_PARAM_BASE + 0x08)
-#define FEC_RBD_NEXT		(FEC_PARAM_BASE + 0x0c)
-
-/* BD Numer definitions */
-#define FEC_TBD_NUM		48	/* The user can adjust this value */
-#define FEC_RBD_NUM		32	/* The user can adjust this value */
-
-/* packet size limit */
-#define FEC_MAX_PKT_SIZE	1536
-
-/* RBD bits definitions */
-#define FEC_RBD_EMPTY		0x8000	/* Buffer is empty */
-#define FEC_RBD_WRAP		0x2000	/* Last BD in ring */
-#define FEC_RBD_INT		0x1000	/* Interrupt */
-#define FEC_RBD_LAST		0x0800	/* Buffer is last in frame(useless) */
-#define FEC_RBD_MISS		0x0100	/* Miss bit for prom mode */
-#define FEC_RBD_BC		0x0080	/* The received frame is broadcast frame */
-#define FEC_RBD_MC		0x0040	/* The received frame is multicast frame */
-#define FEC_RBD_LG		0x0020	/* Frame length violation */
-#define FEC_RBD_NO		0x0010	/* Nonoctet align frame */
-#define FEC_RBD_SH		0x0008	/* Short frame */
-#define FEC_RBD_CR		0x0004	/* CRC error */
-#define FEC_RBD_OV		0x0002	/* Receive FIFO overrun */
-#define FEC_RBD_TR		0x0001	/* Frame is truncated */
-#define FEC_RBD_ERR		(FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \
-				FEC_RBD_OV | FEC_RBD_TR)
-
-/* TBD bits definitions */
-#define FEC_TBD_READY		0x8000	/* Buffer is ready */
-#define FEC_TBD_WRAP		0x2000	/* Last BD in ring */
-#define FEC_TBD_INT		0x1000	/* Interrupt */
-#define FEC_TBD_LAST		0x0800	/* Buffer is last in frame */
-#define FEC_TBD_TC		0x0400	/* Transmit the CRC */
-#define FEC_TBD_ABC		0x0200	/* Append bad CRC */
-
-/* MII-related definitios */
-#define FEC_MII_DATA_ST		0x40000000	/* Start of frame delimiter */
-#define FEC_MII_DATA_OP_RD	0x20000000	/* Perform a read operation */
-#define FEC_MII_DATA_OP_WR	0x10000000	/* Perform a write operation */
-#define FEC_MII_DATA_PA_MSK	0x0f800000	/* PHY Address field mask */
-#define FEC_MII_DATA_RA_MSK	0x007c0000	/* PHY Register field mask */
-#define FEC_MII_DATA_TA		0x00020000	/* Turnaround */
-#define FEC_MII_DATA_DATAMSK	0x0000ffff	/* PHY data field */
-
-#define FEC_MII_DATA_RA_SHIFT	18	/* MII Register address bits */
-#define FEC_MII_DATA_PA_SHIFT	23	/* MII PHY address bits */
-
-#endif	/* __MPC5XXX_FEC_H */
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 438681da7a..420767286f 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -38,7 +38,6 @@ obj-$(CONFIG_RTC_MC146818) += mc146818.o
 obj-$(CONFIG_RTC_MCP79411) += ds1307.o
 obj-$(CONFIG_MCFRTC) += mcfrtc.o
 obj-$(CONFIG_RTC_MK48T59) += mk48t59.o
-obj-$(CONFIG_RTC_MPC5200) += mpc5xxx.o
 obj-$(CONFIG_RTC_MPC8xx) += mpc8xx.o
 obj-$(CONFIG_RTC_MV) += mvrtc.o
 obj-$(CONFIG_RTC_MX27) += mx27rtc.o
diff --git a/drivers/rtc/mpc5xxx.c b/drivers/rtc/mpc5xxx.c
deleted file mode 100644
index 929783e15f..0000000000
--- a/drivers/rtc/mpc5xxx.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * (C) Copyright 2004
- * Reinhard Meyer, EMK Elektronik GmbH
- * r.meyer@emk-elektronik.de
- * www.emk-elektronik.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*****************************************************************************
- * Date & Time support for internal RTC of MPC52xx
- *****************************************************************************/
-/*#define	DEBUG*/
-
-#include <common.h>
-#include <command.h>
-#include <rtc.h>
-
-#if defined(CONFIG_CMD_DATE)
-
-/*****************************************************************************
- * this structure should be defined in mpc5200.h ...
- *****************************************************************************/
-typedef struct rtc5200 {
-	volatile ulong	tsr;	/* MBAR+0x800: time set register */
-	volatile ulong	dsr;	/* MBAR+0x804: data set register */
-	volatile ulong	nysr;	/* MBAR+0x808: new year and stopwatch register */
-	volatile ulong	aier;	/* MBAR+0x80C: alarm and interrupt enable register */
-	volatile ulong	ctr;	/* MBAR+0x810: current time register */
-	volatile ulong	cdr;	/* MBAR+0x814: current data register */
-	volatile ulong	asir;	/* MBAR+0x818: alarm and stopwatch interrupt register */
-	volatile ulong	piber;	/* MBAR+0x81C: periodic interrupt and bus error register */
-	volatile ulong	trdr;	/* MBAR+0x820: test register/divides register */
-} RTC5200;
-
-#define	RTC_SET		0x02000000
-#define	RTC_PAUSE	0x01000000
-
-/*****************************************************************************
- * get time
- *****************************************************************************/
-int rtc_get (struct rtc_time *tmp)
-{
-	RTC5200	*rtc = (RTC5200 *) (CONFIG_SYS_MBAR+0x800);
-	ulong time, date, time2;
-
-	/* read twice to avoid getting a funny time when the second is just changing */
-	do {
-		time = rtc->ctr;
-		date = rtc->cdr;
-		time2 = rtc->ctr;
-	} while (time != time2);
-
-	tmp->tm_year	= date & 0xfff;
-	tmp->tm_mon		= (date >> 24) & 0xf;
-	tmp->tm_mday	= (date >> 16) & 0x1f;
-	tmp->tm_wday	= (date >> 21) & 7;
-	/* sunday is 7 in 5200 but 0 in rtc_time */
-	if (tmp->tm_wday == 7)
-		tmp->tm_wday = 0;
-	tmp->tm_hour	= (time >> 16) & 0x1f;
-	tmp->tm_min		= (time >> 8) & 0x3f;
-	tmp->tm_sec		= time & 0x3f;
-
-	debug ( "Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
-		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
-		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-
-	return 0;
-}
-
-/*****************************************************************************
- * set time
- *****************************************************************************/
-int rtc_set (struct rtc_time *tmp)
-{
-	RTC5200	*rtc = (RTC5200 *) (CONFIG_SYS_MBAR+0x800);
-	ulong time, date, year;
-
-	debug ( "Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
-		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
-		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-
-	time = (tmp->tm_hour << 16) | (tmp->tm_min << 8) | tmp->tm_sec;
-	date = (tmp->tm_mon << 16) | tmp->tm_mday;
-	if (tmp->tm_wday == 0)
-		date |= (7 << 8);
-	else
-		date |= (tmp->tm_wday << 8);
-	year = tmp->tm_year;
-
-	/* mask unwanted bits that might show up when rtc_time is corrupt */
-	time &= 0x001f3f3f;
-	date &= 0x001f071f;
-	year &= 0x00000fff;
-
-	/* pause and set the RTC */
-	rtc->nysr = year;
-	rtc->dsr = date | RTC_PAUSE;
-	udelay (1000);
-	rtc->dsr = date | RTC_PAUSE | RTC_SET;
-	udelay (1000);
-	rtc->dsr = date | RTC_PAUSE;
-	udelay (1000);
-	rtc->dsr = date;
-	udelay (1000);
-
-	rtc->tsr = time | RTC_PAUSE;
-	udelay (1000);
-	rtc->tsr = time | RTC_PAUSE | RTC_SET;
-	udelay (1000);
-	rtc->tsr = time | RTC_PAUSE;
-	udelay (1000);
-	rtc->tsr = time;
-	udelay (1000);
-
-	return 0;
-}
-
-/*****************************************************************************
- * reset rtc circuit
- *****************************************************************************/
-void rtc_reset (void)
-{
-	return;	/* nothing to do */
-}
-
-#endif
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 8b213d0f22..6c5aa5d077 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -133,7 +133,6 @@ serial_initfunc(marvell_serial_initialize);
 serial_initfunc(max3100_serial_initialize);
 serial_initfunc(mcf_serial_initialize);
 serial_initfunc(ml2_serial_initialize);
-serial_initfunc(mpc512x_serial_initialize);
 serial_initfunc(mpc85xx_serial_initialize);
 serial_initfunc(mpc8xx_serial_initialize);
 serial_initfunc(mxc_serial_initialize);
@@ -221,7 +220,6 @@ void serial_initialize(void)
 	max3100_serial_initialize();
 	mcf_serial_initialize();
 	ml2_serial_initialize();
-	mpc512x_serial_initialize();
 	mpc85xx_serial_initialize();
 	mpc8xx_serial_initialize();
 	mxc_serial_initialize();
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index a73b255176..ab5a99faa8 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -26,11 +26,7 @@ obj-$(CONFIG_USB_OHCI_GENERIC) += ohci-generic.o
 obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
 obj-$(CONFIG_USB_EHCI_ARMADA100) += ehci-armada100.o utmi-armada100.o
 obj-$(CONFIG_USB_EHCI_ATMEL) += ehci-atmel.o
-ifdef CONFIG_MPC512X
-obj-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o
-else
 obj-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
-endif
 obj-$(CONFIG_USB_EHCI_FARADAY) += ehci-faraday.o
 obj-$(CONFIG_USB_EHCI_GENERIC) += ehci-generic.o
 obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o
diff --git a/drivers/usb/host/ehci-mpc512x.c b/drivers/usb/host/ehci-mpc512x.c
deleted file mode 100644
index bb4f461613..0000000000
--- a/drivers/usb/host/ehci-mpc512x.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * (C) Copyright 2010, Damien Dusha, <d.dusha@gmail.com>
- *
- * (C) Copyright 2009, Value Team S.p.A.
- * Francesco Rendine, <francesco.rendine@valueteam.com>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
- *
- * Author: Tor Krill tor@excito.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <pci.h>
-#include <usb.h>
-#include <asm/io.h>
-#include <usb/ehci-ci.h>
-
-#include "ehci.h"
-
-static void fsl_setup_phy(volatile struct ehci_hcor *);
-static void fsl_platform_set_host_mode(volatile struct usb_ehci *ehci);
-static int reset_usb_controller(volatile struct usb_ehci *ehci);
-static void usb_platform_dr_init(volatile struct usb_ehci *ehci);
-
-/*
- * Initialize SOC FSL EHCI Controller
- *
- * This code is derived from EHCI FSL USB Linux driver for MPC5121
- *
- */
-int ehci_hcd_init(int index, enum usb_init_type init,
-		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
-	volatile struct usb_ehci *ehci;
-
-	/* Hook the memory mapped registers for EHCI-Controller */
-	ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
-	*hccr = (struct ehci_hccr *)((uint32_t)&(ehci->caplength));
-	*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
-				HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
-
-	/* configure interface for UTMI_WIDE */
-	usb_platform_dr_init(ehci);
-
-	/* Init Phy USB0 to UTMI+ */
-	fsl_setup_phy(*hcor);
-
-	/* Set to host mode */
-	fsl_platform_set_host_mode(ehci);
-
-	/*
-	 * Setting the burst size seems to be required to prevent the
-	 * USB from hanging when communicating with certain USB Mass
-	 * storage devices. This was determined by analysing the
-	 * EHCI registers under Linux vs U-Boot and burstsize was the
-	 * major non-interrupt related difference between the two
-	 * implementations.
-	 *
-	 * Some USB sticks behave better than others. In particular,
-	 * the following USB stick is especially problematic:
-	 * 0930:6545 Toshiba Corp
-	 *
-	 * The burstsize is set here to match the Linux implementation.
-	 */
-	out_be32(&ehci->burstsize, FSL_EHCI_TXPBURST(8) |
-				   FSL_EHCI_RXPBURST(8));
-
-	return 0;
-}
-
-/*
- * Destroy the appropriate control structures corresponding
- * the the EHCI host controller.
- */
-int ehci_hcd_stop(int index)
-{
-	volatile struct usb_ehci *ehci;
-	int exit_status = 0;
-
-	/* Reset the USB controller */
-	ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
-	exit_status = reset_usb_controller(ehci);
-
-	return exit_status;
-}
-
-static int reset_usb_controller(volatile struct usb_ehci *ehci)
-{
-	unsigned int i;
-
-	/* Command a reset of the USB Controller */
-	out_be32(&(ehci->usbcmd), CMD_RESET);
-
-	/* Wait for the reset process to finish */
-	for (i = 65535 ; i > 0 ; i--) {
-		/*
-		 * The host will set this bit to zero once the
-		 * reset process is complete
-		 */
-		if ((in_be32(&(ehci->usbcmd)) & CMD_RESET) == 0)
-			return 0;
-	}
-
-	/* Hub did not reset in time */
-	return -1;
-}
-
-static void fsl_setup_phy(volatile struct ehci_hcor *hcor)
-{
-	uint32_t portsc;
-
-	portsc  = ehci_readl(&hcor->or_portsc[0]);
-	portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
-
-	/* Enable the phy mode to UTMI Wide */
-	portsc |= PORT_PTS_PTW;
-	portsc |= PORT_PTS_UTMI;
-
-	ehci_writel(&hcor->or_portsc[0], portsc);
-}
-
-static void fsl_platform_set_host_mode(volatile struct usb_ehci *ehci)
-{
-	uint32_t temp;
-
-	temp  = in_le32(&ehci->usbmode);
-	temp |= CM_HOST | ES_BE;
-	out_le32(&ehci->usbmode, temp);
-}
-
-static void usb_platform_dr_init(volatile struct usb_ehci *ehci)
-{
-	/* Configure interface for UTMI_WIDE */
-	out_be32(&ehci->isiphyctrl, PHYCTRL_PHYE | PHYCTRL_PXE);
-	out_be32(&ehci->usbgenctrl, GC_PPP | GC_PFP );
-}
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index b5e0304348..272df0784a 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -53,7 +53,6 @@
 #if defined(CONFIG_CPU_ARM920T) || \
     defined(CONFIG_440EP) || \
     defined(CONFIG_PCI_OHCI) || \
-    defined(CONFIG_MPC5200) || \
     defined(CONFIG_SYS_OHCI_USE_NPS)
 # define OHCI_USE_NPS		/* force NoPowerSwitching mode */
 #endif
@@ -1088,10 +1087,6 @@ static void check_status(td_t *td_list)
 				*phwHeadP &= m32_swap(0xfffffff2);
 			flush_dcache_ed(td_list->ed);
 		}
-#ifdef CONFIG_MPC5200
-		td_list->hwNextTD = 0;
-		flush_dcache_td(td_list);
-#endif
 	}
 }
 
diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
index db0924c943..2350831932 100644
--- a/drivers/usb/host/ohci.h
+++ b/drivers/usb/host/ohci.h
@@ -115,9 +115,7 @@ struct td {
 	__u32 hwNextTD;		/* Next TD Pointer */
 	__u32 hwBE;		/* Memory Buffer End Pointer */
 
-/* #ifndef CONFIG_MPC5200 /\* this seems wrong *\/ */
 	__u16 hwPSW[MAXPSW];
-/* #endif */
 	__u8 unused;
 	__u8 index;
 	struct ed *ed;
@@ -141,13 +139,8 @@ typedef struct td td_t;
 #define NUM_INTS 32	/* part of the OHCI standard */
 struct ohci_hcca {
 	__u32	int_table[NUM_INTS];	/* Interrupt ED table */
-#if defined(CONFIG_MPC5200)
-	__u16	pad1;			/* set to 0 on each frame_no change */
-	__u16	frame_no;		/* current frame number */
-#else
 	__u16	frame_no;		/* current frame number */
 	__u16	pad1;			/* set to 0 on each frame_no change */
-#endif
 	__u32	done_head;		/* info returned for an interrupt */
 	u8		reserved_for_hc[116];
 } __attribute__((aligned(256)));
diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile
index 2d08bae24a..f6dea20071 100644
--- a/examples/standalone/Makefile
+++ b/examples/standalone/Makefile
@@ -9,7 +9,6 @@ extra-y        := hello_world
 extra-$(CONFIG_SMC91111)           += smc91111_eeprom
 extra-$(CONFIG_SMC911X)            += smc911x_eeprom
 extra-$(CONFIG_SPI_FLASH_ATMEL)    += atmel_df_pow2
-extra-$(CONFIG_MPC5xxx)            += interrupt
 extra-$(CONFIG_8xx)                += test_burst timer
 extra-$(CONFIG_PPC)                += sched
 
diff --git a/examples/standalone/interrupt.c b/examples/standalone/interrupt.c
deleted file mode 100644
index 6e0086015b..0000000000
--- a/examples/standalone/interrupt.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * (C) Copyright 2006
- * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * This is a very simple standalone application demonstrating
- * catching IRQs on the MPC52xx architecture.
- *
- * The interrupt to be intercepted can be specified as an argument
- * to the application.  Specifying nothing will intercept IRQ1 on the
- * MPC5200 platform.  On the CR825 carrier board from MicroSys this
- * maps to the ABORT switch :)
- *
- * Note that the specified vector is only a logical number specified
- * by the respective header file.
- */
-
-#include <common.h>
-#include <exports.h>
-#include <config.h>
-
-#if defined(CONFIG_MPC5xxx)
-#define DFL_IRQ MPC5XXX_IRQ1
-#else
-#define DFL_IRQ 0
-#endif
-
-static void irq_handler (void *arg);
-
-int interrupt (int argc, char * const argv[])
-{
-	int c, irq = -1;
-
-	app_startup (argv);
-
-	if (argc > 1)
-		irq = simple_strtoul (argv[1], NULL, 0);
-	if ((irq < 0) || (irq > NR_IRQS))
-		irq = DFL_IRQ;
-
-	printf ("Installing handler for irq vector %d and doing busy wait\n",
-		irq);
-	printf ("Press 'q' to quit\n");
-
-	/* Install interrupt handler */
-	install_hdlr (irq, irq_handler, NULL);
-	while ((c = getc ()) != 'q') {
-		printf ("Ok, ok, I am still alive!\n");
-	}
-
-	free_hdlr (irq);
-	printf ("\nInterrupt handler has been uninstalled\n");
-
-	return (0);
-}
-
-/*
- * Handler for interrupt
- */
-static void irq_handler (void *arg)
-{
-	/* just for demonstration */
-	printf ("+");
-}
diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index 7f587670b3..8df28ed0ed 100644
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h
@@ -45,7 +45,7 @@ typedef struct bd_info {
 	|| defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 	unsigned long	bi_immr_base;	/* base of IMMR register */
 #endif
-#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K)
+#if defined(CONFIG_M68K)
 	unsigned long	bi_mbar_base;	/* base of internal registers */
 #endif
 #if defined(CONFIG_MPC83xx)
@@ -63,10 +63,7 @@ typedef struct bd_info {
 	unsigned long	bi_sccfreq;	/* SCC_CLK Freq, in MHz */
 	unsigned long	bi_vco;		/* VCO Out from PLL, in MHz */
 #endif
-#if defined(CONFIG_MPC512X)
-	unsigned long	bi_ipsfreq;	/* IPS Bus Freq, in MHz */
-#endif /* CONFIG_MPC512X */
-#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K)
+#if defined(CONFIG_M68K)
 	unsigned long	bi_ipbfreq;	/* IPB Bus Freq, in MHz */
 	unsigned long	bi_pcifreq;	/* PCI Bus Freq, in MHz */
 #endif
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
deleted file mode 100644
index e1f04459c4..0000000000
--- a/include/configs/TQM5200.h
+++ /dev/null
@@ -1,626 +0,0 @@
-/*
- * (C) Copyright 2003-2014
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004-2006
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU		*/
-#define CONFIG_TQM5200		1	/* ... on TQM5200 module		*/
-#undef CONFIG_TQM5200_REV100		/*  define for revision 100 modules	*/
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFC000000	boot low (standard configuration with room for
- *		max 64 MByte Flash ROM)
- * 0xFFF00000	boot high (for a backup copy of U-Boot)
- * 0x00100000	boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFC000000
-#endif
-
-/* On a Cameron or on a FO300 board or ...				*/
-#if !defined(CONFIG_CAM5200) && !defined(CONFIG_CHARON) \
-	&& !defined(CONFIG_FO300)
-#define CONFIG_STK52XX		1	/* ... on a STK52XX board		*/
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported			*/
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1			*/
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-#define CONFIG_BOOTCOUNT_LIMIT	1
-
-#ifdef CONFIG_FO300
-#define CONFIG_SYS_DEVICE_NULLDEV		1	/* enable null device */
-#define CONFIG_USB_BIN_FIXUP		1	/* for a buggy USB device */
-#if 0
-#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED	1	/* silent console on PSC1 when S1 */
-							/* switch is closed */
-#endif
-
-#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED		/* silent console on PSC1 when S1 */
-							/* switch is open */
-#endif	/* CONFIG_FO300 */
-
-#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
-#define CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
-#define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
-#define CONFIG_PS2SERIAL	6	/* .. on PSC6			*/
-#define CONFIG_PS2MULT_DELAY	(CONFIG_SYS_HZ/2)	/* Initial delay	*/
-#define CONFIG_BOARD_EARLY_INIT_R
-#endif /* CONFIG_STK52XX */
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
-/* #define CONFIG_PCI_SCAN_SHOW	1 */
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-
-#define CONFIG_EEPRO100		1
-#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
-#define CONFIG_NS8382X		1
-#endif	/* CONFIG_STK52XX */
-
-/*
- * Video console
- */
-#ifndef CONFIG_TQM5200S		/* No graphics controller on TQM5200S */
-#define CONFIG_VIDEO_SM501
-#define CONFIG_VIDEO_SM501_32BPP
-#define CONFIG_VIDEO_LOGO
-
-#ifndef CONFIG_FO300
-#else
-#define CONFIG_VIDEO_BMP_LOGO
-#endif
-
-#define CONFIG_SPLASH_SCREEN
-#endif /* #ifndef CONFIG_TQM5200S */
-
-/* Partitions */
-
-/* USB */
-#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
-    defined(CONFIG_STK52XX)
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_OHCI_BE_CONTROLLER
-
-#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE	MPC5XXX_USB
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"mpc5200"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
-
-#endif
-
-#ifndef CONFIG_CAM5200
-/* POST support */
-#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
-				 CONFIG_SYS_POST_CPU)
-#endif
-
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_REGINFO
-
-#ifdef CONFIG_PCI
-#define CONFIG_CMD_PCI
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
-#endif
-
-#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
-	defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
-#endif
-
-#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
-	defined(CONFIG_STK52XX)
-    #define CONFIG_CFG_USB
-    #define CONFIG_CFG_FAT
-#endif
-
-#define	CONFIG_TIMESTAMP		/* display image timestamps */
-
-#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000)
-#   define CONFIG_SYS_LOWBOOT		1	/* Boot low */
-#endif
-
-/*
- * Autobooting
- */
-
-#define CONFIG_PREBOOT	"echo;" \
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#if defined(CONFIG_TQM5200_B) && !defined(CONFIG_SYS_LOWBOOT)
-# define ENV_UPDT							\
-	"update=protect off FFF00000 +${filesize};"			\
-		"erase FFF00000 +${filesize};"				\
-		"cp.b 200000 FFF00000 ${filesize};"			\
-		"protect on FFF00000 +${filesize}\0"
-#else	/* default lowboot configuration */
-#   define ENV_UPDT							\
-	"update=protect off FC000000 +${filesize};"			\
-		"erase FC000000 +${filesize};"				\
-		"cp.b 200000 FC000000 ${filesize};"			\
-		"protect on FC000000 +${filesize}\0"
-#endif
-
-#if defined(CONFIG_TQM5200)
-#define CUSTOM_ENV_SETTINGS						\
-	"hostname=tqm5200\0"						\
-	"bootfile=/tftpboot/tqm5200/uImage\0"				\
-	"fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0"			\
-	"u-boot=/tftpboot/tqm5200/u-boot.bin\0"
-#elif defined(CONFIG_CAM5200)
-#define CUSTOM_ENV_SETTINGS						\
-	"bootfile=cam5200/uImage\0"					\
-	"u-boot=cam5200/u-boot.bin\0"					\
-	"setup=tftp 200000 cam5200/setup.img; source 200000\0"
-#endif
-
-#if defined(CONFIG_TQM5200_B)
-#define ENV_FLASH_LAYOUT						\
-	"fdt_addr=FC100000\0"						\
-	"kernel_addr=FC140000\0"					\
-	"ramdisk_addr=FC600000\0"
-#elif defined(CONFIG_CHARON)
-#define ENV_FLASH_LAYOUT						\
-	"fdt_addr=FDFC0000\0"						\
-	"kernel_addr=FC0A0000\0"					\
-	"ramdisk_addr=FC200000\0"
-#else	/* !CONFIG_TQM5200_B */
-#define ENV_FLASH_LAYOUT						\
-	"fdt_addr=FC0A0000\0"						\
-	"kernel_addr=FC0C0000\0"					\
-	"ramdisk_addr=FC300000\0"
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"console=ttyPSC0\0"						\
-	ENV_FLASH_LAYOUT						\
-	"kernel_addr_r=400000\0"					\
-	"fdt_addr_r=600000\0"						\
-	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addcons=setenv bootargs ${bootargs} "				\
-		"console=${console},${baudrate}\0"			\
-	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
-	"flash_self_old=sete console ttyS0; "				\
-		"run ramargs addip addcons addmtd; "			\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"flash_self=run ramargs addip addcons;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
-	"flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;"	\
-		"bootm ${kernel_addr}\0"				\
-	"flash_nfs=run nfsargs addip addcons;"				\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"net_nfs_old=tftp ${kernel_addr_r} ${bootfile};"		\
-		"sete console ttyS0; run nfsargs addip addcons;bootm\0"	\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
-		"tftp ${fdt_addr_r} ${fdt_file}; "			\
-		"run nfsargs addip addcons addmtd; "			\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	CUSTOM_ENV_SETTINGS						\
-	"load=tftp 200000 ${u-boot}\0"					\
-	ENV_UPDT							\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run net_nfs"
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-
-#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200)
-/*
- * PCI Bus clocking configuration
- *
- * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of
- * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
- */
-#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
-#endif
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE		0xFC000000
-
-#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of flash banks
-					   (= chip selects) */
-#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned int /* main flash device with */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_ADDR0		0x555
-#define CONFIG_SYS_FLASH_ADDR1		0x2AA
-#define CONFIG_SYS_FLASH_2ND_16BIT_DEV	1	/* NIOS flash is a 16bit device */
-#define CONFIG_SYS_MAX_FLASH_SECT	128
-#else
-/* use CFI flash driver */
-#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CONFIG_FLASH_CFI_MTD		/* with MTD support */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_BOOTCS_START }
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
-					   (= chip selects) */
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
-#endif
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_SIZE		0x04000000 /* 64 MByte */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
-
-#if defined (CONFIG_CAM5200)
-# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)
-#elif defined(CONFIG_TQM5200_B)
-# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00080000)
-#else
-# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00060000)
-#endif
-
-/* Dynamic MTD partition support */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
-#define MTDIDS_DEFAULT		"nor0=fc000000.flash"
-
-#if defined(CONFIG_STK52XX)
-# if defined(CONFIG_TQM5200_B)
-#  if defined(CONFIG_SYS_LOWBOOT)
-#   define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:1m(firmware),"	\
-						"256k(dtb),"		\
-						"2304k(kernel),"	\
-						"2560k(small-fs),"	\
-						"2m(initrd),"		\
-						"8m(misc),"		\
-						"16m(big-fs)"
-#  else	/* highboot */
-#   define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:2560k(kernel),"\
-						"3584k(small-fs),"	\
-						"2m(initrd),"		\
-						"8m(misc),"		\
-						"15m(big-fs),"		\
-						"1m(firmware)"
-#  endif /* CONFIG_SYS_LOWBOOT */
-# else	/* !CONFIG_TQM5200_B */
-#   define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:640k(firmware),"\
-						"128k(dtb),"		\
-						"2304k(kernel),"	\
-						"2m(initrd),"		\
-						"4m(small-fs),"		\
-						"8m(misc),"		\
-						"15m(big-fs)"
-# endif /* CONFIG_TQM5200_B */
-#elif defined (CONFIG_CAM5200)
-#   define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:768k(firmware),"\
-						"1792k(kernel),"	\
-						"5632k(rootfs),"	\
-						"24m(home)"
-#elif defined (CONFIG_CHARON)
-#   define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:640k(firmware),"\
-						"1408k(kernel),"	\
-						"2m(initrd),"		\
-						"4m(small-fs),"		\
-						"24320k(big-fs),"	\
-						"256k(dts)"
-#elif defined (CONFIG_FO300)
-#   define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:640k(firmware),"\
-						"1408k(kernel),"	\
-						"2m(initrd),"		\
-						"4m(small-fs),"		\
-						"8m(misc),"		\
-						"16m(big-fs)"
-#else
-# error "Unknown Carrier Board"
-#endif	/* CONFIG_STK52XX */
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_SIZE		0x4000	/* 16 k - keep small for fast booting */
-#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200)
-#define CONFIG_ENV_SECT_SIZE	0x40000
-#else
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#endif /* CONFIG_TQM5200_B */
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-/* Use ON-Chip SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
-#else
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
-#endif
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#if defined (CONFIG_CAM5200)
-# define CONFIG_SYS_MONITOR_LEN	(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#elif defined(CONFIG_TQM5200_B)
-# define CONFIG_SYS_MONITOR_LEN	(512 << 10)	/* Reserve 512 kB for Monitor	*/
-#else
-# define CONFIG_SYS_MONITOR_LEN	(384 << 10)	/* Reserve 384 kB for Monitor	*/
-#endif
-
-#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)	/* Reserve 1024 kB for malloc()	*/
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII100
-/*
- * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
- */
-/* #define CONFIG_MPC5xxx_FEC_MII10 */
-#define CONFIG_PHY_ADDR		0x00
-
-/*
- * GPIO configuration
- *
- * use CS1: Bit 0 (mask: 0x80000000):
- *	   1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1).
- * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
- *	  00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
- *		SPI on PSC3 according to PSC3 setting. Use for CAM5200.
- *	  01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
- *		Use for REV200 STK52XX boards and FO300 boards. Do not use
- *		with REV100 modules (because, there I2C1 is used as I2C bus).
- * use ATA: Bits 6-7 (mask 0x03000000):
- *	  00 -> No ATA chip selects, csb_4/5 used as normal chip selects.
- *		Use for CAM5200 board.
- *	  01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards.
- * use PSC6: Bits 9-11 (mask 0x00700000):
- *	 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as
- *		UART, CODEC or IrDA.
- *		GPIO on PSC6_3 is used in post_hotkeys_pressed() to
- *		enable extended POST tests.
- *		Use for MINI-FAP and TQM5200_IB boards.
- *	 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used.
- *		Extended POST test is not available.
- *		Use for STK52xx, FO300 and CAM5200 boards.
- *		WARNING: When the extended POST is enabled, these bits will
- *			 be overridden by this code as GPIOs!
- * use PCI_DIS: Bit 16 (mask 0x00008000):
- *	   1 -> disable PCI controller (on CAM5200 board).
- * use USB: Bits 18-19 (mask 0x00003000):
- *	  10 -> two UARTs (on FO300 and CAM5200).
- * use PSC3: Bits 20-23 (mask: 0x00000f00):
- *	0000 -> All PSC3 pins are GPIOs.
- *	1100 -> UART/SPI (on FO300 board).
- *	0100 -> UART (on CAM5200 board).
- * use PSC2: Bits 25:27 (mask: 0x00000030):
- *	 000 -> All PSC2 pins are GPIOs.
- *	 100 -> UART (on CAM5200 board).
- *	 001 -> CAN1/2 on PSC2 pins.
- *		Use for REV100 STK52xx boards
- *	 01x -> Use AC97 (on FO300 board).
- * use PSC1: Bits 29-31 (mask: 0x00000007):
- *	 100 -> UART (on all boards).
- */
-#if !defined(CONFIG_SYS_GPS_PORT_CONFIG)
-#if defined (CONFIG_MINIFAP)
-# define CONFIG_SYS_GPS_PORT_CONFIG	0x91000004
-#elif defined (CONFIG_STK52XX)
-# if defined (CONFIG_STK52XX_REV100)
-#  define CONFIG_SYS_GPS_PORT_CONFIG	0x81500014
-# else /* STK52xx REV200 and above */
-#  if defined (CONFIG_TQM5200_REV100)
-#   error TQM5200 REV100 not supported on STK52XX REV200 or above
-#  else/* TQM5200 REV200 and above */
-#   define CONFIG_SYS_GPS_PORT_CONFIG	0x91500404
-#  endif
-# endif
-#elif defined (CONFIG_FO300)
-# define CONFIG_SYS_GPS_PORT_CONFIG	0x91502c24
-#elif defined (CONFIG_CAM5200)
-# define CONFIG_SYS_GPS_PORT_CONFIG	0x8050A444
-#else  /* TMQ5200 Inbetriebnahme-Board */
-# define CONFIG_SYS_GPS_PORT_CONFIG	0x81000004
-#endif
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-/* Enable an alternate, more extensive memory test */
-#define CONFIG_SYS_ALT_MEMTEST
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
-#define CONFIG_SYS_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
-#else
-#define CONFIG_SYS_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
-#endif
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_LAST_STAGE_INIT
-
-/*
- * SRAM - Do not map below 2 GB in address space, because this area is used
- * for SDRAM autosizing.
- */
-#define CONFIG_SYS_CS2_START		0xE5000000
-#define CONFIG_SYS_CS2_SIZE		0x100000	/* 1 MByte */
-#define CONFIG_SYS_CS2_CFG		0x0004D930
-
-/*
- * Grafic controller - Do not map below 2 GB in address space, because this
- * area is used for SDRAM autosizing.
- */
-#define SM501_FB_BASE		0xE0000000
-#define CONFIG_SYS_CS1_START		(SM501_FB_BASE)
-#define CONFIG_SYS_CS1_SIZE		0x4000000	/* 64 MByte */
-#define CONFIG_SYS_CS1_CFG		0x8F48FF70
-#define SM501_MMIO_BASE		CONFIG_SYS_CS1_START + 0x03E00000
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */
-
-#if defined(CONFIG_CAM5200)
-#define CONFIG_SYS_CS4_START		0xB0000000
-#define CONFIG_SYS_CS4_SIZE		0x00010000
-#define CONFIG_SYS_CS4_CFG		0x01019C10
-
-#define CONFIG_SYS_CS5_START		0xD0000000
-#define CONFIG_SYS_CS5_SIZE		0x01208000
-#define CONFIG_SYS_CS5_CFG		0x1414BF10
-#endif
-
-#define CONFIG_SYS_RESET_ADDRESS	0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK	0x0001BBBB
-#define CONFIG_USB_CONFIG	0x00001000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef	CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card Adapter */
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
-#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
-
-#define CONFIG_IDE_RESET		/* reset for ide supported	*/
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
-
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE		4
-
-/* Support ATAPI devices */
-#define CONFIG_ATAPI			1
-
-/*-----------------------------------------------------------------------
- * Open firmware flat tree support
- *-----------------------------------------------------------------------
- */
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_SOC			"soc5200@f0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h
deleted file mode 100644
index 82b9ff471d..0000000000
--- a/include/configs/a3m071.h
+++ /dev/null
@@ -1,408 +0,0 @@
-/*
- * Copyright 2012-2013 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200
-#define CONFIG_A3M071			/* A3M071 board */
-
-#define	CONFIG_SYS_TEXT_BASE	0x01000000	/* boot low for 32 MiB boards */
-
-#define CONFIG_SPL_TARGET	"u-boot-img.bin"
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz */
-
-#define CONFIG_MISC_INIT_R
-#define CONFIG_SYS_LOWBOOT		/* Enable lowboot	*/
-
-#ifdef CONFIG_A4M2K
-#define CONFIG_HOSTNAME		a4m2k
-#else
-#define CONFIG_HOSTNAME		a3m071
-#endif
-
-#define CONFIG_BOOTCOUNT_LIMIT
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	    /* console is on PSC1 */
-#define CONFIG_SYS_BAUDRATE_TABLE		\
-	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_REGINFO
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_BOOTP_SERVERIP
-#define CONFIG_BOOTP_MAY_FAIL
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_SERVERIP
-#define CONFIG_NET_RETRY_COUNT 3
-#define CONFIG_NETCONSOLE
-#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
-#define CONFIG_MTD_PARTITIONS	/* needed for UBI */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT          "nor0=fc000000.flash"
-#define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:512k(u-boot),"	\
-						"128k(env1),"	\
-						"128k(env2),"	\
-						"128k(hwinfo),"	\
-						"1M(nvramsim),"	\
-						"128k(dtb),"	\
-						"5M(kernel),"	\
-						"128k(sysinfo),"	\
-						"7552k(root),"	\
-						"4M(app),"	\
-						"5376k(data),"	\
-						"8M(install)"
-
-#define CONFIG_LZO			/* needed for UBI */
-#define CONFIG_RBTREE			/* needed for UBI */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_UBIFS
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-/* define for 66MHz speed - undef for 33MHz PCI clock speed */
-#ifdef CONFIG_A4M2K
-#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
-#else
-#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
-#endif
-
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE	8192
-
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_SOC			"soc5200@f0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
-
-/*
- * NOR flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE		0xfc000000
-#define CONFIG_SYS_FLASH_SIZE		0x02000000
-#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x80000)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	256
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500
-#define CONFIG_SYS_FLASH_LOCK_TOUT	5
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_FLASH_VERIFY
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SIZE		0x10000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR			0xf0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR		0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
-#define CONFIG_SYS_MALLOC_LEN		(4 << 20)
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC
-#define CONFIG_MPC5xxx_FEC_MII100
-#ifdef CONFIG_A4M2K
-#define CONFIG_PHY_ADDR			0x01
-#else
-#define CONFIG_PHY_ADDR			0x00
-#endif
-
-/*
- * GPIO configuration
- */
-
-/*
- * GPIO-config depends on failsave-level
- * failsave 0 means just MPX-config, no digiboard, no fpga
- *          1 means digiboard ok
- *          2 means fpga ok
- */
-
-#ifdef CONFIG_A4M2K
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x1005C805
-#else
-/* for failsave-level 0 - full failsave */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x1005C005
-/* for failsave-level 1 - only digiboard ok */
-#define CONFIG_SYS_GPS_PORT_CONFIG_1	0x1005C065
-/* for failsave-level 2 - all ok */
-#define CONFIG_SYS_GPS_PORT_CONFIG_2	0x1005C065
-#endif
-
-#define CONFIG_WDOG_GPIO_PIN		GPIO_WKUP_7
-#if defined(CONFIG_A4M2K) && !defined(CONFIG_SPL_BUILD)
-#define CONFIG_HW_WATCHDOG		/* Use external HW-Watchdog	*/
-#endif
-
-/*
- * Configuration matrix
- *                        MSB                            LSB
- * failsave 0  0x1005C005  00010000000001011100000000000101  ( full failsave )
- * failsave 1  0x1005C065  00010000000001011100000001100101  ( digib.-ver ok )
- * failsave 2  0x1005C065  00010000000001011100000001100101  ( all ok )
- *                         || ||| ||  |   ||| |   |   |   |
- *                         || ||| ||  |   ||| |   |   |   |  bit rev name
- *                         ++-+++-++--+---+++-+---+---+---+-  0   31 CS1
- *                          +-+++-++--+---+++-+---+---+---+-  1   30 LPTZ
- *                            ||| ||  |   ||| |   |   |   |   2   29 ALTs
- *                            +++-++--+---+++-+---+---+---+-  3   28 ALTs
- *                             ++-++--+---+++-+---+---+---+-  4   27 CS7
- *                              +-++--+---+++-+---+---+---+-  5   26 CS6
- *                                ||  |   ||| |   |   |   |   6   25 ATA
- *                                ++--+---+++-+---+---+---+-  7   24 ATA
- *                                 +--+---+++-+---+---+---+-  8   23 IR_USB_CLK
- *                                    |   ||| |   |   |   |   9   22 IRDA
- *                                    |   ||| |   |   |   |  10   21 IRDA
- *                                    +---+++-+---+---+---+- 11   20 IRDA
- *                                        ||| |   |   |   |  12   19 Ether
- *                                        ||| |   |   |   |  13   18 Ether
- *                                        ||| |   |   |   |  14   17 Ether
- *                                        +++-+---+---+---+- 15   16 Ether
- *                                         ++-+---+---+---+- 16   15 PCI_DIS
- *                                          +-+---+---+---+- 17   14 USB_SE
- *                                            |   |   |   |  18   13 USB
- *                                            +---+---+---+- 19   12 USB
- *                                                |   |   |  20   11 PSC3
- *                                                |   |   |  21   10 PSC3
- *                                                |   |   |  22    9 PSC3
- *                                                +---+---+- 23    8 PSC3
- *                                                    |   |  24    7 -
- *                                                    |   |  25    6 PSC2
- *                                                    |   |  26    5 PSC2
- *                                                    +---+- 27    4 PSC2
- *                                                        |  28    3 -
- *                                                        |  29    2 PSC1
- *                                                        |  30    1 PSC1
- *                                                        +- 31    0 PSC1
- */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP
-
-#define CONFIG_CMDLINE_EDITING
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024
-#else
-#define CONFIG_SYS_CBSIZE		256
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS		16
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000
-#define CONFIG_SYS_MEMTEST_END		0x00f00000
-
-#define CONFIG_SYS_LOAD_ADDR		0x00100000
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		(HID0_ICE | HID0_ICFI)
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#ifdef CONFIG_A4M2K
-/* external MRAM */
-#define CONFIG_SYS_CS1_START		0xf1000000
-#define CONFIG_SYS_CS1_SIZE		(512 << 10)	/* 512KiB MRAM */
-#endif
-
-#define CONFIG_SYS_CS2_START		0xe0000000
-#define CONFIG_SYS_CS2_SIZE		0x00100000
-
-/* FPGA slave io (512kiB / 1MiB) - see ticket #66 */
-#define CONFIG_SYS_CS3_START		0xE9000000
-#ifdef CONFIG_A4M2K
-#define CONFIG_SYS_CS3_SIZE		0x00100000
-#else
-#define CONFIG_SYS_CS3_SIZE		0x00080000
-#endif
-/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0  = 0x0032B900 */
-#define CONFIG_SYS_CS3_CFG		0x0032B900
-
-#ifndef CONFIG_A4M2K
-/* Diagnosis Interface - see ticket #63 */
-#define CONFIG_SYS_CS4_START		0xEA000000
-#define CONFIG_SYS_CS4_SIZE		0x00000001
-/* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0  = 0x0002B900 */
-#define CONFIG_SYS_CS4_CFG		0x0002B900
-#endif
-
-/* FPGA master io (64kiB / 1MiB) - see ticket #66 */
-#define CONFIG_SYS_CS5_START		0xE8000000
-#ifdef CONFIG_A4M2K
-#define CONFIG_SYS_CS5_SIZE		0x00100000
-#else
-#define CONFIG_SYS_CS5_SIZE		0x00010000
-#endif
-/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0  = 0x0032B900 */
-#define CONFIG_SYS_CS5_CFG		0x0032B900
-
-#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* for pci_clk  = 66 MHz */
-#define CONFIG_SYS_BOOTCS_CFG		0x0006F900
-#define CONFIG_SYS_CS1_CFG		0x0008FD00
-#define CONFIG_SYS_CS2_CFG		0x0006F90C
-#else	/* for pci_clk = 33 MHz */
-#define CONFIG_SYS_BOOTCS_CFG		0x0002F900
-#define CONFIG_SYS_CS1_CFG		0x0001FB00
-#define CONFIG_SYS_CS2_CFG		0x0002F90C
-#endif
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-/* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */
-/* R  7  R  6  R  5  R  4  R  3  R  2  R  1  R  0  */
-/* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */
-#define CONFIG_SYS_CS_DEADCYCLE		0x33030000
-
-#define CONFIG_SYS_RESET_ADDRESS	0xff000000
-
-/*
- * Environment Configuration
- */
-
-#undef  CONFIG_BOOTARGS
-
-#define CONFIG_SYS_AUTOLOAD	"n"
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \
-	"echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define CONFIG_SYS_FDT_BASE	0xfc1e0000
-#define CONFIG_SYS_FDT_SIZE	(16<<10)
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"verify=no\0"							\
-	"loadaddr=200000\0"						\
-	"kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0"		\
-	"kernel_addr_r=1000000\0"					\
-	"fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0"		\
-	"fdt_addr_r=1800000\0"						\
-	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
-	"fdtfile=" __stringify(CONFIG_HOSTNAME) "/"			\
-		__stringify(CONFIG_HOSTNAME) ".dtb\0"			\
-	"rootpath=/opt/eldk-5.2.1/powerpc/"				\
-		"core-image-minimal-mtdutils-dropbear-generic\0"	\
-	"consoledev=ttyPSC0\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"mtdargs=setenv bootargs root=/dev/mtdblock8 "			\
-		"rootfstype=squashfs,jffs2\0"				\
-	"addhost=setenv bootargs ${bootargs} "				\
-		"hostname=${hostname}\0"				\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} "				\
-		"console=${consoledev},${baudrate}\0"			\
-	"flash_nfs=run nfsargs addip addtty addmtd addhost;"		\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"flash_mtd=run mtdargs addip addtty addmtd addhost;"		\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"flash_self=run ramargs addip addtty addmtd addhost;"		\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
-		"tftp ${fdt_addr_r} ${fdtfile};"			\
-		"run nfsargs addip addtty addmtd addhost;"		\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	"load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME)		\
-		"/u-boot-img.bin\0"					\
-	"update=protect off fc000000 fc07ffff;"				\
-		"era fc000000 fc07ffff;"				\
-		"cp.b ${loadaddr} fc000000 ${filesize}\0"		\
-	"upd=run load;run update\0"					\
-	"upd_fdt=tftp 1800000 a3m071/a3m071.dtb;"			\
-		"run mtdargs addip addtty addmtd addhost;"		\
-		"fdt addr 1800000;fdt boardsetup;fdt chosen;"		\
-		"erase fc1e0000 fc1fffff;cp.b 1800000 fc1e0000 20000"	\
-	"upd_kernel=tftp 1000000 a3m071/uImage-uncompressed;"		\
-		"erase fc200000 fc6fffff;"				\
-		"cp.b 1000000 fc200000 ${filesize}"			\
-	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
-	"mtdids=" MTDIDS_DEFAULT "\0"					\
-	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run flash_mtd"
-
-/*
- * SPL related defines
- */
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_TEXT_BASE	0xfc000000
-
-/* Place BSS for SPL near end of SDRAM */
-#define CONFIG_SPL_BSS_START_ADDR	((128 - 1) << 20)
-#define CONFIG_SPL_BSS_MAX_SIZE		(64 << 10)
-
-/* Place patched DT blob (fdt) at this address */
-#define CONFIG_SYS_SPL_ARGS_ADDR	0x01800000
-
-/* Settings for real U-Boot to be loaded from NOR flash */
-#ifndef __ASSEMBLY__
-extern char __spl_flash_end[];
-#endif
-#define CONFIG_SYS_UBOOT_BASE		__spl_flash_end
-#define CONFIG_SYS_SPL_MAX_LEN		(32 << 10)
-#define CONFIG_SYS_UBOOT_START		0x1000100
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h
deleted file mode 100644
index 6a26269807..0000000000
--- a/include/configs/a4m072.h
+++ /dev/null
@@ -1,324 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2010
- * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU */
-#define CONFIG_A4M072		1	/* ... on A4M072 board */
-#define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM */
-
-#define CONFIG_SYS_TEXT_BASE	0xFE000000
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-/* define to enable silent console */
-#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device */
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-
-#if defined(CONFIG_PCI)
-#define CONFIG_PCI_SCAN_SHOW	1
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-#endif
-
-#define CONFIG_SYS_XLB_PIPELINING	1
-
-#undef CONFIG_EEPRO100
-
-/* USB */
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_OHCI_BE_CONTROLLER
-#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
-#define CONFIG_SYS_USB_OHCI_REGS_BASE	MPC5XXX_USB
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"mpc5200"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_PCI
-#endif
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)		/* Boot low with 32 MB Flash */
-#define CONFIG_SYS_LOWBOOT		1
-#define CONFIG_SYS_LOWBOOT32		1
-#endif
-
-/*
- * Autobooting
- */
-
-#define CONFIG_SYS_AUTOLOAD	"n"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_PREBOOT				"run try_update"
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"bk=run add_mtd ; run add_consolespec ; bootm 200000\0"		\
-	"cf1=diskboot 200000 0:1\0"					\
-	"bootcmd_cf1=run bcf1\0"					\
-	"bcf=setenv bootargs root=/dev/hda3\0"				\
-	"bootcmd_nfs=run bnfs\0"					\
-	"norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs "\
-		"panic=1\0"						\
-	"bootcmd_nor=cp.b ${kernel_addr} 200000 100000;"		\
-			"run norargs addip; run bk\0"			\
-	"bnfs=nfs 200000 ${rootpath}/boot/uImage;"			\
-			"run nfsargs addip ; run bk\0"			\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-				"nfsroot=${serverip}:${rootpath}\0"	\
-	"try_update=usb start;sleep 2;usb start;sleep 1;"		\
-			"fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;"	\
-			"source 2F0000\0"				\
-	"env_addr=FE060000\0"						\
-	"kernel_addr=FE100000\0"					\
-	"rootfs_addr=FE200000\0"					\
-	"add_mtd=setenv bootargs ${bootargs} mtdparts="			\
-		"phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0"	\
-	"bcf1=run cf1; run bcf; run addip; run bk\0"			\
-	"add_consolespec=setenv bootargs ${bootargs} "			\
-				"console=/dev/null quiet\0"		\
-	"addip=if test -n ${ethaddr};"					\
-		"then if test -n ${ipaddr};"				\
-			"then setenv bootargs ${bootargs} "		\
-				"ip=${ipaddr}:${serverip}:${gatewayip}:"\
-				"${netmask}:${hostname}:${netdev}:off;"	\
-			"fi;"						\
-		"else;"							\
-			"setenv bootargs ${bootargs} no_ethaddr;"	\
-		"fi\0"							\
-	"hostname=CPUP0\0"						\
-	"netdev=eth0\0"							\
-	"bootcmd=run bootcmd_nor\0" 					\
-	""
-/*
- * IPB Bus clocking configuration.
- */
-#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE		0xFE000000
-#define CONFIG_SYS_FLASH_SIZE		0x02000000
-#if !defined(CONFIG_SYS_LOWBOOT)
-#error "CONFIG_SYS_LOWBOOT not defined?"
-#else	/* CONFIG_SYS_LOWBOOT */
-#if defined(CONFIG_SYS_LOWBOOT32)
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00060000)
-#endif
-#endif	/* CONFIG_SYS_LOWBOOT */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_CS0_START}
-#define CONFIG_SYS_FLASH_BANKS_SIZES	{CONFIG_SYS_CS0_SIZE}
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_SIZE		0x10000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
-
-#define CONFIG_ENV_OVERWRITE	1
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE		MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII100
-/*
- * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
- */
-/* #define CONFIG_MPC5xxx_FEC_MII10 */
-#define CONFIG_PHY_ADDR		0x1f
-#define CONFIG_PHY_TYPE		0x79c874		/* AMD Phy Controller */
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x18000004
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_CMDLINE_EDITING	1
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-/* Flash at CSBoot, CS0 */
-#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x0002DD00
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-/* External SRAM at CS1 */
-#define CONFIG_SYS_CS1_START		0x62000000
-#define CONFIG_SYS_CS1_SIZE		0x00400000
-#define CONFIG_SYS_CS1_CFG		0x00009930
-#define CONFIG_SYS_SRAM_BASE		CONFIG_SYS_CS1_START
-#define CONFIG_SYS_SRAM_SIZE		CONFIG_SYS_CS1_SIZE
-/* LED display at CS7 */
-#define CONFIG_SYS_CS7_START		0x6a000000
-#define CONFIG_SYS_CS7_SIZE		(64*1024)
-#define CONFIG_SYS_CS7_CFG		0x0000bf30
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE		0x33333003
-
-#define CONFIG_SYS_RESET_ADDRESS	0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK	0x0001BBBB
-#define CONFIG_USB_CONFIG	0x00001000 /* 0x4000 for SE mode */
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 2 drives per IDE bus	*/
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
-
-/* Offset for data I/O			*/
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
-
-/* Offset for normal register accesses	*/
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers	*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
-
-/* Interval between registers                                                */
-#define CONFIG_SYS_ATA_STRIDE          4
-
-#define CONFIG_ATAPI                   1
-
-/*-----------------------------------------------------------------------
- * Open firmware flat tree support
- *-----------------------------------------------------------------------
- */
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_SOC			"soc5200@f0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
-
-/* Support for the 7-segment display */
-#define CONFIG_SYS_DISP_CHR_RAM	     CONFIG_SYS_CS7_START
-#define CONFIG_SHOW_ACTIVITY		/* used for display realization */
-
-#define CONFIG_SHOW_BOOT_PROGRESS
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h
deleted file mode 100644
index 4eb8f39aaf..0000000000
--- a/include/configs/ac14xx.h
+++ /dev/null
@@ -1,516 +0,0 @@
-/*
- * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
- * (C) Copyright 2010 DAVE Srl <www.dave.eu>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * ifm AC14xx (MPC5121e based) board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_AC14XX 1
-
-/*
- * Memory map for the ifm AC14xx board:
- *
- * 0x0000_0000-0x0FFF_FFFF	DDR RAM (256 MB)
- * 0x3000_0000-0x3001_FFFF	On Chip SRAM (128 KB)
- * 0x8000_0000-0x803F_FFFF	IMMR (4 MB)
- * 0xE000_0000-0xEFFF_FFFF	several LPB attached hardware (CSx)
- * 0xFC00_0000-0xFFFF_FFFF	NOR Boot FLASH (64 MB)
- */
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300		1	/* E300 Family */
-
-#define CONFIG_SYS_TEXT_BASE	0xFFF00000
-
-#define CONFIG_SYS_MPC512X_CLKIN	25000000	/* in Hz */
-#define SCFR1_IPS_DIV			2
-#define SCFR1_LPC_DIV			2
-#define SCFR1_NFC_DIV			2
-#define SCFR1_DIU_DIV			240
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_IMMR			0x80000000
-#define CONFIG_SYS_DIU_ADDR		(CONFIG_SYS_IMMR + 0x2100)
-
-/* more aggressive 'mtest' over a wider address range */
-#define CONFIG_SYS_ALT_MEMTEST
-#define CONFIG_SYS_MEMTEST_START	0x00100000      /* memtest region */
-#define CONFIG_SYS_MEMTEST_END		0x0FE00000
-
-/*
- * DDR Setup - manually set all parameters as there's no SPD etc.
- */
-#define CONFIG_SYS_DDR_SIZE		256		/* MB */
-#define CONFIG_SYS_DDR_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_MAX_RAM_SIZE		0x20000000
-
-/*
- * DDR Controller Configuration
- *
- * SYS_CFG:
- *	[31:31]	MDDRC Soft Reset:	Diabled
- *	[30:30]	DRAM CKE pin:		Enabled
- *	[29:29]	DRAM CLK:		Enabled
- *	[28:28]	Command Mode:		Enabled (For initialization only)
- *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
- *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
- *	[20:19]	Read Test:		DON'T USE
- *	[18:18]	Self Refresh:		Enabled
- *	[17:17]	16bit Mode:		Disabled
- *	[16:13] Ready Delay:		2
- *	[12:12]	Half DQS Delay:		Disabled
- *	[11:11]	Quarter DQS Delay:	Disabled
- *	[10:08]	Write Delay:		2
- *	[07:07]	Early ODT:		Disabled
- *	[06:06]	On DIE Termination:	Disabled
- *	[05:05]	FIFO Overflow Clear:	DON'T USE here
- *	[04:04]	FIFO Underflow Clear:	DON'T USE here
- *	[03:03]	FIFO Overflow Pending:	DON'T USE here
- *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
- *	[01:01]	FIFO Overlfow Enabled:	Enabled
- *	[00:00]	FIFO Underflow Enabled:	Enabled
- * TIME_CFG0
- *	[31:16]	DRAM Refresh Time:	0 CSB clocks
- *	[15:8]	DRAM Command Time:	0 CSB clocks
- *	[07:00]	DRAM Precharge Time:	0 CSB clocks
- * TIME_CFG1
- *	[31:26]	DRAM tRFC:
- *	[25:21]	DRAM tWR1:
- *	[20:17]	DRAM tWRT1:
- *	[16:11]	DRAM tDRR:
- *	[10:05]	DRAM tRC:
- *	[04:00]	DRAM tRAS:
- * TIME_CFG2
- *	[31:28]	DRAM tRCD:
- *	[27:23]	DRAM tFAW:
- *	[22:19]	DRAM tRTW1:
- *	[18:15]	DRAM tCCD:
- *	[14:10] DRAM tRTP:
- *	[09:05]	DRAM tRP:
- *	[04:00] DRAM tRPA
- */
-
-/*
- * NOTE: although this board uses DDR1 only, the common source brings defaults
- * for DDR2 init sequences, that's why we have to keep those here as well
- */
-
-/* DDR1 -- 32bit, drive strength (pad configuration) 3 for control and data */
-#define CONFIG_SYS_IOCTRL_MUX_DDR	((0 << 6) | (3 << 3) | (3 << 0))
-
-#define CONFIG_SYS_MDDRC_SYS_CFG (/* 0xEAA09100 */ 0 \
-			| (1 << 31)	/* RST_B */ \
-			| (1 << 30)	/* CKE */ \
-			| (1 << 29)	/* CLK_ON */ \
-			| (0 << 28)	/* CMD_MODE */ \
-			| (5 << 25)	/* DRAM_ROW_SELECT */ \
-			| (5 << 21)	/* DRAM_BANK_SELECT */ \
-			| (0 << 18)	/* SELF_REF_EN */ \
-			| (0 << 17)	/* 16BIT_MODE */ \
-			| (4 << 13)	/* RDLY */ \
-			| (1 << 12)	/* HALF_DQS_DLY */ \
-			| (0 << 11)	/* QUART_DQS_DLY */ \
-			| (1 <<  8)	/* WDLY */ \
-			| (0 <<  7)	/* EARLY_ODT */ \
-			| (0 <<  6)	/* ON_DIE_TERMINATE */ \
-			| (0 <<  5)	/* FIFO_OV_CLEAR */ \
-			| (0 <<  4)	/* FIFO_UV_CLEAR */ \
-			| (0 <<  1)	/* FIFO_OV_EN */ \
-			| (0 <<  0)	/* FIFO_UV_EN */ \
-			)
-
-#define CONFIG_SYS_MDDRC_TIME_CFG0	0x04E03124
-#define CONFIG_SYS_MDDRC_TIME_CFG1	0x30CA1147
-#define CONFIG_SYS_MDDRC_TIME_CFG2	0x32B10864
-
-/* register address only, i.e. template without values */
-#define CONFIG_SYS_MICRON_BMODE		0x01000000
-#define CONFIG_SYS_MICRON_EMODE		0x01010000
-#define CONFIG_SYS_MICRON_EMODE2	0x01020000
-#define CONFIG_SYS_MICRON_EMODE3	0x01030000
-/*
- * values for mode registers (without mode register address)
- */
-/* CAS 2.5 (6), burst seq (0) and length 4 (2) */
-#define CONFIG_SYS_MICRON_BMODE_PARAM	0x00000062
-#define CONFIG_SYS_MICRON_BMODE_RSTDLL	0x00000100
-/* DLL enable, reduced drive strength */
-#define CONFIG_SYS_MICRON_EMODE_PARAM	0x00000002
-
-#define CONFIG_SYS_DDRCMD_NOP		0x01380000
-#define CONFIG_SYS_DDRCMD_PCHG_ALL	0x01100400
-#define CONFIG_SYS_MICRON_EMR	       ((1 << 24) |	/* CMD_REQ */ \
-					(0 << 22) |	/* DRAM_CS */ \
-					(0 << 21) |	/* DRAM_RAS */ \
-					(0 << 20) |	/* DRAM_CAS */ \
-					(0 << 19) |	/* DRAM_WEB */ \
-					(1 << 16) |	/* DRAM_BS[2:0] */ \
-					(0 << 15) |	/* */ \
-					(0 << 12) |	/* A12->out */ \
-					(0 << 11) |	/* A11->RDQS */ \
-					(0 << 10) |	/* A10->DQS# */ \
-					(0 <<  7) |	/* OCD program */ \
-					(0 <<  6) |	/* Rtt1 */ \
-					(0 <<  3) |	/* posted CAS# */ \
-					(0 <<  2) |	/* Rtt0 */ \
-					(1 <<  1) |	/* ODS */ \
-					(0 <<  0)	/* DLL */ \
-				     )
-#define CONFIG_SYS_MICRON_EMR2		0x01020000
-#define CONFIG_SYS_MICRON_EMR3		0x01030000
-#define CONFIG_SYS_DDRCMD_RFSH		0x01080000
-#define CONFIG_SYS_MICRON_INIT_DEV_OP	0x01000432
-#define CONFIG_SYS_MICRON_EMR_OCD      ((1 << 24) |	/* CMD_REQ */ \
-					(0 << 22) |	/* DRAM_CS */ \
-					(0 << 21) |	/* DRAM_RAS */ \
-					(0 << 20) |	/* DRAM_CAS */ \
-					(0 << 19) |	/* DRAM_WEB */ \
-					(1 << 16) |	/* DRAM_BS[2:0] */ \
-					(0 << 15) |	/* */ \
-					(0 << 12) |	/* A12->out */ \
-					(0 << 11) |	/* A11->RDQS */ \
-					(1 << 10) |	/* A10->DQS# */ \
-					(7 <<  7) |	/* OCD program */ \
-					(0 <<  6) |	/* Rtt1 */ \
-					(0 <<  3) |	/* posted CAS# */ \
-					(1 <<  2) |	/* Rtt0 */ \
-					(0 <<  1) |	/* ODS */ \
-					(0 <<  0)	/* DLL */ \
-				     )
-
-/*
- * Backward compatible definitions,
- * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c
- */
-#define	CONFIG_SYS_DDRCMD_EM2		(CONFIG_SYS_MICRON_EMR2)
-#define CONFIG_SYS_DDRCMD_EM3		(CONFIG_SYS_MICRON_EMR3)
-#define CONFIG_SYS_DDRCMD_EN_DLL	(CONFIG_SYS_MICRON_EMR)
-#define CONFIG_SYS_DDRCMD_OCD_DEFAULT	(CONFIG_SYS_MICRON_EMR_OCD)
-
-/* DDR Priority Manager Configuration */
-#define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
-#define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
-#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
-#define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
-#define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
-#define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
-#define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
-#define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
-#define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
-#define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
-#define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
-#define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
-#define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
-#define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111
-
-/*
- * NOR FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI				/* use the CFI code */
-#define CONFIG_FLASH_CFI_DRIVER				/* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE		0xFC000000	/* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE		0x04000000	/* max flash size */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ \
-	CONFIG_SYS_FLASH_BASE + 0 * CONFIG_SYS_FLASH_SIZE, \
-	}
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_PROTECTION
-
-/*
- * SRAM support
- */
-#define CONFIG_SYS_SRAM_BASE		0x30000000
-#define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
-
-/*
- * CS related parameters
- */
-/* CS0 Flash */
-#define CONFIG_SYS_CS0_CFG		0x00031110
-#define CONFIG_SYS_CS0_START		0xFC000000
-#define CONFIG_SYS_CS0_SIZE		0x04000000
-/* CS1 FRAM */
-#define CONFIG_SYS_CS1_CFG		0x00011000
-#define CONFIG_SYS_CS1_START		0xE0000000
-#define CONFIG_SYS_CS1_SIZE		0x00010000
-/* CS2 AS-i 1 */
-#define CONFIG_SYS_CS2_CFG		0x00009100
-#define CONFIG_SYS_CS2_START		0xE0100000
-#define CONFIG_SYS_CS2_SIZE		0x00080000
-/* CS3 netX */
-#define CONFIG_SYS_CS3_CFG		0x000A1140
-#define CONFIG_SYS_CS3_START		0xE0300000
-#define CONFIG_SYS_CS3_SIZE		0x00020000
-/* CS5 safety */
-#define CONFIG_SYS_CS5_CFG		0x0011F000
-#define CONFIG_SYS_CS5_START		0xE0400000
-#define CONFIG_SYS_CS5_SIZE		0x00010000
-/* CS6 AS-i 2 */
-#define CONFIG_SYS_CS6_CFG		0x00009100
-#define CONFIG_SYS_CS6_START		0xE0200000
-#define CONFIG_SYS_CS6_SIZE		0x00080000
-
-/* Don't use alternative CS timing for any CS */
-#define CONFIG_SYS_CS_ALETIMING		0x00000000
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE		0x00000020
-#define CONFIG_SYS_CS_HOLDCYCLE		0x00000020
-
-/* Use SRAM for initial stack */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
-
-#ifdef	CONFIG_FSL_DIU_FB
-#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)
-#else
-#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
-#endif
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX		1
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE		3	/* console on PSC3 */
-#define CONFIG_SYS_PSC3
-#if CONFIG_PSC_CONSOLE != 3
-#error CONFIG_PSC_CONSOLE must be 3
-#endif
-
-#define CONSOLE_FIFO_TX_SIZE		FIFOC_PSC3_TX_SIZE
-#define CONSOLE_FIFO_TX_ADDR		FIFOC_PSC3_TX_ADDR
-#define CONSOLE_FIFO_RX_SIZE		FIFOC_PSC3_RX_SIZE
-#define CONSOLE_FIFO_RX_ADDR		FIFOC_PSC3_RX_ADDR
-
-/*
- * Clocks in use
- */
-#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |		\
-			 CLOCK_SCCR1_LPC_EN |		\
-			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
-			 CLOCK_SCCR1_PSC_EN(7) |	\
-			 CLOCK_SCCR1_PSCFIFO_EN |	\
-			 CLOCK_SCCR1_DDR_EN |		\
-			 CLOCK_SCCR1_FEC_EN |		\
-			 CLOCK_SCCR1_TPR_EN)
-
-#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\
-			 CLOCK_SCCR2_SPDIF_EN |		\
-			 CLOCK_SCCR2_DIU_EN |		\
-			 CLOCK_SCCR2_I2C_EN)
-
-#define CONFIG_CMDLINE_EDITING		1	/* command line history */
-
-/*
- * IIM - IC Identification Module
- */
-#undef CONFIG_FSL_IIM
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC512x_FEC		1
-#define CONFIG_PHY_ADDR			0x1F
-#define CONFIG_MII			1	/* MII PHY management */
-#define CONFIG_FEC_AN_TIMEOUT		1
-#define CONFIG_HAS_ETH0
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_FLASH		1
-/* This has to be a multiple of the flash sector size */
-#define CONFIG_ENV_ADDR			0xFFF40000
-#define CONFIG_ENV_SIZE			0x2000
-#define CONFIG_ENV_SECT_SIZE		0x20000
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR + \
-					 CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
-
-#define CONFIG_LOADS_ECHO		1
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1
-
-#define CONFIG_CMD_REGINFO
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_PCI
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-#ifdef CONFIG_CMD_KGDB
-# define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
-#else
-# define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
-#endif
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
-				 sizeof(CONFIG_SYS_PROMPT) + 16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS	32
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
-
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE		32768
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of 32 */
-#endif
-
-#define CONFIG_SYS_HID0_INIT		0x000000000
-#define CONFIG_SYS_HID0_FINAL		(HID0_ENABLE_MACHINE_CHECK | \
-					 HID0_ICE)
-#define CONFIG_SYS_HID2	HID2_HBE
-
-#define CONFIG_HIGH_BATS		1	/* High BATs supported */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE		230400	/* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_TIMESTAMP
-
-/* default load addr for tftp and bootm */
-#define CONFIG_LOADADDR		400000
-
-
-/* the builtin environment and standard greeting */
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#define CONFIG_EXTRA_ENV_SETTINGS_DEVEL					\
-	"muster_nr=-00\0"						\
-	"fromram=run ramargs addip addtty; "				\
-		"tftp ${fdt_addr_r} ac14xx/ac14xx.dtb${muster_nr}; "	\
-		"tftp ${kernel_addr_r} ac14xx/uImage${muster_nr}; "	\
-		"tftp ${ramdisk_addr_r} ac14xx/uFS${muster_nr}; "	\
-		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
-	"fromnfs=run nfsargs addip addtty; "				\
-		"tftp ${fdt_addr_r} ac14xx/ac14xx.dtb${muster_nr}; "	\
-		"tftp ${kernel_addr_r} ac14xx/uImage${muster_nr}; "	\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	"fromflash=run nfsargs addip addtty; "				\
-		"bootm fc020000 - fc000000\0"				\
-	"mtdargsrec=setenv bootargs root=/dev/mtdblock1 ro\0"		\
-	"recovery=run mtdargsrec addip addtty; "			\
-		"bootm ffd20000 - ffee0000\0"				\
-	"production=run ramargs addip addtty; "				\
-		"bootm fc020000 fc400000 fc000000\0"			\
-	"mtdargs=setenv bootargs root=/dev/mtdblock1 ro\0"		\
-	"prodmtd=run mtdargs addip addtty; "				\
-		"bootm fc020000 - fc000000\0"				\
-	""
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"u-boot_addr_r=200000\0"					\
-	"kernel_addr_r=600000\0"					\
-	"fdt_addr_r=a00000\0"						\
-	"ramdisk_addr_r=b00000\0"					\
-	"u-boot_addr=FFF00000\0"					\
-	"kernel_addr=FC020000\0"					\
-	"fdt_addr=FC000000\0"						\
-	"ramdisk_addr=FC400000\0"					\
-	"verify=n\0"							\
-	"ramdiskfile=ac14xx/uRamdisk\0"					\
-	"u-boot=ac14xx/u-boot.bin\0"					\
-	"bootfile=ac14xx/uImage\0"					\
-	"fdtfile=ac14xx/ac14xx.dtb\0"					\
-	"netdev=eth0\0"							\
-	"consdev=ttyPSC0\0"						\
-	"hostname=ac14xx\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}${muster_nr}\0"	\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} "				\
-		"console=${consdev},${baudrate}\0"			\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
-		"tftp ${fdt_addr_r} ${fdtfile};"			\
-		"run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	"net_self=tftp ${kernel_addr_r} ${bootfile};"			\
-		"tftp ${ramdisk_addr_r} ${ramdiskfile};"		\
-		"tftp ${fdt_addr_r} ${fdtfile};"			\
-		"run ramargs addip addtty;"				\
-		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
-	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
-	"update=protect off ${u-boot_addr} +${filesize};"		\
-		"era ${u-boot_addr} +${filesize};"			\
-		"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"	\
-	CONFIG_EXTRA_ENV_SETTINGS_DEVEL					\
-	"upd=run load update\0"						\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run production"
-
-#define CONFIG_ARP_TIMEOUT	200UL
-
-#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES	1
-
-#define OF_CPU			"PowerPC,5121@0"
-#define OF_SOC_COMPAT		"fsl,mpc5121-immr"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc@80000000/serial@11300"
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/aria.h b/include/configs/aria.h
deleted file mode 100644
index 0a7ef9919e..0000000000
--- a/include/configs/aria.h
+++ /dev/null
@@ -1,591 +0,0 @@
-/*
- * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
- * (C) Copyright 2009, DAVE Srl <www.dave.eu>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Aria board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_ARIA 1
-
-/*
- * Memory map for the ARIA board:
- *
- * 0x0000_0000-0x0FFF_FFFF	DDR RAM (256 MB)
- * 0x3000_0000-0x3001_FFFF	On Chip SRAM (128 KB)
- * 0x3010_0000-0x3011_FFFF	On Board SRAM (128 KB) - CS6
- * 0x3020_0000-0x3021_FFFF	FPGA (128 KB) - CS2
- * 0x8000_0000-0x803F_FFFF	IMMR (4 MB)
- * 0x8400_0000-0x82FF_FFFF	PCI I/O space (16 MB)
- * 0xA000_0000-0xAFFF_FFFF	PCI memory space (256 MB)
- * 0xB000_0000-0xBFFF_FFFF	PCI memory mapped I/O space (256 MB)
- * 0xFC00_0000-0xFFFF_FFFF	NOR Boot FLASH (64 MB)
- */
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300		1	/* E300 Family */
-#define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
-
-/* video */
-
-/* CONFIG_PCI is defined at config time */
-
-#define CONFIG_SYS_MPC512X_CLKIN	33000000	/* in Hz */
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_IMMR			0x80000000
-#define CONFIG_SYS_DIU_ADDR		(CONFIG_SYS_IMMR+0x2100)
-
-#define CONFIG_SYS_MEMTEST_START	0x00200000      /* memtest region */
-#define CONFIG_SYS_MEMTEST_END		0x00400000
-
-/*
- * DDR Setup - manually set all parameters as there's no SPD etc.
- */
-#define CONFIG_SYS_DDR_SIZE		256		/* MB */
-#define CONFIG_SYS_DDR_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_MAX_RAM_SIZE		0x20000000
-
-#define CONFIG_SYS_IOCTRL_MUX_DDR	0x00000036
-
-/* DDR Controller Configuration
- *
- * SYS_CFG:
- *	[31:31]	MDDRC Soft Reset:	Diabled
- *	[30:30]	DRAM CKE pin:		Enabled
- *	[29:29]	DRAM CLK:		Enabled
- *	[28:28]	Command Mode:		Enabled (For initialization only)
- *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
- *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
- *	[20:19]	Read Test:		DON'T USE
- *	[18:18]	Self Refresh:		Enabled
- *	[17:17]	16bit Mode:		Disabled
- *	[16:13] Ready Delay:		2
- *	[12:12]	Half DQS Delay:		Disabled
- *	[11:11]	Quarter DQS Delay:	Disabled
- *	[10:08]	Write Delay:		2
- *	[07:07]	Early ODT:		Disabled
- *	[06:06]	On DIE Termination:	Disabled
- *	[05:05]	FIFO Overflow Clear:	DON'T USE here
- *	[04:04]	FIFO Underflow Clear:	DON'T USE here
- *	[03:03]	FIFO Overflow Pending:	DON'T USE here
- *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
- *	[01:01]	FIFO Overlfow Enabled:	Enabled
- *	[00:00]	FIFO Underflow Enabled:	Enabled
- * TIME_CFG0
- *	[31:16]	DRAM Refresh Time:	0 CSB clocks
- *	[15:8]	DRAM Command Time:	0 CSB clocks
- *	[07:00]	DRAM Precharge Time:	0 CSB clocks
- * TIME_CFG1
- *	[31:26]	DRAM tRFC:
- *	[25:21]	DRAM tWR1:
- *	[20:17]	DRAM tWRT1:
- *	[16:11]	DRAM tDRR:
- *	[10:05]	DRAM tRC:
- *	[04:00]	DRAM tRAS:
- * TIME_CFG2
- *	[31:28]	DRAM tRCD:
- *	[27:23]	DRAM tFAW:
- *	[22:19]	DRAM tRTW1:
- *	[18:15]	DRAM tCCD:
- *	[14:10] DRAM tRTP:
- *	[09:05]	DRAM tRP:
- *	[04:00] DRAM tRPA
- */
-#define CONFIG_SYS_MDDRC_SYS_CFG     (	(1 << 31) |	/* RST_B */ \
-					(1 << 30) |	/* CKE */ \
-					(1 << 29) |	/* CLK_ON */ \
-					(0 << 28) |	/* CMD_MODE */ \
-					(4 << 25) |	/* DRAM_ROW_SELECT */ \
-					(3 << 21) |	/* DRAM_BANK_SELECT */ \
-					(0 << 18) |	/* SELF_REF_EN */ \
-					(0 << 17) |	/* 16BIT_MODE */ \
-					(2 << 13) |	/* RDLY */ \
-					(0 << 12) |	/* HALF_DQS_DLY */ \
-					(1 << 11) |	/* QUART_DQS_DLY */ \
-					(2 <<  8) |	/* WDLY */ \
-					(0 <<  7) |	/* EARLY_ODT */ \
-					(1 <<  6) |	/* ON_DIE_TERMINATE */ \
-					(0 <<  5) |	/* FIFO_OV_CLEAR */ \
-					(0 <<  4) |	/* FIFO_UV_CLEAR */ \
-					(0 <<  1) |	/* FIFO_OV_EN */ \
-					(0 <<  0) 	/* FIFO_UV_EN */ \
-				     )
-
-#define CONFIG_SYS_MDDRC_TIME_CFG0	0x030C3D2E
-#define CONFIG_SYS_MDDRC_TIME_CFG1	0x55D81189
-#define CONFIG_SYS_MDDRC_TIME_CFG2	0x34790863
-
-#define CONFIG_SYS_DDRCMD_NOP		0x01380000
-#define CONFIG_SYS_DDRCMD_PCHG_ALL	0x01100400
-#define CONFIG_SYS_MICRON_EMR	     (	(1 << 24) |	/* CMD_REQ */ \
-					(0 << 22) |	/* DRAM_CS */ \
-					(0 << 21) |	/* DRAM_RAS */ \
-					(0 << 20) |	/* DRAM_CAS */ \
-					(0 << 19) |	/* DRAM_WEB */ \
-					(1 << 16) |	/* DRAM_BS[2:0] */ \
-					(0 << 15) |	/* */ \
-					(0 << 12) |	/* A12->out */ \
-					(0 << 11) |	/* A11->RDQS */ \
-					(0 << 10) |	/* A10->DQS# */ \
-					(0 <<  7) |	/* OCD program */ \
-					(0 <<  6) |	/* Rtt1 */ \
-					(0 <<  3) |	/* posted CAS# */ \
-					(0 <<  2) |	/* Rtt0 */ \
-					(1 <<  1) |	/* ODS */ \
-					(0 <<  0)	/* DLL */ \
-				     )
-#define CONFIG_SYS_MICRON_EMR2		0x01020000
-#define CONFIG_SYS_MICRON_EMR3		0x01030000
-#define CONFIG_SYS_DDRCMD_RFSH		0x01080000
-#define CONFIG_SYS_MICRON_INIT_DEV_OP	0x01000432
-#define CONFIG_SYS_MICRON_EMR_OCD    (	(1 << 24) |	/* CMD_REQ */ \
-					(0 << 22) |	/* DRAM_CS */ \
-					(0 << 21) |	/* DRAM_RAS */ \
-					(0 << 20) |	/* DRAM_CAS */ \
-					(0 << 19) |	/* DRAM_WEB */ \
-					(1 << 16) |	/* DRAM_BS[2:0] */ \
-					(0 << 15) |	/* */ \
-					(0 << 12) |	/* A12->out */ \
-					(0 << 11) |	/* A11->RDQS */ \
-					(1 << 10) |	/* A10->DQS# */ \
-					(7 <<  7) |	/* OCD program */ \
-					(0 <<  6) |	/* Rtt1 */ \
-					(0 <<  3) |	/* posted CAS# */ \
-					(1 <<  2) |	/* Rtt0 */ \
-					(0 <<  1) |	/* ODS (Output Drive Strength) */ \
-					(0 <<  0)	/* DLL */ \
-				     )
-
-/*
- * Backward compatible definitions,
- * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c
- */
-#define	CONFIG_SYS_DDRCMD_EM2		(CONFIG_SYS_MICRON_EMR2)
-#define CONFIG_SYS_DDRCMD_EM3		(CONFIG_SYS_MICRON_EMR3)
-#define CONFIG_SYS_DDRCMD_EN_DLL	(CONFIG_SYS_MICRON_EMR)
-#define CONFIG_SYS_DDRCMD_OCD_DEFAULT	(CONFIG_SYS_MICRON_EMR_OCD)
-
-/* DDR Priority Manager Configuration */
-#define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
-#define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
-#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
-#define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
-#define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
-#define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
-#define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
-#define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
-#define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
-#define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
-#define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
-#define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
-#define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
-#define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111
-
-/*
- * NOR FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI				/* use the CFI code */
-#define CONFIG_FLASH_CFI_DRIVER				/* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE		0xF8000000	/* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE		0x08000000	/* max flash size */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* max sectors */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-
-/*
- * NAND FLASH support
- * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
- */
-#define CONFIG_CMD_NAND					/* enable NAND support */
-#define CONFIG_JFFS2_NAND				/* with JFFS2 on it */
-#define CONFIG_NAND_MPC5121_NFC
-#define CONFIG_SYS_NAND_BASE		0x40000000
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-
-/*
- * Configuration parameters for MPC5121 NAND driver
- */
-#define CONFIG_FSL_NFC_WIDTH		1
-#define CONFIG_FSL_NFC_WRITE_SIZE	2048
-#define CONFIG_FSL_NFC_SPARE_SIZE	64
-#define CONFIG_FSL_NFC_CHIPS		CONFIG_SYS_MAX_NAND_DEVICE
-
-#define CONFIG_SYS_SRAM_BASE		0x30000000
-#define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
-
-/* Make two SRAM regions contiguous */
-#define CONFIG_SYS_ARIA_SRAM_BASE	(CONFIG_SYS_SRAM_BASE + \
-					 CONFIG_SYS_SRAM_SIZE)
-#define CONFIG_SYS_ARIA_SRAM_SIZE	0x00100000	/* reserve 1MB-window */
-#define CONFIG_SYS_CS6_START		CONFIG_SYS_ARIA_SRAM_BASE
-#define CONFIG_SYS_CS6_SIZE		CONFIG_SYS_ARIA_SRAM_SIZE
-
-#define CONFIG_SYS_ARIA_FPGA_BASE	(CONFIG_SYS_ARIA_SRAM_BASE + \
-					 CONFIG_SYS_ARIA_SRAM_SIZE)
-#define CONFIG_SYS_ARIA_FPGA_SIZE	0x20000		/* 128 KB */
-
-#define CONFIG_SYS_CS2_START		CONFIG_SYS_ARIA_FPGA_BASE
-#define CONFIG_SYS_CS2_SIZE		CONFIG_SYS_ARIA_FPGA_SIZE
-
-#define CONFIG_SYS_CS0_CFG		0x05059150
-#define CONFIG_SYS_CS2_CFG		(	(5 << 24) | \
-						(5 << 16) | \
-						(1 << 15) | \
-						(0 << 14) | \
-						(0 << 13) | \
-						(1 << 12) | \
-						(0 << 10) | \
-						(3 <<  8) | /* 32 bit */ \
-						(0 <<  7) | \
-						(1 <<  6) | \
-						(1 <<  4) | \
-						(0 <<  3) | \
-						(0 <<  2) | \
-						(0 <<  1) | \
-						(0 <<  0)   \
-					)
-#define CONFIG_SYS_CS6_CFG		0x05059150
-
-/* Use alternative CS timing for CS0 and CS2 */
-#define CONFIG_SYS_CS_ALETIMING	0x00000005
-
-/* Use SRAM for initial stack */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE
-#define CONFIG_SYS_INIT_RAM_SIZE		CONFIG_SYS_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(384 * 1024)
-
-#ifdef	CONFIG_FSL_DIU_FB
-#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)
-#else
-#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
-#endif
-
-/* FPGA */
-#define CONFIG_ARIA_FPGA		1
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX		1
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE		3	/* console on PSC3 */
-#define CONFIG_SYS_PSC3
-#if CONFIG_PSC_CONSOLE != 3
-#error CONFIG_PSC_CONSOLE must be 3
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONSOLE_FIFO_TX_SIZE		FIFOC_PSC3_TX_SIZE
-#define CONSOLE_FIFO_TX_ADDR		FIFOC_PSC3_TX_ADDR
-#define CONSOLE_FIFO_RX_SIZE		FIFOC_PSC3_RX_SIZE
-#define CONSOLE_FIFO_RX_ADDR		FIFOC_PSC3_RX_ADDR
-
-#define CONFIG_CMDLINE_EDITING		1	/* command line history */
-
-/*
- * PCI
- */
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_SYS_PCI_MEM_BASE		0xA0000000
-#define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE		0x10000000	/* 256M */
-#define CONFIG_SYS_PCI_MMIO_BASE	(CONFIG_SYS_PCI_MEM_BASE + \
-					 CONFIG_SYS_PCI_MEM_SIZE)
-#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
-#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI_IO_BASE		0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS		0x84000000
-#define CONFIG_SYS_PCI_IO_SIZE		0x01000000	/* 16M */
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-
-#endif
-
-/*
- * IIM - IC Identification Module
- */
-#undef CONFIG_FSL_IIM
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC512x_FEC		1
-#define CONFIG_PHY_ADDR			0x17
-#define CONFIG_MII			1	/* MII PHY management */
-#define CONFIG_FEC_AN_TIMEOUT		1
-#define CONFIG_HAS_ETH0
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-/* This has to be a multiple of the flash sector size */
-#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + \
-					 CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SIZE			0x2000
-#define CONFIG_ENV_SECT_SIZE		0x20000	/* one sector (256K) */
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR + \
-					 CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
-
-#define CONFIG_LOADS_ECHO		1
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1
-
-#define CONFIG_CMD_REGINFO
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_PCI
-#endif
-
-/*
- * Dynamic MTD partition support
- */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT		"nor0=f8000000.flash,nand0=mpc5121.nand"
-
-/*
- * NOR flash layout:
- *
- * F8000000 - FEAFFFFF	107 MiB		User Data
- * FEB00000 - FFAFFFFF	 16 MiB		Root File System
- * FFB00000 - FFFEFFFF	  4 MiB		Linux Kernel
- * FFF00000 - FFFBFFFF	768 KiB		U-Boot (up to 512 KiB) and 2 x * env
- * FFFC0000 - FFFFFFFF	256 KiB		Device Tree
- *
- * NAND flash layout: one big partition
- */
-#define MTDPARTS_DEFAULT	"mtdparts=f8000000.flash:107m(user),"	\
-						"16m(rootfs),"		\
-						"4m(kernel),"		\
-						"768k(u-boot),"		\
-						"256k(dtb);"		\
-					"mpc5121.nand:-(data)"
-
-/*
- * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
- * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE
- * is set to 0xFFFF, watchdog timeouts after about 64s. For details
- * refer to chapter 36 of the MPC5121e Reference Manual.
- */
-/* #define CONFIG_WATCHDOG */		/* enable watchdog */
-#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
-
- /*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-#ifdef CONFIG_CMD_KGDB
-# define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
-#else
-# define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
-#endif
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
-				 sizeof(CONFIG_SYS_PROMPT) + 16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS	32
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
-
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE		32768
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of 32 */
-#endif
-
-#define CONFIG_SYS_HID0_INIT		0x000000000
-#define CONFIG_SYS_HID0_FINAL		(HID0_ENABLE_MACHINE_CHECK | \
-					 HID0_ICE)
-#define CONFIG_SYS_HID2	HID2_HBE
-
-#define CONFIG_HIGH_BATS		1	/* High BATs supported */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE		230400	/* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_TIMESTAMP
-
-#define CONFIG_HOSTNAME			aria
-#define CONFIG_BOOTFILE			"aria/uImage"
-#define CONFIG_ROOTPATH			"/opt/eldk/ppc_6xx"
-
-#define CONFIG_LOADADDR			400000	/* default load addr */
-
-#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"u-boot_addr_r=200000\0"					\
-	"kernel_addr_r=600000\0"					\
-	"fdt_addr_r=880000\0"						\
-	"ramdisk_addr_r=900000\0"					\
-	"u-boot_addr=FFF00000\0"					\
-	"kernel_addr=FFB00000\0"					\
-	"fdt_addr=FFFC0000\0"						\
-	"ramdisk_addr=FEB00000\0"					\
-	"ramdiskfile=aria/uRamdisk\0"				\
-	"u-boot=aria/u-boot.bin\0"					\
-	"fdtfile=aria/aria.dtb\0"					\
-	"netdev=eth0\0"							\
-	"consdev=ttyPSC0\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} "				\
-		"console=${consdev},${baudrate}\0"			\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
-		"tftp ${fdt_addr_r} ${fdtfile};"			\
-		"run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	"net_self=tftp ${kernel_addr_r} ${bootfile};"			\
-		"tftp ${ramdisk_addr_r} ${ramdiskfile};"		\
-		"tftp ${fdt_addr_r} ${fdtfile};"			\
-		"run ramargs addip addtty;"				\
-		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
-	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
-	"update=protect off ${u-boot_addr} +${filesize};"		\
-		"era ${u-boot_addr} +${filesize};"			\
-		"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"	\
-	"upd=run load update\0"						\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES	1
-
-#define OF_CPU			"PowerPC,5121@0"
-#define OF_SOC_COMPAT		"fsl,mpc5121-immr"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc@80000000/serial@11300"
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-
-#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for IDE not supported	*/
-
-#define CONFIG_IDE_RESET		/* reset for IDE supported	*/
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS		1	/* 1 IDE bus		*/
-#define CONFIG_SYS_IDE_MAXDEVICE	2	/* 1 drive per IDE bus	*/
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-#define CONFIG_SYS_ATA_BASE_ADDR	get_pata_base()
-
-/* Offset for data I/O			RefMan MPC5121EE Table 28-10	*/
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x00A0)
-
-/* Offset for normal register accesses	*/
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers	RefMan MPC5121EE Table 28-23	*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x00D8)
-
-/* Interval between registers	*/
-#define CONFIG_SYS_ATA_STRIDE		4
-
-#define ATA_BASE_ADDR			get_pata_base()
-
-/*
- * Control register bit definitions
- */
-#define FSL_ATA_CTRL_FIFO_RST_B		0x80000000
-#define FSL_ATA_CTRL_ATA_RST_B		0x40000000
-#define FSL_ATA_CTRL_FIFO_TX_EN		0x20000000
-#define FSL_ATA_CTRL_FIFO_RCV_EN	0x10000000
-#define FSL_ATA_CTRL_DMA_PENDING	0x08000000
-#define FSL_ATA_CTRL_DMA_ULTRA		0x04000000
-#define FSL_ATA_CTRL_DMA_WRITE		0x02000000
-#define FSL_ATA_CTRL_IORDY_EN		0x01000000
-
-/* Clocks in use */
-#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
-			 CLOCK_SCCR1_LPC_EN |				\
-			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
-			 CLOCK_SCCR1_PSCFIFO_EN |			\
-			 CLOCK_SCCR1_DDR_EN |				\
-			 CLOCK_SCCR1_FEC_EN |				\
-			 CLOCK_SCCR1_NFC_EN |				\
-			 CLOCK_SCCR1_PATA_EN |				\
-			 CLOCK_SCCR1_PCI_EN |				\
-			 CLOCK_SCCR1_TPR_EN)
-
-#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\
-			 CLOCK_SCCR2_SPDIF_EN |		\
-			 CLOCK_SCCR2_DIU_EN |		\
-			 CLOCK_SCCR2_I2C_EN)
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/canmb.h b/include/configs/canmb.h
deleted file mode 100644
index b7c74b4264..0000000000
--- a/include/configs/canmb.h
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * (C) Copyright 2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU */
-#define CONFIG_CANMB		1	/* ... on canmb board - we need this for FEC.C */
-
-/*
- * allowed and functional CONFIG_SYS_TEXT_BASE values:
- * 0xfe000000	low boot at 0x00000100 (default board setting)
- * 0x00100000	RAM load and test
- */
-#define	CONFIG_SYS_TEXT_BASE	0xFE000000
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_BOARD_EARLY_INIT_R
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_REGINFO
-
-/*
- * MUST be low boot - HIGHBOOT is not supported anymore
- */
-#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)		/* Boot low with 32 MB Flash */
-#   define CONFIG_SYS_LOWBOOT		1
-#   define CONFIG_SYS_LOWBOOT16	1
-#else
-#   error "CONFIG_SYS_TEXT_BASE must be 0xFE000000"
-#endif
-
-/*
- * Autobooting
- */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip;"					\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
-	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"bootfile=/tftpboot/canmb/uImage\0"				\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-/*
- * IPB Bus clocking configuration.
- */
-#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-
-/*
- * Flash configuration, expect one 16 Megabyte Bank at most
- */
-#define CONFIG_SYS_FLASH_BASE		0xFE000000
-#define CONFIG_SYS_FLASH_SIZE		0x02000000
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_OFFSET		(2*128*1024)
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE       (128*1024)
-
-/*
- * Memory map
- *
- * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
- */
-#define CONFIG_SYS_MBAR			0xf0000000	/* DO NOT CHANGE this */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII100
-#define	CONFIG_PHY_ADDR		0x0
-/*
- * GPIO configuration:
- * PSC1,2,3 predefined as UART
- * PCI disabled
- * Ethernet 100 with MD
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x00058444
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#  define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x01f00000	/* 1 ... 31 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
-
-#define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x00047D01
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
-
-#define CONFIG_SYS_RESET_ADDRESS	0x7f000000
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/charon.h b/include/configs/charon.h
deleted file mode 100644
index 913b707a5f..0000000000
--- a/include/configs/charon.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004-2006
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * (C) Copyright 2010
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_CHARON_H
-#define __CONFIG_CHARON_H
-
-#define CONFIG_CHARON
-#define CONFIG_HOSTNAME		charon
-
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x81550414
-
-/* include common defines/options for TQM52xx boards */
-#include "TQM5200.h"
-
-/* defines special on charon board */
-#undef CONFIG_RTC_MPC5200
-
-#undef CUSTOM_ENV_SETTINGS
-#define CUSTOM_ENV_SETTINGS					\
-	"bootfile=/tftpboot/charon/uImage\0"			\
-	"fdt_file=/tftpboot/charon/charon.dtb\0"		\
-	"u-boot=/tftpboot/charon/u-boot.bin\0"			\
-	"mtdparts=" MTDPARTS_DEFAULT "\0"			\
-	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"
-
-/* additional features on charon board */
-#define CONFIG_RESET_PHY_R
-
-/*
- * I2C configuration
- */
-#define CONFIG_I2C_MULTI_BUS
-
-#define CONFIG_SYS_TFP410_ADDR	0x38
-#define CONFIG_SYS_TFP410_BUS	0
-
-/*
- * FPGA configuration
- */
-#define CONFIG_SYS_CS3_START		0xE8000000
-#define CONFIG_SYS_CS3_SIZE		0x80000	/* 512 KByte */
-
-/*
- * CS3 Config Register Init:
- * 	CS3 Enabled
- * 	AddrBus: 8bits
- *  	DataBus: 4bytes
- *  	Multiplexed: Yes
- *  	MuxBank: 00
- */
-#define CONFIG_SYS_CS3_CFG		0x00009310
-
-#endif /* __CONFIG_CHARON_H */
diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h
deleted file mode 100644
index 3777a0d863..0000000000
--- a/include/configs/cm5200.h
+++ /dev/null
@@ -1,286 +0,0 @@
-/*
- * (C) Copyright 2003-2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
-#define CONFIG_CM5200		1	/* ... on CM5200 platform */
-
-#define	CONFIG_SYS_TEXT_BASE	0xfc000000
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/*
- * Supported commands
- */
-#define CONFIG_CMD_REGINFO
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR		0x00
-#define CONFIG_ENV_OVERWRITE	1	/* allow overwriting of ethaddr */
-/* use misc_init_r() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
-#define CONFIG_MISC_INIT_R	1
-#define CONFIG_MAC_OFFSET	0x35	/* MAC address offset in I2C EEPROM */
-
-/*
- * POST support
- */
-#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU)
-#define MPC5XXX_SRAM_POST_SIZE	(MPC5XXX_SRAM_SIZE - 4)
-/* List of I2C addresses to be verified by POST */
-#define CONFIG_SYS_POST_I2C_ADDRS	{CONFIG_SYS_I2C_SLAVE,	\
-					 CONFIG_SYS_I2C_IO,	\
-					 CONFIG_SYS_I2C_EEPROM}
-
-/* display image timestamps */
-#define CONFIG_TIMESTAMP	1
-
-/*
- * Autobooting
- */
-#define CONFIG_PREBOOT	"echo;" \
-	"echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \
-	"echo"
-#undef CONFIG_BOOTARGS
-
-/*
- * Default environment settings
- */
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"netmask=255.255.0.0\0"						\
-	"ipaddr=192.168.160.33\0"					\
-	"serverip=192.168.1.1\0"					\
-	"gatewayip=192.168.1.1\0"					\
-	"console=ttyPSC0\0"						\
-	"u-boot_addr=100000\0"						\
-	"kernel_addr=200000\0"						\
-	"kernel_addr_flash=fc0c0000\0"					\
-	"fdt_addr=400000\0"						\
-	"fdt_addr_flash=fc0a0000\0"					\
-	"ramdisk_addr=500000\0"						\
-	"rootpath=/opt/eldk-4.1/ppc_6xx\0"				\
-	"u-boot=/tftpboot/cm5200/u-boot.bin\0"				\
-	"bootfile_fdt=/tftpboot/cm5200/uImage\0"			\
-	"fdt_file=/tftpboot/cm5200/cm5200.dtb\0"			\
-	"load=tftp ${u-boot_addr} ${u-boot}\0"				\
-	"update=prot off fc000000 +${filesize}; "			\
-		"era fc000000 +${filesize}; "				\
-		"cp.b ${u-boot_addr} fc000000 ${filesize}; "		\
-		"prot on fc000000 +${filesize}\0"			\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"flashargs=setenv bootargs root=/dev/mtdblock5 rw\0"		\
-	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
-	"addinit=setenv bootargs ${bootargs} init=/linuxrc\0"		\
-	"addcons=setenv bootargs ${bootargs} "				\
-		"console=${console},${baudrate}\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
-		"${netmask}:${hostname}:${netdev}:off panic=1\0"	\
-	"flash_flash=run flashargs addinit addip addcons;"		\
-		"bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0"	\
-	"net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; "		\
-		"tftp ${fdt_addr} ${fdt_file}; run nfsargs addip "	\
-		"addcons; bootm ${kernel_addr} - ${fdt_addr}\0"		\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_flash"
-
-/*
- * Low level configuration
- */
-
-/*
- * Clock configuration
- */
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000	/* SYS_XTAL_IN = 33MHz */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK	1	/* IPB = 133MHz */
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-#define CONFIG_SYS_LOWBOOT		1
-
-/* Use ON-Chip SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
-#else
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
-#endif
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_BOARD_TYPES	1	/* we use board_type */
-
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* 384 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* 256 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* initial mem map for Linux */
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_CFI		1
-#define CONFIG_FLASH_CFI_DRIVER	1
-#define CONFIG_SYS_FLASH_BASE		0xfc000000
-/* we need these despite using CFI */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sectors on one chip */
-#define CONFIG_SYS_FLASH_SIZE		0x02000000 /* 32 MiB */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT		1
-#undef CONFIG_SYS_LOWBOOT
-#endif
-
-/*
- * Chip selects configuration
- */
-/* Boot Chipselect */
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x00087D31	/* for pci_clk = 33 MHz */
-/* use board_early_init_r to enable flash write in CS_BOOT */
-#define CONFIG_BOARD_EARLY_INIT_R
-
-/* Flash memory addressing */
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-/* No burst, dead cycle = 1 for CS0 (Flash) */
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x00000001
-
-/*
- * SDRAM configuration
- * settings for k4s561632E-xx75, assuming XLB = 132 MHz
- */
-#define SDRAM_MODE	0x00CD0000	/* CASL 3, burst length 8 */
-#define SDRAM_CONTROL	0x514F0000
-#define SDRAM_CONFIG1	0xE2333900
-#define SDRAM_CONFIG2	0x8EE70000
-
-/*
- * MTD configuration
- */
-#define CONFIG_CMD_MTDPARTS	1
-#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT		"nor0=cm5200-0"
-#define MTDPARTS_DEFAULT	"mtdparts=cm5200-0:"			\
-					"384k(uboot),128k(env),"	\
-					"128k(redund_env),128k(dtb),"	\
-					"2m(kernel),27904k(rootfs),"	\
-					"-(config)"
-
-/*
- * RTC configuration
- */
-#define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
-
-/*
- * USB configuration
- */
-#define CONFIG_USB_OHCI		1
-#define CONFIG_USB_CLOCK	0x0001BBBB
-#define CONFIG_USB_CONFIG	0x00001000
-/* Partitions (for USB) */
-
-/*
- * Invoke our last_stage_init function - needed by fwupdate
- */
-#define CONFIG_LAST_STAGE_INIT	1
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_SIZE		0x10000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
-/* Configuration of redundant environment */
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-/*
- * Pin multiplexing configuration
- */
-
-/*
- * CS1/GPIO_WKUP_6: GPIO (default)
- * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1
- * IRDA/PSC6: UART
- * Ether: Ethernet 100Mbit with MD
- * PCI_DIS: PCI controller disabled
- * USB: USB
- * PSC3: SPI with UART3
- * PSC2: UART
- * PSC1: UART
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x10559C44
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		1	/* undef to save memory */
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_ALT_MEMTEST		1
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x03f00000	/* 1 .. 63 MiB in SDRAM */
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_XLB_PIPELINING	1	/* enable transaction pipeling */
-
-/*
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Flat Device Tree support
- */
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_SOC			"soc5200@f0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h
deleted file mode 100644
index 6710507a8d..0000000000
--- a/include/configs/digsy_mtc.h
+++ /dev/null
@@ -1,410 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2005-2007
- * Modified for InterControl digsyMTC MPC5200 board by
- * Frank Bodammer, GCD Hard- & Software GmbH,
- *                 frank.bodammer@gcd-solutions.de
- *
- * (C) Copyright 2009 Semihalf
- * Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-
-#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
-#define CONFIG_DIGSY_MTC	1	/* ... on InterControl digsyMTC board */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFFF00000	boot high (standard configuration)
- * 0xFE000000	boot low
- * 0x00100000	boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFFF00000	/* Standard: boot high */
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000
-
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	4	/* console is on PSC4  */
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#define CONFIG_PCI_SCAN_SHOW	1
-#define CONFIG_PCI_BOOTDELAY	250
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-
-#define CONFIG_BZIP2
-
-/*
- * Video
- */
-
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_MB862xx
-#define CONFIG_VIDEO_MB862xx_ACCEL
-#define CONFIG_VIDEO_CORALP
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* decompressed img */
-
-/* Coral-PA clock frequency, geo and other both 133MHz */
-#define CONFIG_SYS_MB862xx_CCF	0x00050000
-/* Video SDRAM parameters */
-#define CONFIG_SYS_MB862xx_MMR	0x11d7fa72
-#endif
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SAVES
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)
-#define CONFIG_SYS_LOWBOOT	1
-#endif
-
-/*
- * Autobooting
- */
-
-#undef	CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"fw_image=digsyMPC.img\0"					\
-	"mtcb_start=mtc led diag orange; run mtcb_1\0"			\
-	"mtcb_clearled=for x in user1 user2 usbpwr usbbusy; "		\
-		"do mtc led $x; done\0"					\
-	"mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; "	\
-		"else run mtcb_fw; fi\0"				\
-	"mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; "		\
-		"else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0"	\
-	"mtcb_update=mtc led user1 orange;"				\
-		"while mtc key; do ; done; run mtcb_2;\0"		\
-	"mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0"	\
-	"mtcb_usb1=if fatload usb 0 400000 script.img; "		\
-		"then run mtcb_doscript; else run mtcb_usb2; fi\0"	\
-	"mtcb_usb2=if fatload usb 0 400000 $fw_image; "			\
-		"then run mtcb_dousb; else run mtcb_ide; fi\0"		\
-	"mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; "	\
-		"run mtcb_wait_flickr mtcb_ds_1;\0"			\
-	"mtcb_ds_1=if imi 400000; then mtc led usbbusy; "		\
-		"source 400000; else run mtcb_error; fi\0"		\
-	"mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0"	\
-	"mtcb_du_1=if imi 400000; then run mtcb_du_2; "			\
-		"else run mtcb_error; fi\0"				\
-	"mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; "		\
-		"run mtcb_checkfw\0"					\
-	"mtcb_checkfw=if imi ff000000; then run mtcb_success; "		\
-		"else run mtcb_error; fi\0"				\
-	"mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0"	\
-	"mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0"		\
-	"mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\
-	"mtcb_uledflckr=mtc led user1 orange 11\0"			\
-	"mtcb_error=mtc led user1 red\0"				\
-	"mtcb_clear=erase ff000000 ff0fffff\0"				\
-	"mtcb_prog=cp.b 400000 ff000000 ${filesize}\0"			\
-	"mtcb_success=mtc led user1 green\0"				\
-	"mtcb_ide=if fatload ide 0 400000 $fw_image;"			\
-		"then run mtcb_doide; else run mtcb_error; fi\0"	\
-	"mtcb_doide=mtc led user2 green 1;"				\
-		"run mtcb_wait_flickr mtcb_di_1;\0"			\
-	"mtcb_di_1=if imi 400000; then run mtcb_di_2;"			\
-		"else run mtcb_error; fi\0"				\
-	"mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0"	\
-	"ramdisk_num_sector=16\0"					\
-	"flash_base=ff000000\0"						\
-	"flashdisk_size=e00000\0"					\
-	"env_sector=fff60000\0"						\
-	"flashdisk_start=ff100000\0"					\
-	"load_cmd=tftp 400000 digsyMPC.img\0"				\
-	"clear_cmd=erase ff000000 ff0fffff\0"				\
-	"flash_cmd=cp.b 400000 ff000000 ${filesize}\0"			\
-	"update_cmd=run load_cmd; "					\
-	"iminfo 400000; "						\
-	"run clear_cmd flash_cmd; "					\
-	"iminfo ff000000\0"						\
-	"spi_driver=yes\0"						\
-	"spi_watchdog=no\0"						\
-	"ftps_start=yes\0"						\
-	"ftps_user1=admin\0"						\
-	"ftps_pass1=admin\0"						\
-	"ftps_base1=/\0"						\
-	"ftps_home1=/\0"						\
-	"plc_sio_srv=no\0"						\
-	"plc_sio_baud=57600\0"						\
-	"plc_sio_parity=no\0"						\
-	"plc_sio_stop=1\0"						\
-	"plc_sio_com=2\0"						\
-	"plc_eth_srv=yes\0"						\
-	"plc_eth_port=1200\0"						\
-	"plc_root=/ide/\0"						\
-	"diag_level=0\0"						\
-	"webvisu=no\0"							\
-	"plc_can1_routing=no\0"						\
-	"plc_can1_baudrate=250\0"					\
-	"plc_can2_routing=no\0"						\
-	"plc_can2_baudrate=250\0"					\
-	"plc_can3_routing=no\0"						\
-	"plc_can3_baudrate=250\0"					\
-	"plc_can4_routing=no\0"						\
-	"plc_can4_baudrate=250\0"					\
-	"netdev=eth0\0"							\
-	"console=ttyPSC0\0"						\
-	"kernel_addr_r=400000\0"					\
-	"fdt_addr_r=600000\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-	"nfsroot=${serverip}:${rootpath}\0"				\
-	"addip=setenv bootargs ${bootargs} "				\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:"			\
-	"${netmask}:${hostname}:${netdev}:off panic=1\0"		\
-	"addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
-	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
-		"tftp ${fdt_addr_r} ${fdt_file};"			\
-		"run nfsargs addip addcons;"				\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	"load=tftp 200000 ${u-boot}\0"					\
-	"update=protect off FFF00000 +${filesize};"			\
-		"erase FFF00000 +${filesize};"				\
-		"cp.b 200000 FFF00000 ${filesize};"			\
-		"protect on FFF00000 +${filesize}\0"			\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run mtcb_start"
-
-/*
- * Flash configuration
- */
-#define	CONFIG_SYS_FLASH_CFI		1
-#define	CONFIG_FLASH_CFI_DRIVER	1
-
-#if defined(CONFIG_DIGSY_REV5)
-#define CONFIG_SYS_FLASH_BASE		0xFE000000
-#define CONFIG_SYS_FLASH_BASE_CS1	0xFC000000
-#define CONFIG_SYS_MAX_FLASH_BANKS	2
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, \
-					CONFIG_SYS_FLASH_BASE_CS1}
-#define CONFIG_SYS_UPDATE_FLASH_SIZE
-#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
-#else
-#define CONFIG_SYS_FLASH_BASE		0xFF000000
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-#endif
-
-#define CONFIG_SYS_MAX_FLASH_SECT	256
-#define CONFIG_FLASH_16BIT
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_SIZE	0x01000000
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500
-
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_SOC			"soc5200@f0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_MISC_INIT_R
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#if defined(CONFIG_LOWBOOT)
-#define CONFIG_ENV_ADDR		0xFF060000
-#else	/* CONFIG_LOWBOOT */
-#define CONFIG_ENV_ADDR		0xFFF60000
-#endif	/* CONFIG_LOWBOOT */
-#define CONFIG_ENV_SIZE		0x10000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_OVERWRITE	1
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#if !defined(CONFIG_SYS_LOWBOOT)
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-#else
-#define CONFIG_SYS_DEFAULT_MBAR	0xF0000000
-#endif
-
-/*
- *  Use SRAM until RAM will be available
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE		MPC5XXX_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	\
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN	(256 << 10)
-#define CONFIG_SYS_MALLOC_LEN	(4096 << 10)
-#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII100
-#if defined(CONFIG_DIGSY_REV5)
-#define CONFIG_PHY_ADDR		0x01
-#else
-#define CONFIG_PHY_ADDR		0x00
-#endif
-#define CONFIG_PHY_RESET_DELAY	1000
-
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-
-/*
- * GPIO configuration
- * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1)
- *  Bit 0   (mask 0x80000000) : 0x1
- * SPI on Tmr2/3/4/5 pins
- *  Bit 2:3 (mask 0x30000000) : 0x2
- * ATA cs0/1 on csb_4/5
- *  Bit 6:7 (mask 0x03000000) : 0x2
- * Ethernet 100Mbit with MD
- *  Bits 12:15 (mask 0x000f0000): 0x5
- * USB - Two UARTs
- *  Bits 18:19 (mask 0x00003000) : 0x2
- * PSC3 - USB2 on PSC3
- *  Bits 20:23 (mask 0x00000f00) : 0x1
- * PSC2 - CAN1&2 on PSC2 pins
- *  Bits 25:27 (mask 0x00000070) : 0x1
- * PSC1 - AC97 functionality
- *  Bits 29:31 (mask 0x00000007) : 0x2
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0xA2552112
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_AUTO_COMPLETE	1
-#define CONFIG_CMDLINE_EDITING	1
-
-#define CONFIG_MX_CYCLIC	1
-
-#define CONFIG_SYS_CBSIZE		1024
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS		32
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_ALT_MEMTEST
-#define CONFIG_SYS_MEMTEST_SCRATCH	0x00001000
-#define CONFIG_SYS_MEMTEST_START	0x00010000
-#define CONFIG_SYS_MEMTEST_END		0x019fffff
-
-#define CONFIG_SYS_LOAD_ADDR		0x00100000
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_SDRAM_CS1		1
-#define CONFIG_SYS_XLB_PIPELINING	1
-
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#if defined(CONFIG_SYS_LOWBOOT)
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x0002DD00
-#endif
-
-#define CONFIG_SYS_CS4_START		0x60000000
-#define CONFIG_SYS_CS4_SIZE		0x1000
-#define CONFIG_SYS_CS4_CFG		0x0008FC00
-
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_CS0_CFG		0x0002DD00
-
-#if defined(CONFIG_DIGSY_REV5)
-#define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH_BASE_CS1
-#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_CS1_CFG		0x0002DD00
-#endif
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x11111111
-
-#if !defined(CONFIG_SYS_LOWBOOT)
-#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
-#else
-#define CONFIG_SYS_RESET_ADDRESS	0xff000100
-#endif
-
-/*
- * USB
- */
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_OHCI_BE_CONTROLLER
-
-#define CONFIG_USB_CLOCK	0x00013333
-#define CONFIG_USB_CONFIG	0x00002000
-
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
-#define CONFIG_SYS_USB_OHCI_REGS_BASE	MPC5XXX_USB
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"mpc5200"
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-
-/*
- * IDE/ATA
- */
-#define CONFIG_IDE_RESET
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_ATA_CS_ON_I2C2
-#define CONFIG_SYS_IDE_MAXBUS		1
-#define CONFIG_SYS_IDE_MAXDEVICE	1
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
-#define CONFIG_SYS_ATA_STRIDE		4
-
-#define CONFIG_ATAPI		1
-#define CONFIG_LBA48		1
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
deleted file mode 100644
index d651eff4b2..0000000000
--- a/include/configs/inka4x0.h
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
- * (C) Copyright 2009
- * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
- *
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU	*/
-#define CONFIG_INKA4X0		1	/* INKA4x0 board		*/
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFFE00000	boot low
- * 0x00100000	boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFFE00000	/* Standard: boot low */
-#endif
-#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
-
-#define CONFIG_MISC_INIT_F	1	/* Use misc_init_f()			*/
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported			*/
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#define CONFIG_PCI_SCAN_SHOW	1
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-
-#define CONFIG_SYS_XLB_PIPELINING	1
-
-/* Partitions */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PCI
-
-#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFFE00000)		/* Boot low */
-#   define CONFIG_SYS_LOWBOOT		1
-#endif
-
-/*
- * Autobooting
- */
-
-#define CONFIG_PREBOOT	"echo;" \
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_IPADDR		192.168.100.2
-#define	CONFIG_SERVERIP		192.168.100.1
-#define	CONFIG_NETMASK		255.255.255.0
-#define HOSTNAME		inka4x0
-#define CONFIG_BOOTFILE		"/tftpboot/inka4x0/uImage"
-#define	CONFIG_ROOTPATH		"/opt/eldk/ppc_6xx"
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addcons=setenv bootargs ${bootargs} "				\
-		"console=ttyS0,${baudrate}\0"				\
-	"flash_nfs=run nfsargs addip addcons;"				\
-		"bootm ${kernel_addr}\0"				\
-	"net_nfs=tftp 200000 ${bootfile};"				\
-		"run nfsargs addip addcons;bootm\0"			\
-	"enable_disp=mw.l 100000 04000000 1;"				\
-		"cp.l 100000 f0000b20 1;"				\
-		"cp.l 100000 f0000b28 1\0"				\
-	"ideargs=setenv bootargs root=/dev/hda1 rw\0"			\
-	"ide_boot=ext2load ide 0:1 200000 uImage;"			\
-		"run ideargs addip addcons enable_disp;bootm\0"		\
-	"brightness=255\0"						\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run ide_boot"
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER	1
-#define CONFIG_SYS_FLASH_BASE		0xffe00000
-#define CONFIG_SYS_FLASH_SIZE		0x00200000
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x4000)
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x2000
-#define CONFIG_ENV_OVERWRITE	1
-#define CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-/*
- * SDRAM controller configuration
- */
-#undef CONFIG_SDR_MT48LC16M16A2
-#undef CONFIG_DDR_MT46V16M16
-#undef CONFIG_DDR_MT46V32M16
-#undef CONFIG_DDR_HYB25D512160BF
-#define CONFIG_DDR_K4H511638C
-
-/* Use ON-Chip SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-
-/* preserve space for the post_word at end of on-chip SRAM */
-#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
-
-#ifdef CONFIG_POST
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
-#else
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
-#endif
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII100
-/*
- * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
- */
-/* #define CONFIG_MPC5xxx_FEC_MII10 */
-#define CONFIG_PHY_ADDR		0x00
-#define CONFIG_MII
-
-/*
- * GPIO configuration
- *
- * use CS1 as gpio_wkup_6 output
- *	Bit 0 (mask: 0x80000000): 0
- * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
- *	00 -> No Alternatives, I2C1 is used for onboard EEPROM
- *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
- *	      EEPROM
- * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
- * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100
- * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100
- * use PSC6 as UART: Bits  9-11 (mask: 0x00700000): 0101
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x01501444
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/* Enable an alternate, more extensive memory test */
-#define CONFIG_SYS_ALT_MEMTEST
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x00087800 /* for pci_clk  = 66 MHz */
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-/* 32Mbit SRAM @0x30000000 */
-#define CONFIG_SYS_CS1_START		0x30000000
-#define CONFIG_SYS_CS1_SIZE		0x00400000
-#define CONFIG_SYS_CS1_CFG		0x31800 /* for pci_clk = 33 MHz */
-
-/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
-#define CONFIG_SYS_CS2_START		0x80000000
-#define CONFIG_SYS_CS2_SIZE		0x0001000
-#define CONFIG_SYS_CS2_CFG		0x21800  /* for pci_clk = 33 MHz */
-
-/* GPIO in @0x30400000 */
-#define CONFIG_SYS_CS3_START		0x30400000
-#define CONFIG_SYS_CS3_SIZE		0x00100000
-#define CONFIG_SYS_CS3_CFG		0x31800 /* for pci_clk = 33 MHz */
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_CLOCK	0x00015555
-#define CONFIG_USB_CONFIG	0x00001000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
-#define CONFIG_SYS_ATA_DATA_OFFSET	0x0060	/* Offset for data I/O		*/
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET	0x005C	/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_STRIDE          4	/* Interval between registers	*/
-
-#define CONFIG_ATAPI            1
-
-#define CONFIG_SYS_BRIGHTNESS          0xFF	/* LCD Default Brightness (255 = off) */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h
deleted file mode 100644
index c6390dbdbe..0000000000
--- a/include/configs/ipek01.h
+++ /dev/null
@@ -1,321 +0,0 @@
-/*
- * (C) Copyright 2006
- * MicroSys GmbH
- *
- * (C) Copyright 2009
- * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-
-#define CONFIG_MPC5200
-#define CONFIG_MPX5200		1	/* MPX5200 board */
-#define CONFIG_MPC5200_DDR	1	/* use DDR RAM */
-#define CONFIG_IPEK01           	/* Motherboard is ipek01 */
-
-#define	CONFIG_SYS_TEXT_BASE	0xfc000000
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz */
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_CACHELINE_SIZE	32 /* For MPC5xxx CPUs */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CACHELINE_SHIFT	5  /* log base 2 of the above value */
-#endif
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
-
-/*
- * Video configuration for LIME GDC
- */
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_MB862xx
-#define CONFIG_VIDEO_MB862xx_ACCEL
-#define VIDEO_FB_16BPP_WORD_SWAP
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* decompressed img */
-/* Lime clock frequency */
-#define CONFIG_SYS_MB862xx_CCF	0x90000	/* geo 166MHz other 133MHz */
-/* SDRAM parameter */
-#define CONFIG_SYS_MB862xx_MMR	0x41c767e3
-#endif
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#define CONFIG_PCI_SCAN_SHOW	1
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-
-#define CONFIG_MII		1
-#define CONFIG_EEPRO100		1
-#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
-
-/* USB */
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_OHCI_BE_CONTROLLER
-
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE		MPC5XXX_USB
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"mpc5200"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PCI		/* pciinfo */
-
-#define CONFIG_SYS_LOWBOOT	1
-
-/*
- * Autobooting
- */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"consoledev=ttyPSC0\0"						\
-	"hostname=ipek01\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} "				\
-		"console=${consoledev},${baudrate}\0"			\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr} - ${fdtaddr}\0"			\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0"	\
-	"net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};"  \
-		"run nfsargs addip addtty;"    				\
-		 "bootm ${loadaddr} - ${fdtaddr}\0"			\
-	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"bootfile=ipek01/uImage\0"					\
-	"load=tftp 100000 ipek01/u-boot.bin\0"				\
-	"update=protect off FC000000 +60000; era FC000000 +60000; "	\
-		"cp.b 100000 FC000000 ${filesize}\0"   			\
-	"upd=run load;run update\0"					\
-	"fdtaddr=800000\0"						\
-	"loadaddr=400000\0"						\
-	"fdtfile=ipek01/ipek01.dtb\0"					\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK 	/* for 133MHz */
-/* PCI clock must be 33, because board will not boot */
-#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* for 66MHz */
-
-/*
- * Open firmware flat tree support
- */
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_SOC			"soc5200@f0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-
-#define CONFIG_SYS_FLASH_BASE		0xFC000000
-#define CONFIG_SYS_FLASH_SIZE		0x01000000
-#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + \
-					 CONFIG_SYS_MONITOR_LEN)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1    /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	256  /* max num of sects on one chip */
-#define CONFIG_SYS_FLASH_PROTECTION  /* "Real" (hardware) sectors protection */
-
-/* use CFI flash driver */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH		1
-#define CONFIG_ENV_SIZE			0x10000
-#define CONFIG_ENV_SECT_SIZE		0x20000
-#define CONFIG_ENV_OVERWRITE		1
-#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR			0xf0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR		0x80000000
-#define	CONFIG_SYS_SRAM_BASE		0xF1000000
-#define	CONFIG_SYS_SRAM_SIZE		0x00200000
-#define	CONFIG_SYS_LIME_BASE		0xE4000000
-#define	CONFIG_SYS_LIME_SIZE		0x04000000
-#define	CONFIG_SYS_FPGA_BASE		0xC0000000
-#define	CONFIG_SYS_FPGA_SIZE		0x10000000
-#define	CONFIG_SYS_MPEG_BASE		0xe2000000
-#define	CONFIG_SYS_MPEG_SIZE		0x01000000
-#define CONFIG_SYS_CF_BASE		0xe1000000
-#define CONFIG_SYS_CF_SIZE		0x01000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-/* End of used area in DPRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE		MPC5XXX_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN	(384 << 10)  /* Reserve 384 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN	(4 << 20)    /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)    /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC		1
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR			0x00
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x1d556624
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
-#endif
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					 sizeof(CONFIG_SYS_PROMPT) + 16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS		16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1...15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000 /* default load address */
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_CS1_START		CONFIG_SYS_SRAM_BASE
-#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_SRAM_SIZE
-#define CONFIG_SYS_CS3_START		CONFIG_SYS_LIME_BASE
-#define CONFIG_SYS_CS3_SIZE		CONFIG_SYS_LIME_SIZE
-#define	CONFIG_SYS_CS6_START		CONFIG_SYS_FPGA_BASE
-#define	CONFIG_SYS_CS6_SIZE		CONFIG_SYS_FPGA_SIZE
-#define	CONFIG_SYS_CS5_START		CONFIG_SYS_CF_BASE
-#define	CONFIG_SYS_CS5_SIZE		CONFIG_SYS_CF_SIZE
-#define	CONFIG_SYS_CS7_START		CONFIG_SYS_MPEG_BASE
-#define	CONFIG_SYS_CS7_SIZE		CONFIG_SYS_MPEG_SIZE
-
-#ifdef CONFIG_SYS_PCISPEED_66
-#define CONFIG_SYS_BOOTCS_CFG		0x0006F900
-#define CONFIG_SYS_CS1_CFG		0x0004FB00
-#define CONFIG_SYS_CS2_CFG		0x0006F900
-#else
-#define CONFIG_SYS_BOOTCS_CFG		0x0002F900
-#define CONFIG_SYS_CS1_CFG		0x0001FB00
-#define CONFIG_SYS_CS2_CFG		0x0002F90C
-#endif
-
-/*
- * Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0
- * waitstates, writeswap and readswap enabled
- */
-#define CONFIG_SYS_CS3_CFG		0x00FFFB0C
-#define	CONFIG_SYS_CS6_CFG		0x00FFFB0C
-#define	CONFIG_SYS_CS7_CFG		0x4040751C
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE		0x33330000
-
-#define CONFIG_SYS_RESET_ADDRESS	0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK		0x0001BBBB
-#define CONFIG_USB_CONFIG		0x00005000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS		1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE	2 /* max. 2 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
-
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE		4
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h
deleted file mode 100644
index 4461623118..0000000000
--- a/include/configs/jupiter.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * (C) Copyright 2007
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
-#define CONFIG_JUPITER		1	/* ... on Jupiter board */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFFF00000	boot high (standard configuration)
- * 0x00100000	boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFFF00000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_BOARD_EARLY_INIT_R	1
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-
-#if defined(CONFIG_PCI)
-#define CONFIG_PCI_SCAN_SHOW	1
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-#endif
-
-#define CONFIG_SYS_XLB_PIPELINING	1
-
-#define CONFIG_MII		1
-#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
-
-/* Partitions */
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-
-#if defined(CONFIG_PCI)
-#define CODFIG_CMD_PCI
-#endif
-
-/*
- * Autobooting
- */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip addcons;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"addcons=setenv bootargs ${bootargs} console=${contyp},"	\
-		"${baudrate}\0"						\
-	"contyp=ttyS0\0"						\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;"	\
-		"bootm\0"						\
-	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"bootfile=/tftpboot/jupiter/uImage\0"				\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-/*
- * IPB Bus clocking configuration.
- */
-#undef CONFIG_SYS_IPBSPEED_133			/* define for 133MHz speed */
-
-#if 0
-/* pass open firmware flat tree */
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_SOC			"soc5200@f0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
-#endif
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE		0xFF000000
-#define CONFIG_SYS_FLASH_SIZE		0x01000000
-
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_TEXT_BASE + 0x40000) /* third sector */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks */
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
-#define CONFIG_SYS_UPDATE_FLASH_SIZE	1
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_SIZE		0x20000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_OVERWRITE	1
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII100
-/*
- * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
- */
-/* #define CONFIG_MPC5xxx_FEC_MII10 */
-#define CONFIG_PHY_ADDR		0x00
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x10000004
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
-#define CONFIG_SYS_ALT_MEMTEST		1
-
-#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x00047801
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
-
-#define CONFIG_SYS_RESET_ADDRESS	0xff000000
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/manroland/mpc5200-common.h b/include/configs/manroland/mpc5200-common.h
deleted file mode 100644
index 68874dc029..0000000000
--- a/include/configs/manroland/mpc5200-common.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * (C) Copyright 2009
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MANROLAND_MPC52XX__COMMON_H
-#define __MANROLAND_MPC52XX__COMMON_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC5200		1	/* MPC5200 CPU */
-
-/* ... running at 33.000000MHz	*/
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported		*/
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200,\
-					 230400 }
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */
-#   define CONFIG_SYS_LOWBOOT		1
-#endif
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE		0xFF800000
-
-#define CONFIG_SYS_FLASH_SIZE		0x00800000 /* 8 MByte */
-
-#define CONFIG_ENV_ADDR	(CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
-					   (= chip selects) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout [ms]*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout [ms]*/
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_SIZE		0x4000
-#define CONFIG_ENV_OFFSET_REDUND   (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND     (CONFIG_ENV_SIZE)
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE -\
-					 GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_SRAM_BASE	0x80100000	/* CS 1 */
-#define CONFIG_SYS_DISPLAY_BASE	0x80600000	/* CS 3 */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_DDR	 1
-#define SDRAM_MODE      0x018D0000
-#define SDRAM_EMODE     0x40090000
-#define SDRAM_CONTROL   0x714f0f00
-#define SDRAM_CONFIG1   0x73722930
-#define SDRAM_CONFIG2   0x47770000
-#define SDRAM_TAPDELAY  0x10000000
-
-/* Use ON-Chip SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
-#else
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
-#endif
-
-#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(192 << 10)
-#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR		0x00
-#define CONFIG_MII		1
-
-/*use  Hardware WDT */
-#define CONFIG_HW_WATCHDOG
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs	*/
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5 /* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-/* 8Mbit SRAM @0x80100000 */
-#define CONFIG_SYS_CS1_START		CONFIG_SYS_SRAM_BASE
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus	*/
-
-#define CONFIG_IDE_PREINIT	1
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
-
-/* Offset for data I/O			*/
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
-
-/* Offset for normal register accesses	*/
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers	*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
-
-/* Interval between registers	*/
-#define CONFIG_SYS_ATA_STRIDE          4
-
-#define CONFIG_ATAPI            1
-
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_SOC			"soc5200@f0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
-#define CONFIG_OF_IDE_FIXUP
-
-#endif /* __MANROLAND_MPC52XX__COMMON_H */
diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h
deleted file mode 100644
index 17a97dfc3a..0000000000
--- a/include/configs/mecp5123.h
+++ /dev/null
@@ -1,398 +0,0 @@
-/*
- * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
- * (C) Copyright 2009, DAVE Srl <www.dave.eu>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- * modifications for the MECP5123 by reinhard.arlt@esd-electronics.com
- *
- */
-
-/*
- * MECP5123 board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MECP5123 1
-
-/*
- * Memory map for the MECP5123 board:
- *
- * 0x0000_0000 - 0x1FFF_FFFF	DDR RAM (512 MB)
- * 0x3000_0000 - 0x3001_FFFF	SRAM (128 KB)
- * 0x8000_0000 - 0x803F_FFFF	IMMR (4 MB)
- * 0x8200_0000 - 0x8200_FFFF	VPC-3 (64 KB)
- * 0xFFC0_0000 - 0xFFFF_FFFF	NOR Boot FLASH (64 MB)
- */
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300		1	/* E300 Family */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
-
-#define CONFIG_SYS_MPC512X_CLKIN	33333333	/* in Hz */
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_IMMR		        0x80000000
-#define CONFIG_SYS_DIU_ADDR		(CONFIG_SYS_IMMR+0x2100)
-
-#define CONFIG_SYS_MEMTEST_START	0x00200000      /* memtest region */
-#define CONFIG_SYS_MEMTEST_END		0x00400000
-
-/*
- * DDR Setup - manually set all parameters as there's no SPD etc.
- */
-#define CONFIG_SYS_DDR_SIZE		512		/* MB */
-
-#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is sys memory*/
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_MAX_RAM_SIZE		0x20000000
-
-#define CONFIG_SYS_IOCTRL_MUX_DDR	0x00000036
-
-/* DDR Controller Configuration
- *
- * SYS_CFG:
- *	[31:31]	MDDRC Soft Reset:	Diabled
- *	[30:30]	DRAM CKE pin:		Enabled
- *	[29:29]	DRAM CLK:		Enabled
- *	[28:28]	Command Mode:		Enabled (For initialization only)
- *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
- *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
- *	[20:19]	Read Test:		DON'T USE
- *	[18:18]	Self Refresh:		Enabled
- *	[17:17]	16bit Mode:		Disabled
- *	[16:13] Ready Delay:		2
- *	[12:12]	Half DQS Delay:		Disabled
- *	[11:11]	Quarter DQS Delay:	Disabled
- *	[10:08]	Write Delay:		2
- *	[07:07]	Early ODT:		Disabled
- *	[06:06]	On DIE Termination:	Disabled
- *	[05:05]	FIFO Overflow Clear:	DON'T USE here
- *	[04:04]	FIFO Underflow Clear:	DON'T USE here
- *	[03:03]	FIFO Overflow Pending:	DON'T USE here
- *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
- *	[01:01]	FIFO Overlfow Enabled:	Enabled
- *	[00:00]	FIFO Underflow Enabled:	Enabled
- * TIME_CFG0
- *	[31:16]	DRAM Refresh Time:	0 CSB clocks
- *	[15:8]	DRAM Command Time:	0 CSB clocks
- *	[07:00]	DRAM Precharge Time:	0 CSB clocks
- * TIME_CFG1
- *	[31:26]	DRAM tRFC:
- *	[25:21]	DRAM tWR1:
- *	[20:17]	DRAM tWRT1:
- *	[16:11]	DRAM tDRR:
- *	[10:05]	DRAM tRC:
- *	[04:00]	DRAM tRAS:
- * TIME_CFG2
- *	[31:28]	DRAM tRCD:
- *	[27:23]	DRAM tFAW:
- *	[22:19]	DRAM tRTW1:
- *	[18:15]	DRAM tCCD:
- *	[14:10] DRAM tRTP:
- *	[09:05]	DRAM tRP:
- *	[04:00] DRAM tRPA
- */
-#define CONFIG_SYS_MDDRC_SYS_CFG	 0xEA804A00
-#define CONFIG_SYS_MDDRC_TIME_CFG0	 0x06183D2E
-#define CONFIG_SYS_MDDRC_TIME_CFG1	 0x68EC1168
-#define CONFIG_SYS_MDDRC_TIME_CFG2	 0x34310864
-
-#define CONFIG_SYS_DDRCMD_NOP		0x01380000
-#define CONFIG_SYS_DDRCMD_PCHG_ALL	0x01100400
-#define CONFIG_SYS_DDRCMD_EM2		0x01020000
-#define CONFIG_SYS_DDRCMD_EM3		0x01030000
-#define CONFIG_SYS_DDRCMD_EN_DLL	0x01010000
-#define CONFIG_SYS_DDRCMD_RFSH		0x01080000
-#define CONFIG_SYS_MICRON_INIT_DEV_OP	0x01000432
-#define CONFIG_SYS_DDRCMD_OCD_DEFAULT	0x01010780
-
-/* DDR Priority Manager Configuration */
-#define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
-#define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
-#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
-#define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
-#define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
-#define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
-#define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
-#define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
-#define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
-#define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
-#define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
-#define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
-#define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
-#define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111
-
-/*
- * NOR FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
-
-#define CONFIG_SYS_FLASH_BASE		0xFFC00000	/* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE		0x00400000	/* max flash size */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-
-/*
- * NAND FLASH
- * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
- */
-#define CONFIG_CMD_NAND
-#define CONFIG_NAND_MPC5121_NFC
-#define CONFIG_SYS_NAND_BASE            0x40000000
-#define CONFIG_SYS_MAX_NAND_DEVICE      1
-
-/*
- * Configuration parameters for MPC5121 NAND driver
- */
-#define CONFIG_FSL_NFC_WIDTH		1
-#define CONFIG_FSL_NFC_WRITE_SIZE	2048
-#define CONFIG_FSL_NFC_SPARE_SIZE	64
-#define CONFIG_FSL_NFC_CHIPS		1
-
-#define CONFIG_SYS_SRAM_BASE		0x30000000
-#define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
-
-/* Initialize Local Window for NOR FLASH access */
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-/* ALE active low, data size 4bytes */
-#define CONFIG_SYS_CS0_CFG		0x05051150
-
-/* Use not alternative CS timing */
-#define CONFIG_SYS_CS_ALETIMING		0x00000000
-
-/* ALE active low, data size 4bytes */
-#define CONFIG_SYS_CS1_CFG		0x1f1f3090
-#define CONFIG_SYS_VPC3_BASE		0x82000000	/* start of VPC3 space */
-#define CONFIG_SYS_VPC3_SIZE		0x00010000	/* max VPC3 size */
-/* Initialize Local Window for VPC3 access */
-#define CONFIG_SYS_CS1_START		CONFIG_SYS_VPC3_BASE
-#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_VPC3_SIZE
-
-/* Use SRAM for initial stack */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE /* Init RAM addr */
-#define CONFIG_SYS_INIT_RAM_SIZE		CONFIG_SYS_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* Start of monitor */
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Monitor length */
-#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024) /* Malloc size */
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX     1
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	3	/* console is on PSC3 */
-#define CONFIG_SYS_PSC3
-#if CONFIG_PSC_CONSOLE != 3
-#error CONFIG_PSC_CONSOLE must be 3
-#endif
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONSOLE_FIFO_TX_SIZE	FIFOC_PSC3_TX_SIZE
-#define CONSOLE_FIFO_TX_ADDR	FIFOC_PSC3_TX_ADDR
-#define CONSOLE_FIFO_RX_SIZE	FIFOC_PSC3_RX_SIZE
-#define CONSOLE_FIFO_RX_ADDR	FIFOC_PSC3_RX_ADDR
-
-/*
- * Clocks in use
- */
-#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
-			 CLOCK_SCCR1_LPC_EN |				\
-			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
-			 CLOCK_SCCR1_PSCFIFO_EN |			\
-			 CLOCK_SCCR1_DDR_EN |				\
-			 CLOCK_SCCR1_FEC_EN |				\
-			 CLOCK_SCCR1_NFC_EN |				\
-			 CLOCK_SCCR1_PCI_EN |				\
-			 CLOCK_SCCR1_TPR_EN)
-
-#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |	\
-			 CLOCK_SCCR2_I2C_EN)
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-
-/*
- * IIM - IC Identification Module
- */
-#undef CONFIG_FSL_IIM
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC512x_FEC	1
-#define CONFIG_PHY_ADDR		0x1
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_FEC_AN_TIMEOUT	1
-#define CONFIG_HAS_ETH0
-
-/*
- * Configure on-board RTC
- */
-#define CONFIG_SYS_RTC_BUS_NUM  0x01
-#define CONFIG_SYS_I2C_RTC_ADDR 0x32
-#define CONFIG_RTC_RX8025
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_NOWHERE		/* Store env in I2C EEPROM	*/
-#define CONFIG_ENV_SIZE		0x1000
-#define CONFIG_ENV_OFFSET       0x0000	/* environment starts here	*/
-
-#define CONFIG_LOADS_ECHO		/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change	*/
-
-#define CONFIG_CMD_REGINFO
-
-/*
- * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
- * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
- * to 0xFFFF, watchdog timeouts after about 64s. For details refer
- * to chapter 36 of the MPC5121e Reference Manual.
- */
-/* #define CONFIG_WATCHDOG */		/* enable watchdog */
-#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
-
- /*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-#ifdef CONFIG_CMD_KGDB
-# define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
-#else
-# define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
-#endif
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
-				 sizeof(CONFIG_SYS_PROMPT) + 16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS	32
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Linux initial memory map */
-
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE		32768
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CACHELINE_SHIFT	5
-#endif
-
-#define CONFIG_SYS_HID0_INIT	0x000000000
-#define CONFIG_SYS_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
-#define CONFIG_SYS_HID2		HID2_HBE
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_TIMESTAMP
-
-#define CONFIG_HOSTNAME		mecp512x
-#define CONFIG_BOOTFILE		"/tftpboot/mecp512x/uImage"
-#define CONFIG_ROOTPATH		"/tftpboot/mecp512x/target_root"
-
-#define CONFIG_LOADADDR		400000	/* def. location for tftp and bootm */
-
-#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs*/
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Welcome to MECP5123" \
-	"echo"
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"u-boot_addr_r=200000\0"					\
-	"kernel_addr_r=600000\0"					\
-	"fdt_addr_r=880000\0"						\
-	"ramdisk_addr_r=900000\0"					\
-	"u-boot_addr=FFF00000\0"					\
-	"kernel_addr=FFC40000\0"					\
-	"fdt_addr=FFEC0000\0"						\
-	"ramdisk_addr=FC040000\0"					\
-	"ramdiskfile=/tftpboot/mecp512x/uRamdisk\0"			\
-	"u-boot=/tftpboot/mecp512x/u-boot.bin\0"			\
-	"bootfile=/tftpboot/mecp512x/uImage\0"				\
-	"fdtfile=/tftpboot/mecp512x/mecp512x.dtb\0"			\
-	"rootpath=/tftpboot/mecp512x/target_root\n"	      		\
-	"netdev=eth0\0"							\
-	"consdev=ttyPSC0\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} "				\
-		"console=${consdev},${baudrate}\0"			\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
-		"tftp ${fdt_addr_r} ${fdtfile};"			\
-		"run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	"net_self=tftp ${kernel_addr_r} ${bootfile};"			\
-		"tftp ${ramdisk_addr_r} ${ramdiskfile};"		\
-		"tftp ${fdt_addr_r} ${fdtfile};"			\
-		"run ramargs addip addtty;"				\
-		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
-	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
-	"update=protect off ${u-boot_addr} +${filesize};"		\
-		"era ${u-boot_addr} +${filesize};"			\
-		"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"	\
-	"upd=run load update\0"						\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define OF_CPU			"PowerPC,5121@0"
-#define OF_SOC_COMPAT		"fsl,mpc5121-immr"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc@80000000/serial@11300"
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
deleted file mode 100644
index 75633f66ef..0000000000
--- a/include/configs/motionpro.h
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
- * (C) Copyright 2003-2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Based on Motion-PRO board config file by Robert McCullough, rob@promessinc.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-
-/* CPU and board */
-#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU */
-#define CONFIG_MOTIONPRO	1	/* ... on Promess Motion-PRO board */
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-#define	CONFIG_SYS_TEXT_BASE	0xfff00000
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_REGINFO
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#define CONFIG_NETCONSOLE	1	/* network console */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR		0x2
-#define CONFIG_PHY_TYPE		0x79c874
-#define CONFIG_RESET_PHY_R	1
-
-/*
- * Autobooting
- */
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_CMDLINE_EDITING		1	/* add command line history	*/
-
-/*
- * Default environment settings
- */
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=motionpro\0"						\
-	"netmask=255.255.255.0\0"					\
-	"ipaddr=192.168.1.106\0"					\
-	"serverip=192.168.1.100\0"					\
-	"gatewayip=192.168.1.100\0"					\
-	"console=ttyPSC0,115200\0"					\
-	"u-boot_addr=400000\0"						\
-	"kernel_addr=400000\0"						\
-	"fdt_addr=700000\0"						\
-	"ramdisk_addr=800000\0"						\
-	"multi_image_addr=800000\0"					\
-	"rootpath=/opt/eldk-4.2/ppc_6xx\0"				\
-	"u-boot=/tftpboot/motionpro/u-boot.bin\0"			\
-	"bootfile=/tftpboot/motionpro/uImage\0"				\
-	"fdt_file=/tftpboot/motionpro/motionpro.dtb\0"			\
-	"ramdisk_file=/tftpboot/motionpro/uRamdisk\0"			\
-	"multi_image_file=kernel+initrd+dtb.img\0"			\
-	"load=tftp ${u-boot_addr} ${u-boot}\0"				\
-	"update=prot off fff00000 +${filesize};"			\
-		"era fff00000 +${filesize}; "				\
-		"cp.b ${u-boot_addr} fff00000 ${filesize};"		\
-		"prot on fff00000 +${filesize}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"fat_args=setenv bootargs root=/dev/sda rw\0"			\
-	"mtdids=nor0=ff000000.flash\0"					\
-	"mtdparts=ff000000.flash:13m(fs),2m(kernel),384k(uboot)," 	\
-				"128k(env),128k(redund_env),"	  	\
-				"128k(dtb),128k(user_data)\0"		\
-	"addcons=setenv bootargs ${bootargs} console=${console}\0"	\
-	"addmtd=setenv bootargs ${bootargs} mtdparts=${mtdparts}\0"	\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
-		"${netmask}:${hostname}:${netdev}:off panic=1 "		\
-		"console=${console}\0"					\
-	"net_nfs=tftp ${kernel_addr} ${bootfile}; "			\
-		"tftp ${fdt_addr} ${fdt_file}; "			\
-		"run nfsargs addip addmtd; "				\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"net_self=tftp ${kernel_addr} ${bootfile}; "			\
-		"tftp ${fdt_addr} ${fdt_file}; "			\
-		"tftp ${ramdisk_addr} ${ramdisk_file}; "		\
-		"nfs ${ramdisk_addr} ${serverip}:${rootpath}/images/uRamdisk; "	\
-		"run ramargs addip addcons addmtd; "			\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
-	"fat_multi=run fat_args addip addmtd; fatload ide 0:1 "		\
-		"${multi_image_addr} ${multi_image_file}; "		\
-		"bootm ${multi_image_addr}\0"				\
-	""
-#define CONFIG_BOOTCOMMAND	"run fat_multi"
-
-/*
- * do board-specific init
- */
-#define CONFIG_BOARD_EARLY_INIT_R	1
-
-/*
- * Low level configuration
- */
-
-/*
- * Clock configuration: SYS_XTALIN = 33MHz
- */
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000
-
-/*
- * Set IPB speed to 100MHz
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
-
-/*
- * Memory map
- */
-/*
- * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000.
- * Setting MBAR to otherwise will cause system hang when using SmartDMA such
- * as network commands.
- */
-#define CONFIG_SYS_MBAR			0xf0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-
-/*
- * If building for running out of SDRAM, then MBAR has been set up beforehand
- * (e.g., by the BDI). Otherwise we must specify the default boot-up value of
- * MBAR, as given in the doccumentation.
- */
-#if CONFIG_SYS_TEXT_BASE == 0x00100000
-#define CONFIG_SYS_DEFAULT_MBAR	0xf0000000
-#else /* CONFIG_SYS_TEXT_BASE != 0x00100000 */
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-#define CONFIG_SYS_LOWBOOT		1
-#endif /* CONFIG_SYS_TEXT_BASE == 0x00100000 */
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* 384 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)	/* 1 MiB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* initial mem map for Linux */
-
-/*
- * Chip selects configuration
- */
-/* Boot Chipselect */
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x00045D00
-
-/* Flash memory addressing */
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_CS0_CFG		CONFIG_SYS_BOOTCS_CFG
-
-/* Dual Port SRAM -- Kollmorgen Drive memory addressing */
-#define CONFIG_SYS_CS1_START		0x50000000
-#define CONFIG_SYS_CS1_SIZE		0x10000
-#define CONFIG_SYS_CS1_CFG		0x05055800
-
-/* Local register access */
-#define CONFIG_SYS_CS2_START		0x50010000
-#define CONFIG_SYS_CS2_SIZE		0x10000
-#define CONFIG_SYS_CS2_CFG		0x05055800
-
-/* Anybus CompactCom Module memory addressing */
-#define CONFIG_SYS_CS3_START		0x50020000
-#define CONFIG_SYS_CS3_SIZE		0x10000
-#define CONFIG_SYS_CS3_CFG		0x05055800
-
-/* No burst and dead cycle = 2 for all CSs */
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x22222222
-
-/*
- * SDRAM configuration
- */
-/* 2 x MT48LC16M16A2BG-75 IT:D, CASL 3, 32 bit data bus */
-#define SDRAM_CONFIG1		0x62322900
-#define SDRAM_CONFIG2		0x88c70000
-#define SDRAM_CONTROL		0x504f0000
-#define SDRAM_MODE		0x00cd0000
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER	1
-#define CONFIG_SYS_FLASH_BASE		0xff000000
-#define CONFIG_SYS_FLASH_SIZE		0x01000000
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-#define CONFIG_FLASH_16BIT		/* Flash is 16-bit */
-
-/*
- * MTD configuration
- */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT		"nor0=motionpro-0"
-#define MTDPARTS_DEFAULT	"mtdparts=motionpro-0:"			  \
-					"13m(fs),2m(kernel),384k(uboot)," \
-					"128k(env),128k(redund_env),"	  \
-					"128k(dtb),-(user_data)"
-
-/*
- * IDE/ATA configuration
- */
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
-#define CONFIG_SYS_IDE_MAXBUS		1
-#define CONFIG_SYS_IDE_MAXDEVICE	1
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_ATA_DATA_OFFSET	0x0060
-#define CONFIG_SYS_ATA_REG_OFFSET	CONFIG_SYS_ATA_DATA_OFFSET
-#define CONFIG_SYS_ATA_STRIDE		4
-
-/*
- * RTC configuration
- */
-#define CONFIG_RTC_DS1337	1
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68
-
-/*
- * Status LED configuration
- */
-
-#define ENABLE_GPIO_OUT		0x00000024
-#define LED_ON			0x00000010
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-/* This has to be a multiple of the Flash sector size */
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SIZE		0x1000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-
-/* Configuration of redundant environment */
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-/*
- * Pin multiplexing configuration
- */
-
-/* PSC1: UART1
- * PSC2: GPIO (default)
- * PSC3: GPIO (default)
- * USB: 2xUART4/5
- * Ethernet: Ethernet 100Mbit with MD
- * Timer: CAN2/GPIO
- * PSC6/IRDA: GPIO (default)
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x1105a004
-
-/*
- * Motion-PRO's CPLD revision control register
- */
-#define CPLD_REV_REGISTER	(CONFIG_SYS_CS2_START + 0x06)
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory    */
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x03e00000	/* 1 ... 62 MiB in DRAM */
-#define CONFIG_SYS_ALT_MEMTEST
-
-#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default kernel load addr */
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-
-/* Not needed for MPC 5xxx U-Boot, but used by tools/updater */
-#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
-
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_SOC			"soc5200@f0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/mpc5121-common.h b/include/configs/mpc5121-common.h
deleted file mode 100644
index d252297e89..0000000000
--- a/include/configs/mpc5121-common.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * (C) Copyright 2010 DENX Software Engineering
- * Anatolij Gustschin <agust@denx.de>
- *
- * Common configuration options for MPC5121 based boards
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MPC5121_COMMON_H
-#define __MPC5121_COMMON_H
-
-/* Use SRAM for initial stack */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE /* Init RAM base */
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_SRAM_SIZE /* Size of area */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
-#define CONFIG_SYS_MEMTEST_END		0x00400000
-
-/*
- * Serial console
- */
-#define CONFIG_SYS_BAUDRATE_TABLE \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_CMDLINE_EDITING		1	/* command line history */
-
-#endif /* __MPC5121_COMMON_H */
diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h
deleted file mode 100644
index e11a0e628a..0000000000
--- a/include/configs/mpc5121ads.h
+++ /dev/null
@@ -1,581 +0,0 @@
-/*
- * (C) Copyright 2007-2009 DENX Software Engineering
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * MPC5121ADS board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MPC5121ADS 1
-
-/*
- * Memory map for the MPC5121ADS board:
- *
- * 0x0000_0000 - 0x0FFF_FFFF	DDR RAM (256 MB)
- * 0x3000_0000 - 0x3001_FFFF	SRAM (128 KB)
- * 0x8000_0000 - 0x803F_FFFF	IMMR (4 MB)
- * 0x8200_0000 - 0x8200_001F	CPLD (32 B)
- * 0x8400_0000 - 0x82FF_FFFF	PCI I/O space (16 MB)
- * 0xA000_0000 - 0xAFFF_FFFF	PCI memory space (256 MB)
- * 0xB000_0000 - 0xBFFF_FFFF	PCI memory mapped I/O space (256 MB)
- * 0xFC00_0000 - 0xFFFF_FFFF	NOR Boot FLASH (64 MB)
- */
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300		1	/* E300 Family */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
-
-/* video */
-#ifdef CONFIG_FSL_DIU_FB
-#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_IMMR + 0x2100)
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#endif
-
-/* CONFIG_PCI is defined at config time */
-
-#ifdef CONFIG_MPC5121ADS_REV2
-#define CONFIG_SYS_MPC512X_CLKIN	66000000	/* in Hz */
-#else
-#define CONFIG_SYS_MPC512X_CLKIN	33333333	/* in Hz */
-#endif
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_IMMR		0x80000000
-
-#define CONFIG_SYS_MEMTEST_START	0x00200000      /* memtest region */
-#define CONFIG_SYS_MEMTEST_END		0x00400000
-
-/*
- * DDR Setup - manually set all parameters as there's no SPD etc.
- */
-#ifdef CONFIG_MPC5121ADS_REV2
-#define CONFIG_SYS_DDR_SIZE		256		/* MB */
-#else
-#define CONFIG_SYS_DDR_SIZE		512		/* MB */
-#endif
-#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_MAX_RAM_SIZE		0x20000000
-
-#define CONFIG_SYS_IOCTRL_MUX_DDR	0x00000036
-
-/* DDR Controller Configuration
- *
- * SYS_CFG:
- *	[31:31]	MDDRC Soft Reset:	Diabled
- *	[30:30]	DRAM CKE pin:		Enabled
- *	[29:29]	DRAM CLK:		Enabled
- *	[28:28]	Command Mode:		Enabled (For initialization only)
- *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
- *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
- *	[20:19]	Read Test:		DON'T USE
- *	[18:18]	Self Refresh:		Enabled
- *	[17:17]	16bit Mode:		Disabled
- *	[16:13] Ready Delay:		2
- *	[12:12]	Half DQS Delay:		Disabled
- *	[11:11]	Quarter DQS Delay:	Disabled
- *	[10:08]	Write Delay:		2
- *	[07:07]	Early ODT:		Disabled
- *	[06:06]	On DIE Termination:	Disabled
- *	[05:05]	FIFO Overflow Clear:	DON'T USE here
- *	[04:04]	FIFO Underflow Clear:	DON'T USE here
- *	[03:03]	FIFO Overflow Pending:	DON'T USE here
- *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
- *	[01:01]	FIFO Overlfow Enabled:	Enabled
- *	[00:00]	FIFO Underflow Enabled:	Enabled
- * TIME_CFG0
- *	[31:16]	DRAM Refresh Time:	0 CSB clocks
- *	[15:8]	DRAM Command Time:	0 CSB clocks
- *	[07:00]	DRAM Precharge Time:	0 CSB clocks
- * TIME_CFG1
- *	[31:26]	DRAM tRFC:
- *	[25:21]	DRAM tWR1:
- *	[20:17]	DRAM tWRT1:
- *	[16:11]	DRAM tDRR:
- *	[10:05]	DRAM tRC:
- *	[04:00]	DRAM tRAS:
- * TIME_CFG2
- *	[31:28]	DRAM tRCD:
- *	[27:23]	DRAM tFAW:
- *	[22:19]	DRAM tRTW1:
- *	[18:15]	DRAM tCCD:
- *	[14:10] DRAM tRTP:
- *	[09:05]	DRAM tRP:
- *	[04:00] DRAM tRPA
- */
-#ifdef CONFIG_MPC5121ADS_REV2
-#define CONFIG_SYS_MDDRC_SYS_CFG	0xE8604A00
-#define CONFIG_SYS_MDDRC_TIME_CFG1	0x54EC1168
-#define CONFIG_SYS_MDDRC_TIME_CFG2	0x35210864
-#else
-#define CONFIG_SYS_MDDRC_SYS_CFG	0xEA804A00
-#define CONFIG_SYS_MDDRC_TIME_CFG1	0x68EC1168
-#define CONFIG_SYS_MDDRC_TIME_CFG2	0x34310864
-#endif
-#define CONFIG_SYS_MDDRC_TIME_CFG0	0x06183D2E
-
-#define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA	 	0xEA802B00
-#define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA	0x690e1189
-#define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA	0x35310864
-
-#define CONFIG_SYS_DDRCMD_NOP		0x01380000
-#define CONFIG_SYS_DDRCMD_PCHG_ALL	0x01100400
-#define CONFIG_SYS_DDRCMD_EM2		0x01020000
-#define CONFIG_SYS_DDRCMD_EM3		0x01030000
-#define CONFIG_SYS_DDRCMD_EN_DLL	0x01010000
-#define CONFIG_SYS_DDRCMD_RFSH		0x01080000
-
-#define DDRCMD_EMR_OCD(pr, ohm) ( \
-	(1 << 24)	   | /* MDDRC Command Request	*/ \
-	(1 << 16)	   | /* MODE Reg BA[2:0] 	*/ \
-	(0 << 12)	   | /* Outputs 0=Enabled	*/ \
-	(0 << 11)	   | /* RDQS 			*/ \
-	(1 << 10)	   | /* DQS# 			*/ \
-	(pr <<  7)	   | /* OCD prog 7=deflt,0=exit	*/ \
-		    /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \
-	((ohm & 0x2) <<  5)| /* Rtt1			*/ \
-	(0 <<  3)	   | /* additive posted CAS#	*/ \
-	((ohm & 0x1) <<  2)| /* Rtt0			*/ \
-	(0 <<  0)	   | /* Output Drive Strength	*/ \
-	(0 <<  0))	     /* DLL Enable 0=Normal	*/
-
-#define CONFIG_SYS_DDRCMD_OCD_DEFAULT	DDRCMD_EMR_OCD(7, 0)
-#define CONFIG_SYS_ELPIDA_OCD_EXIT	DDRCMD_EMR_OCD(0, 0)
-
-#define DDRCMD_MODE_REG(cas, wr) ( \
-	(1 << 24)    | /* MDDRC Command Request			*/ \
-	(0 << 16)    | /* MODE Reg BA[2:0] 			*/ \
-	((wr-1) << 9)| /* Write Recovery 			*/ \
-	(cas << 4)   | /* CAS 					*/ \
-	(0 << 3)     | /* Burst Type:0=Sequential,1=Interleaved	*/ \
-	(2 << 0))      /* 4 or 8 Burst Length:0x2=4 0x3=8	*/
-
-#define CONFIG_SYS_MICRON_INIT_DEV_OP	DDRCMD_MODE_REG(3, 3)
-#define CONFIG_SYS_ELPIDA_INIT_DEV_OP	DDRCMD_MODE_REG(4, 4)
-#define CONFIG_SYS_ELPIDA_RES_DLL	(DDRCMD_MODE_REG(4, 4) | (1 << 8))
-
-/* DDR Priority Manager Configuration */
-#define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
-#define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
-#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
-#define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
-#define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
-#define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
-#define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
-#define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
-#define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
-#define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
-#define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
-#define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
-#define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
-#define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111
-
-/*
- * NOR FLASH on the Local Bus
- */
-#undef CONFIG_BKUP_FLASH
-#define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
-#ifdef CONFIG_BKUP_FLASH
-#define CONFIG_SYS_FLASH_BASE		0xFF800000	/* start of FLASH   */
-#define CONFIG_SYS_FLASH_SIZE		0x00800000	/* max flash size in bytes */
-#else
-#define CONFIG_SYS_FLASH_BASE		0xFC000000	/* start of FLASH   */
-#define CONFIG_SYS_FLASH_SIZE		0x04000000	/* max flash size in bytes */
-#endif
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_SECT	256		/* max sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-
-/*
- * NAND FLASH
- * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
- */
-#define CONFIG_CMD_NAND					/* enable NAND support */
-#define CONFIG_JFFS2_NAND				/* with JFFS2 on it */
-#define CONFIG_NAND_MPC5121_NFC
-#define CONFIG_SYS_NAND_BASE            0x40000000
-
-#define CONFIG_SYS_MAX_NAND_DEVICE      2
-#define CONFIG_SYS_NAND_SELECT_DEVICE	/* driver supports mutipl. chips */
-
-/*
- * Configuration parameters for MPC5121 NAND driver
- */
-#define CONFIG_FSL_NFC_WIDTH 1
-#define CONFIG_FSL_NFC_WRITE_SIZE 2048
-#define CONFIG_FSL_NFC_SPARE_SIZE 64
-#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
-
-/*
- * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
- * window is 64KB
- */
-#define CONFIG_SYS_CPLD_BASE		0x82000000
-#define CONFIG_SYS_CPLD_SIZE		0x00010000	/* 64 KB */
-#define CONFIG_SYS_CS2_START		CONFIG_SYS_CPLD_BASE
-#define CONFIG_SYS_CS2_SIZE		CONFIG_SYS_CPLD_SIZE
-
-#define CONFIG_SYS_SRAM_BASE		0x30000000
-#define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
-
-#define CONFIG_SYS_CS0_CFG		0x05059310	/* ALE active low, data size 4bytes */
-#define CONFIG_SYS_CS2_CFG		0x05059010	/* ALE active low, data size 1byte */
-#define CONFIG_SYS_CS_ALETIMING	0x00000005	/* Use alternative CS timing for CS0 and CS2 */
-
-/* Use SRAM for initial stack */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE		/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_SRAM_SIZE		/* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE		/* Start of monitor */
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)		/* Reserve 512 kB for Mon */
-#ifdef	CONFIG_FSL_DIU_FB
-#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
-#else
-#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
-#endif
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX     1
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	3	/* console is on PSC3 */
-#define CONFIG_SYS_PSC3
-#if CONFIG_PSC_CONSOLE != 3
-#error CONFIG_PSC_CONSOLE must be 3
-#endif
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONSOLE_FIFO_TX_SIZE	FIFOC_PSC3_TX_SIZE
-#define CONSOLE_FIFO_TX_ADDR	FIFOC_PSC3_TX_ADDR
-#define CONSOLE_FIFO_RX_SIZE	FIFOC_PSC3_RX_SIZE
-#define CONSOLE_FIFO_RX_ADDR	FIFOC_PSC3_RX_ADDR
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-
-/*
- * Clocks in use
- */
-#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
-			 CLOCK_SCCR1_DDR_EN |				\
-			 CLOCK_SCCR1_FEC_EN |				\
-			 CLOCK_SCCR1_LPC_EN |				\
-			 CLOCK_SCCR1_NFC_EN |				\
-			 CLOCK_SCCR1_PATA_EN |				\
-			 CLOCK_SCCR1_PCI_EN |				\
-			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
-			 CLOCK_SCCR1_PSCFIFO_EN |			\
-			 CLOCK_SCCR1_TPR_EN)
-
-#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_DIU_EN |		\
-			 CLOCK_SCCR2_I2C_EN |		\
-			 CLOCK_SCCR2_MEM_EN |		\
-			 CLOCK_SCCR2_SPDIF_EN |		\
-			 CLOCK_SCCR2_USB1_EN |		\
-			 CLOCK_SCCR2_USB2_EN)
-
-/*
- * PCI
- */
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-/*
- * General PCI
- */
-#define CONFIG_SYS_PCI_MEM_BASE	0xA0000000
-#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI_MMIO_BASE	(CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE)
-#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
-#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI_IO_BASE		0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS		0x84000000
-#define CONFIG_SYS_PCI_IO_SIZE		0x01000000	/* 16M */
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-
-#endif
-
-/*
- * IIM - IC Identification Module
- */
-#undef CONFIG_FSL_IIM
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC512x_FEC	1
-#define CONFIG_PHY_ADDR		0x1
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_FEC_AN_TIMEOUT	1
-#define CONFIG_HAS_ETH0
-
-/*
- * Configure on-board RTC
- */
-#define CONFIG_RTC_M41T62			/* use M41T62 rtc via i2 */
-#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* at address 0x68		*/
-
-/*
- * USB  Support
- */
-
-#if defined(CONFIG_CMD_USB)
-#define CONFIG_USB_EHCI_FSL			/* On a FSL platform	*/
-#define CONFIG_EHCI_MMIO_BIG_ENDIAN		/* With big-endian regs	*/
-#define CONFIG_EHCI_DESC_BIG_ENDIAN
-#define CONFIG_EHCI_IS_TDI
-#endif
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-/* This has to be a multiple of the Flash sector size */
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SIZE		0x2000
-#ifdef CONFIG_BKUP_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x20000	/* one sector (256K) for env */
-#else
-#define CONFIG_ENV_SECT_SIZE	0x40000	/* one sector (256K) for env */
-#endif
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-#define CONFIG_CMD_REGINFO
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_PCI
-#endif
-
-/*
- * Dynamic MTD partition support
- */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT		"nor0=fc000000.flash,nand0=mpc5121.nand"
-
-/*
- * NOR flash layout:
- *
- * FC000000 - FEABFFFF 42.75 MiB	User Data
- * FEAC0000 - FFABFFFF  16 MiB		Root File System
- * FFAC0000 - FFEBFFFF   4 MiB		Linux Kernel
- * FFEC0000 - FFEFFFFF 256 KiB		Device Tree
- * FFF00000 - FFFFFFFF   1 MiB		U-Boot (up to 512 KiB) and 2 x * env
- *
- * NAND flash layout: one big partition
- */
-#define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:43776k(user),"	\
-						"16m(rootfs),"		\
-						"4m(kernel),"		\
-						"256k(dtb),"		\
-						"1m(u-boot);"		\
-					"mpc5121.nand:-(data)"
-
-#if defined(CONFIG_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB)
-#define CONFIG_SUPPORT_VFAT
-
-#endif /* defined(CONFIG_IDE) */
-
-/*
- * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
- * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
- * to 0xFFFF, watchdog timeouts after about 64s. For details refer
- * to chapter 36 of the MPC5121e Reference Manual.
- */
-/* #define CONFIG_WATCHDOG */		/* enable watchdog */
-#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
-
- /*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-#ifdef CONFIG_CMD_KGDB
-	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
-#else
-	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
-#endif
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Initial Memory map for Linux*/
-
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE		32768
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
-#endif
-
-#define CONFIG_SYS_HID0_INIT	0x000000000
-#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
-#define CONFIG_SYS_HID2	HID2_HBE
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_TIMESTAMP
-
-#define CONFIG_HOSTNAME		mpc5121ads
-#define CONFIG_BOOTFILE		"mpc5121ads/uImage"
-#define CONFIG_ROOTPATH		"/opt/eldk/ppc_6xx"
-
-#define CONFIG_LOADADDR		400000	/* default location for tftp and bootm */
-
-#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"u-boot_addr_r=200000\0"					\
-	"kernel_addr_r=600000\0"					\
-	"fdt_addr_r=880000\0"						\
-	"ramdisk_addr_r=900000\0"					\
-	"u-boot_addr=FFF00000\0"					\
-	"kernel_addr=FFAC0000\0"					\
-	"fdt_addr=FFEC0000\0"						\
-	"ramdisk_addr=FEAC0000\0"					\
-	"ramdiskfile=mpc5121ads/uRamdisk\0"				\
-	"u-boot=mpc5121ads/u-boot.bin\0"				\
-	"bootfile=mpc5121ads/uImage\0"					\
-	"fdtfile=mpc5121ads/mpc5121ads.dtb\0"				\
-	"rootpath=/opt/eldk/ppc_6xx\n"					\
-	"netdev=eth0\0"							\
-	"consdev=ttyPSC0\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} "				\
-		"console=${consdev},${baudrate}\0"			\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
-		"tftp ${fdt_addr_r} ${fdtfile};"			\
-		"run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	"net_self=tftp ${kernel_addr_r} ${bootfile};"			\
-		"tftp ${ramdisk_addr_r} ${ramdiskfile};"		\
-		"tftp ${fdt_addr_r} ${fdtfile};"			\
-		"run ramargs addip addtty;"				\
-		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
-	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
-	"update=protect off ${u-boot_addr} +${filesize};"		\
-		"era ${u-boot_addr} +${filesize};"			\
-		"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"	\
-	"upd=run load update\0"						\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES	1
-
-#define OF_CPU			"PowerPC,5121@0"
-#define OF_SOC_COMPAT		"fsl,mpc5121-immr"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc@80000000/serial@11300"
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-
-#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for IDE not supported	*/
-
-#define CONFIG_IDE_RESET		/* reset for IDE supported	*/
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-#define CONFIG_SYS_ATA_BASE_ADDR	get_pata_base()
-
-/* Offset for data I/O			RefMan MPC5121EE Table 28-10	*/
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x00A0)
-
-/* Offset for normal register accesses	*/
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers	RefMan MPC5121EE Table 28-23	*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x00D8)
-
-/* Interval between registers	*/
-#define CONFIG_SYS_ATA_STRIDE		4
-
-#define ATA_BASE_ADDR			get_pata_base()
-
-/*
- * Control register bit definitions
- */
-#define FSL_ATA_CTRL_FIFO_RST_B		0x80000000
-#define FSL_ATA_CTRL_ATA_RST_B		0x40000000
-#define FSL_ATA_CTRL_FIFO_TX_EN		0x20000000
-#define FSL_ATA_CTRL_FIFO_RCV_EN	0x10000000
-#define FSL_ATA_CTRL_DMA_PENDING	0x08000000
-#define FSL_ATA_CTRL_DMA_ULTRA		0x04000000
-#define FSL_ATA_CTRL_DMA_WRITE		0x02000000
-#define FSL_ATA_CTRL_IORDY_EN		0x01000000
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/munices.h b/include/configs/munices.h
deleted file mode 100644
index ad2d69e6a5..0000000000
--- a/include/configs/munices.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * (C) Copyright 2007
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
-#define CONFIG_MPC5200_DDR	1	/* (with DDR-SDRAM) */
-#define CONFIG_MUNICES		1	/* ... on MUNICes board */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFFF00000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33333333 /* ... running at 33.333333MHz */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_REGINFO
-
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
-#undef	CONFIG_BOOTARGS
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run net_nfs\" to load Kernel over TFTP and to mount root filesystem over NFS;" \
-	"echo"
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=$(serverip):$(rootpath)\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs $(bootargs) "				\
-		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
-		":$(hostname):$(netdev):off panic=5\0"			\
-	"flash_nfs=run nfsargs addip;"					\
-		"bootm $(kernel_addr)\0"				\
-	"flash_self=run ramargs addip;"					\
-		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
-	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
-	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"bootfile=/tftpboot/munices/u-boot.bin\0"			\
-	"update=tftpboot 200000 ${bootfile};protect off fff00000 fff3ffff;" \
-	"erase fff00000 fff3ffff; cp.b 200000 FFF00000 ${filesize}\0"	\
-	""
-#define CONFIG_BOOTCOMMAND	"run net_nfs"
-
-/*
- * IPB Bus clocking configuration.
- */
-#define  CONFIG_SYS_IPBSPEED_133		/* define for 133MHz speed */
-#if defined(CONFIG_SYS_IPBSPEED_133)
-/*
- * PCI Bus clocking configuration
- *
- * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CONFIG_SYS_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
- */
-#define CONFIG_SYS_PCISPEED_66		/* define for 66MHz speed */
-#else
-#undef CONFIG_SYS_PCISPEED_66			/* for 33MHz speed */
-#endif
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000 /* MBAR hast to be switched by other bootloader or debugger config  */
-
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE		0xFF000000
-#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_SIZE		0x01000000 /* 16 MByte */
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	 /* max num of flash banks (= chip selects) */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */
-
-/*
- * Chip selects configuration
- */
-/* Boot Chipselect */
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x00047800
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_OFFSET		0x40000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_SIZE		0x4000
-#define CONFIG_ENV_OFFSET_REDUND   (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET_REDUND)
-#define CONFIG_ENV_SIZE_REDUND     (CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OVERWRITE	1
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR		0x01
-#define CONFIG_MII		1
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x00058044 /* PSC1=UART, PSC2=UART ; Ether=100MBit with MD
-						no PCI */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
-
-#define CONFIG_CMDLINE_EDITING  1
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
-#define CONFIG_SYS_RESET_ADDRESS	0xff000000
-
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_SOC                  "soc5200@f0000000"
-#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/o2d.h b/include/configs/o2d.h
deleted file mode 100644
index 4b36af699a..0000000000
--- a/include/configs/o2d.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2012
- * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFC000000   boot low boot high (standard configuration)
- * 0x00100000   boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xfc000000	/* Standard: boot low */
-#endif
-
-/* Board specific flash config */
-#define CONFIG_SYS_FLASH_BASE		0xfc000000
-#define CONFIG_SYS_FLASH_SIZE		0x04000000      /* maximum 64MB */
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT	512
-
-/*
- * Include common defines for all ifm boards
- */
-#include "o2dnt-common.h"
-
-/*
- * GPIO configuration:
- * CS1 SDRAM activate + no CAN + no PCI
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x8000A004
-
-/* Other board specific configs */
-#define CONFIG_SYS_BOOTCS_CFG		0x00057d01
-#define CONFIG_SYS_RESET_ADDRESS	0xfc000000
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000      /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x07f00000	/* 1 - 127 MB in DRAM */
-
-#define CONFIG_BOARD_NAME		"o2d"
-#define CONFIG_BOARD_BOOTCMD		"run dhcp_boot"
-#define CONFIG_BOARD_MEM_LIMIT		__stringify(126)
-#define BOARD_POST_CRC32_END		__stringify(0x01000000)
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
-	CONFIG_IFM_DEFAULT_ENV_OLD					\
-	CONFIG_IFM_DEFAULT_ENV_NEW					\
-	"linbot=fc060000\0"						\
-	"lintop=fc15ffff\0"						\
-	"rambot=fc160000\0"						\
-	"ramtop=fc55ffff\0"						\
-	"jffbot=fc560000\0"						\
-	"jfftop=fcffffff\0"						\
-	"ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0"		\
-	"ubotop=fc03ffff\0"						\
-	"kernel_addr=0xfc060000\0"					\
-	"ramdisk_addr=0xfc160000\0"					\
-	"progCram=tftp ${fileaddr} ${cramfsname};"			\
-		"erase ${rambot} ${ramtop};"				\
-		"cp.b ${fileaddr} ${rambot} ${filesize}\0"		\
-	"flash_for_configs=22396\0"					\
-	"flash_mtd=run mtd_args addip addmem;"				\
-		"bootm ${kernel_addr}\0"				\
-	"mtd_args=setenv bootargs root=/dev/mtdblock3 "			\
-		"rw rootfstype=cramfs\0"				\
-	"master=mw f0000b00 0x8005A006;mw f0000b0c ${IOpin};"		\
-		"mw f0000b04 ${IOpin};mw f0000b10 0x20\0"		\
-	"dhcp_boot=run dhcpcmd;run flash_mtd\0"				\
-	"hostname=IFM_SENSOR\0"						\
-	"netretry=once\0"						\
-	"autoload=no\0"							\
-	"sensorType=O2D222AG\0"
diff --git a/include/configs/o2d300.h b/include/configs/o2d300.h
deleted file mode 100644
index a8222d9f97..0000000000
--- a/include/configs/o2d300.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * (C) Copyright 2012
- * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFC000000   boot low boot high (standard configuration)
- * 0x00100000   boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xfc000000	/* Standard: boot low */
-#endif
-
-/* Board specific flash config */
-#define CONFIG_SYS_FLASH_BASE		0xfc000000
-#define CONFIG_SYS_FLASH_SIZE		0x04000000      /* maximum 64MB */
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT	512
-
-/*
- * Include common defines for all ifm boards
- */
-#include "o2dnt-common.h"
-
-/*
- * GPIO configuration:
- * CS1 SDRAM activate + no CAN + no PCI
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG      0x8000A004
-
-/* Other board specific configs */
-#define CONFIG_SYS_BOOTCS_CFG		0x00057d01
-#define CONFIG_SYS_RESET_ADDRESS	0xfc000000
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000      /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x07f00000	/* 1 - 127 MB in DRAM */
-
-/* Use redundant environment */
-#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
-
-#define CONFIG_BOARD_NAME		"o2d300"
-#define CONFIG_BOARD_BOOTCMD		"run dhcp_boot"
-#define CONFIG_BOARD_MEM_LIMIT		__stringify(126)
-#define BOARD_POST_CRC32_END		__stringify(0x02000000)
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
-	CONFIG_IFM_DEFAULT_ENV_OLD					\
-	CONFIG_IFM_DEFAULT_ENV_NEW					\
-	"autoload=no\0"							\
-	"dhcp_boot=run dhcpcmd;run flash_mtd\0"				\
-	"flash_mtd=run mtd_args addip addmem;"				\
-		"bootm ${kernel_addr}\0"				\
-	"mtd_args=setenv bootargs root=/dev/mtdblock4 "			\
-		"rw rootfstype=cramfs\0"				\
-	"linbot=fc080000\0"						\
-	"lintop=fc17ffff\0"						\
-	"rambot=fc180000\0"						\
-	"ramtop=fc57ffff\0"						\
-	"jffbot=fc580000\0"						\
-	"jfftop=fd39ffff\0"						\
-	"ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0"		\
-	"ubotop=fc03ffff\0"						\
-	"halname="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME"_halcon\0"	\
-	"halbot=fd3a0000\0"						\
-	"haltop=fdf9ffff\0"						\
-	"progHal=tftp 200000 ${halname};erase ${halbot} ${haltop};"	\
-		"cp.b ${fileaddr} ${halbot} ${filesize}\0"		\
-	"kernel_addr=0xfc060000\0"					\
-	"ramdisk_addr=0xfc160000\0"					\
-	"master=mw f0000b00 0x8005A006;mw f0000b0c ${IOpin};"		\
-		"mw f0000b04 ${IOpin};mw f0000b10 0x20\0"		\
-	"netretry=once\0"						\
-	"protcmd=protect on ${linbot} ${lintop};"			\
-		"protect on ${rambot} ${ramtop}\0"			\
-	"o2derror=def_env\0"						\
-	"sensorType=O2D300AA\0"
diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h
deleted file mode 100644
index 1b4200bcbf..0000000000
--- a/include/configs/o2dnt-common.h
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- *  Common configuration options for ifm camera boards
- *
- * (C) Copyright 2005
- * Sebastien Cazaux, ifm electronic gmbh
- *
- * (C) Copyright 2012
- * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __O2D_CONFIG_H
-#define __O2D_CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_MPC5200
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* running at 33.000000MHz */
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-/* log base 2 of the above value */
-#define CONFIG_SYS_CACHELINE_SHIFT	5
-#endif
-
-/*
-#define CONFIG_POST	(CONFIG_SYS_POST_MEMORY | \
-			 CONFIG_SYS_POST_I2C)
-*/
-
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define MPC5XXX_SRAM_POST_SIZE	(MPC5XXX_SRAM_SIZE - 4)
-#endif
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	5	/* console is on PSC5 */
-#define CONFIG_SYS_BAUDRATE_TABLE \
-	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-
-#define CONFIG_SYS_XLB_PIPELINING	1
-
-/* Partitions */
-
-#define CONFIG_TIMESTAMP	/* Print image info with timestamp */
-
-#define CONFIG_SYS_ALT_MEMTEST	/* Much more complex memory test */
-
-/*
- * Supported commands
- */
-#ifdef CONFIG_PCI
-#define CONFIG_CMD_PCI
-#endif
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) || (CONFIG_SYS_TEXT_BASE == 0xFF000000)
-/* Boot low with 16 or 32 MB Flash */
-#define CONFIG_SYS_LOWBOOT	1
-#elif (CONFIG_SYS_TEXT_BASE != 0x00100000)
-#error "CONFIG_SYS_TEXT_BASE value is invalid"
-#endif
-
-
-#define CONFIG_PREBOOT	"run master"
-
-#undef	CONFIG_BOOTARGS
-
-#if !defined(CONSOLE_DEV)
-#define CONSOLE_DEV	"ttyPSC1"
-#endif
-
-/*
- * Default environment for booting old and new kernel versions
- */
-#define CONFIG_IFM_DEFAULT_ENV_OLD					\
-	"flash_self_old=run ramargs addip addmem;"			\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"flash_nfs_old=run nfsargs addip addmem;"			\
-		"bootm ${kernel_addr}\0"				\
-	"net_nfs_old=tftp ${kernel_addr_r} ${bootfile};"		\
-		"run nfsargs addip addmem;"				\
-		"bootm ${kernel_addr_r}\0"
-
-#define CONFIG_IFM_DEFAULT_ENV_NEW					\
-	"fdt_addr_r=900000\0"						\
-	"fdt_file="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME".dtb\0"	\
-	"flash_self=run ramargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
-	"flash_nfs=run nfsargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
-		"tftp ${fdt_addr_r} ${fdt_file}; "			\
-		"run nfsargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-
-#define	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
-	"IOpin=0x64\0"							\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addmem=setenv bootargs ${bootargs} ${memlimit}\0"		\
-	"addmisc=sete bootargs ${bootargs} ${miscargs}\0"		\
-	"addtty=sete bootargs ${bootargs} console="			\
-		CONSOLE_DEV ",${baudrate}\0"			\
-	"bootfile="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0"	\
-	"kernel_addr_r=600000\0"					\
-	"initrd_high=0x03e00000\0"					\
-	"memlimit=mem="CONFIG_BOARD_MEM_LIMIT"M\0"			\
-	"memtest=mtest 0x00100000 "__stringify(CONFIG_SYS_MEMTEST_END)" 0 1\0" \
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"linuxname="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0"\
-	"progLinux=tftp 200000 ${linuxname};erase ${linbot} ${lintop};" \
-		"cp.b ${fileaddr} ${linbot} ${filesize}\0"		\
-	"ramname="CONFIG_BOARD_NAME"/uRamdisk_"CONFIG_BOARD_NAME"_act\0"\
-	"progRam=tftp 200000 ${ramname};erase ${rambot} ${ramtop};"	\
-		"cp.b ${fileaddr} ${rambot} ${filesize}\0"		\
-	"jffname="CONFIG_BOARD_NAME"/uJFFS2_"CONFIG_BOARD_NAME"_act\0"	\
-	"progJff=tftp 200000 ${jffname};erase ${jffbot} ${jfftop};"	\
-		"cp.b ${fileaddr} ${jffbot} ${filesize}\0"		\
-	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"uboname=" CONFIG_BOARD_NAME					\
-		"/u-boot.bin_" CONFIG_BOARD_NAME "_act\0"		\
-	"progubo=tftp 200000 ${uboname};"				\
-		"protect off ${ubobot} ${ubotop};"			\
-		"erase ${ubobot} ${ubotop};"				\
-		"cp.b ${fileaddr} ${ubobot} ${filesize}\0"		\
-	"unlock=yes\0"							\
-	"post=echo !!! "CONFIG_BOARD_NAME" POWER ON SELF TEST !!!;"	\
-		"setenv bootdelay 1;"					\
-		"crc32 "__stringify(CONFIG_SYS_TEXT_BASE)" "		\
-			BOARD_POST_CRC32_END";"				\
-		"setenv bootcmd "CONFIG_BOARD_BOOTCMD";saveenv;reset\0"
-
-#define CONFIG_BOOTCOMMAND	"run post"
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-
-#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
-/*
- * PCI Bus clocking configuration
- *
- * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
- * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
- */
-#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
-#endif
-
-/*
- * There is no write delay with FRAM, write operations are performed at bus
- * speed. Thus, no status polling or write delay is needed.
- */
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_CFI		1
-#define CONFIG_FLASH_CFI_DRIVER		1
-#define CONFIG_FLASH_16BIT
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Write Timeout (in ms) */
-/* Timeout for Flash Clear Lock Bits (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000
-/* "Real" (hardware) sectors protection */
-#define CONFIG_SYS_FLASH_PROTECTION
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_SIZE		0x20000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_OVERWRITE	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
-#else
-/* End of used area in DPRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
-#endif
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(192 << 10) /* 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10) /* 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)   /* Initial map for Linux */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT		1
-#endif
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR			0x00
-#define CONFIG_RESET_PHY_R
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPIO_DATADIR		0x00000064 /* PSC1_2, PSC2_1,2 output */
-#define CONFIG_SYS_GPIO_OPENDRAIN	0x00000000 /* No open drain */
-#define CONFIG_SYS_GPIO_DATAVALUE	0x00000000 /* PSC1_1 to 1, rest to 0 */
-#define CONFIG_SYS_GPIO_ENABLE		0x00000064 /* PSC1_2, PSC2_1,2 enable */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_CMDLINE_EDITING
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					 sizeof(CONFIG_SYS_PROMPT) + 16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS		16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR		0x100000
-
-/* decrementer freq: 1 ms ticks */
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_BOARD_EARLY_INIT_R
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE		0x33333333
-
-/*
- * DT support
- */
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_SOC			"soc5200@f0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-
-#endif /* __O2D_CONFIG_H */
diff --git a/include/configs/o2dnt2.h b/include/configs/o2dnt2.h
deleted file mode 100644
index 00a8d9618d..0000000000
--- a/include/configs/o2dnt2.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * (C) Copyright 2012
- * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFC000000   boot low boot high (standard configuration)
- * 0x00100000   boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xfc000000	/* Standard: boot low */
-#endif
-
-/* Board specific flash config */
-#define CONFIG_SYS_FLASH_BASE		0xfc000000
-#define CONFIG_SYS_FLASH_SIZE		0x04000000      /* maximum 64MB */
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT	512
-
-/*
- * Include common defines for all ifm boards
- */
-#include "o2dnt-common.h"
-
-/*
- * GPIO configuration:
- * CS1 SDRAM activate + no CAN + no PCI
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x8000A004
-
-/* Other board specific configs */
-#define CONFIG_SYS_BOOTCS_CFG		0x00057d01
-#define CONFIG_SYS_RESET_ADDRESS	0xfc000000
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000      /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x07f00000	/* 1 - 127 MB in DRAM */
-
-#define CONFIG_BOARD_NAME		"o2dnt2"
-#define CONFIG_BOARD_BOOTCMD		"run flash_self"
-#define CONFIG_BOARD_MEM_LIMIT		__stringify(126)
-#define BOARD_POST_CRC32_END		__stringify(0x01000000)
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
-	CONFIG_IFM_DEFAULT_ENV_OLD					\
-	CONFIG_IFM_DEFAULT_ENV_NEW					\
-	"linbot=fc060000\0"						\
-	"lintop=fc15ffff\0"						\
-	"rambot=fc160000\0"						\
-	"ramtop=fc55ffff\0"						\
-	"jffbot=fc560000\0"						\
-	"jfftop=fce5ffff\0"						\
-	"ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0"		\
-	"ubotop=fc03ffff\0"						\
-	"calname="CONFIG_BOARD_NAME"/uCal_"CONFIG_BOARD_NAME"_act\0"	\
-	"calbot=fce60000\0"						\
-	"caltop=fcffffff\0"						\
-	"progCal=tftp 200000 ${calname};erase ${calbot} ${caltop};"	\
-		"cp.b ${fileaddr} ${calbot} ${filesize}\0"		\
-	"kernel_addr=0xfc060000\0"					\
-	"ramdisk_addr=0xfc160000\0"					\
-	"master=mw f0000b00 0x8005A006;mw f0000b0c ${IOpin};"		\
-		"mw f0000b04 ${IOpin};mw f0000b10 0x20\0"
diff --git a/include/configs/o2i.h b/include/configs/o2i.h
deleted file mode 100644
index c0fcedaf10..0000000000
--- a/include/configs/o2i.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * (C) Copyright 2012
- * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFF000000   boot low boot high (standard configuration)
- * 0x00100000   boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xff000000	/* Standard: boot low */
-#endif
-
-/* Board specific flash config */
-#define CONFIG_SYS_FLASH_BASE		0xff000000
-#define CONFIG_SYS_FLASH_SIZE		0x01000000      /* maximum 16MB */
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT	128
-
-/*
- * Include common defines for all ifm boards
- */
-#include "o2dnt-common.h"
-
-/* GPIO configuration */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x00002006	/* no CAN */
-
-/* Other board specific configs */
-#define CONFIG_SYS_BOOTCS_CFG		0x00087801
-#define CONFIG_SYS_RESET_ADDRESS	0xff000000
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000      /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x03f00000	/* 1 - 63 MB in DRAM  */
-
-#define CONFIG_BOARD_NAME		"o2i"
-#define CONFIG_BOARD_BOOTCMD		"run dhcp_boot"
-#define CONFIG_BOARD_MEM_LIMIT		__stringify(62)
-#define BOARD_POST_CRC32_END		__stringify(0x01000000)
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
-	CONFIG_IFM_DEFAULT_ENV_OLD					\
-	CONFIG_IFM_DEFAULT_ENV_NEW					\
-	"linbot=ff060000\0"						\
-	"lintop=ff15ffff\0"						\
-	"rambot=ff160000\0"						\
-	"ramtop=ff55ffff\0"						\
-	"jffbot=ff560000\0"						\
-	"jfftop=ffebffff\0"						\
-	"kernel_addr=0xff060000\0"					\
-	"ramdisk_addr=0xff160000\0"					\
-	"ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0"		\
-	"ubotop=ff03ffff\0"						\
-	"autoload=no\0"							\
-	"dhcp_boot=run dhcpcmd; run flash_mtd\0"			\
-	"hostname=IFM_SENSOR\0"						\
-	"flash_mtd=run mtd_args addip addmem;bootm ${kernel_addr}\0"	\
-	"mtd_args=setenv bootargs root=/dev/mtdblock3 "			\
-		"rw rootfstype=cramfs\0"				\
-	"sensorType=O2I100AA\0"						\
-	"netretry=once\0"						\
-	"master=mw f0000b00 0x00052006;mw f0000b0c ${IOpin};"		\
-		"mw f0000b04 ${IOpin};mw f0000b10 0x20\0"
diff --git a/include/configs/o2mnt.h b/include/configs/o2mnt.h
deleted file mode 100644
index eb63cb0c85..0000000000
--- a/include/configs/o2mnt.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2012
- * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFF000000   boot low boot high (standard configuration)
- * 0x00100000   boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xff000000	/* Standard: boot low */
-#endif
-
-/* Board specific flash config */
-#define CONFIG_SYS_FLASH_BASE		0xff000000
-#define CONFIG_SYS_FLASH_SIZE		0x01000000      /* maximum 16MB */
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT	128
-
-/*
- * Include common defines for all ifm boards
- */
-#include "o2dnt-common.h"
-
-/* GPIO configuration */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x00002004	/* no CAN */
-
-/* Other board specific configs */
-#define CONFIG_NETCONSOLE
-
-#define CONFIG_SYS_BOOTCS_CFG		0x00087801
-#define CONFIG_SYS_RESET_ADDRESS	0xff000000
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000      /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x03f00000	/* 1 - 63 MB in DRAM  */
-
-#define CONFIG_BOARD_NAME		"o2mnt"
-#define CONFIG_BOARD_BOOTCMD		"${newcmd}"
-#define CONFIG_BOARD_MEM_LIMIT		__stringify(62)
-#define BOARD_POST_CRC32_END		__stringify(0x01000000)
-
-#ifndef CONFIG_IFM_SENSOR_TYPE
-#define CONFIG_IFM_SENSOR_TYPE		"O2M110"
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
-	CONFIG_IFM_DEFAULT_ENV_OLD					\
-	CONFIG_IFM_DEFAULT_ENV_NEW					\
-	"linbot=ff060000\0"						\
-	"lintop=ff25ffff\0"						\
-	"rambot=ff260000\0"						\
-	"ramtop=ffc5ffff\0"						\
-	"jffbot=ffc60000\0"						\
-	"jfftop=ffffffff\0"						\
-	"ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0"		\
-	"ubotop=ff03ffff\0"						\
-	"kernel_addr=0xff060000\0"					\
-	"ramdisk_addr=0xff260000\0"					\
-	"newcmd=run scrprot;run flash_ext2\0"				\
-	"scrprot=protect on ${linbot} ${lintop};protect on ${rambot} "	\
-		"${ramtop}\0"						\
-	"flash_ext2=run ext2args addip addmem;bootm ${kernel_addr}\0"	\
-	"ext2args=setenv bootargs root=/dev/mtdblock3 ro "		\
-		"rootfstype=ext2\0"					\
-	"pwm=mw f0000674 0x10006;mw f0000678 0x30000;"			\
-		"mw f0000678 0x30001;mw f0000670 0x3\0"			\
-	"master=mw f0000b00 0x00052006;mw f0000b0c $(IOpin);"		\
-		"mw f0000b04 $(IOpin);mw f0000b10 0x24;run pwm\0"	\
-	"sensortyp="CONFIG_IFM_SENSOR_TYPE"\0"				\
-	"srelease=0.00\0"
diff --git a/include/configs/o3dnt.h b/include/configs/o3dnt.h
deleted file mode 100644
index f0fcedaffc..0000000000
--- a/include/configs/o3dnt.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * (C) Copyright 2012
- * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFC000000   boot low boot high (standard configuration)
- * 0x00100000   boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xfc000000	/* Standard: boot low */
-#endif
-
-/* Board specific flash config */
-#define CONFIG_SYS_FLASH_BASE		0xfc000000
-#define CONFIG_SYS_FLASH_SIZE		0x04000000      /* maximum 64MB */
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT	512
-
-/*
- * Include common defines for all ifm boards
- */
-#include "o2dnt-common.h"
-
-/* Additional commands */
-#define CONFIG_CMD_REGINFO
-
-/*
- * GPIO configuration:
- * no CAN + no PCI
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x0000A000
-
-/* Other board specific configs */
-#define CONFIG_SYS_BOOTCS_CFG		0x00057d01
-#define CONFIG_SYS_RESET_ADDRESS	0xfc000000
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000      /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x03f00000	/* 1 - 63 MB in DRAM */
-
-#define CONFIG_BOARD_NAME		"o3dnt"
-#define CONFIG_BOARD_BOOTCMD		"run flash_self"
-#define CONFIG_BOARD_MEM_LIMIT		__stringify(62)
-#define BOARD_POST_CRC32_END		__stringify(0x01000000)
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
-	CONFIG_IFM_DEFAULT_ENV_OLD					\
-	CONFIG_IFM_DEFAULT_ENV_NEW					\
-	"linbot=fc060000\0"						\
-	"lintop=fc15ffff\0"						\
-	"rambot=fc160000\0"						\
-	"ramtop=fc55ffff\0"						\
-	"jffbot=fc560000\0"						\
-	"jfftop=fce5ffff\0"						\
-	"ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0"		\
-	"ubotop=fc03ffff\0"						\
-	"calname="CONFIG_BOARD_NAME"/uCal_"CONFIG_BOARD_NAME"_act\0"	\
-	"calbot=fce60000\0"						\
-	"caltop=fcffffff\0"						\
-	"progCal=tftp 200000 ${calname};erase ${calbot} ${caltop};"	\
-		"cp.b ${fileaddr} ${calbot} ${filesize}\0"		\
-	"kernel_addr=0xfc060000\0"					\
-	"ramdisk_addr=0xfc160000\0"					\
-	"master=mw f0000b00 0x0005A006;mw f0000b0c ${IOpin};"		\
-		"mw f0000b04 ${IOpin};mw f0000b10 0x20\0"
diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h
deleted file mode 100644
index 6da17be11c..0000000000
--- a/include/configs/pcm030.h
+++ /dev/null
@@ -1,378 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2006
- * Eric Schumann, Phytec Messatechnik GmbH
- *
- * (C) Copyright 2009
- * Jon Smirl <jonsmirl@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_BOARDINFO	 "phyCORE-MPC5200B-tiny"
-
-/*-----------------------------------------------------------------------------
-High Level Configuration Options
-(easy to change)
------------------------------------------------------------------------------*/
-#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
-#define CONFIG_MPC5200_DDR	1	/* (with DDR-SDRAM) */
-#define CONFIG_PHYCORE_MPC5200B_TINY 1	/* phyCORE-MPC5200B -> */
-					/* FEC configuration and IDE */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFFF00000	boot high (standard configuration)
- * 0xFF000000	boot low
- * 0x00100000	boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFFF00000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
-
-/*-----------------------------------------------------------------------------
-Serial console configuration
------------------------------------------------------------------------------*/
-#define CONFIG_PSC_CONSOLE	3	/* console is on PSC3 -> */
-					/*define gps port conf. */
-					/* register later on to */
-					/*enable UART function! */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PCI
-
-#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)	/* Boot low */
-#define CONFIG_SYS_LOWBOOT 1
-#endif
-/* RAMBOOT will be defined automatically in memory section */
-
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT 		"nor0=physmap-flash.0"
-#define MTDPARTS_DEFAULT   	"mtdparts=physmap-flash.0:256k(ubootl)," \
-	"1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
-
-#undef	CONFIG_BOOTARGS
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\
-		"mount root filesystem over NFS;" \
-	"echo"
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"uimage=uImage-pcm030\0"					\
-	"oftree=oftree-pcm030.dtb\0"					\
-	"jffs2=root-pcm030.jffs2\0" 					\
-	"uboot=u-boot-pcm030.bin\0"					\
-	"bargs_base=setenv bootargs console=ttyPSC0,$(baudrate)"	\
-		" $(mtdparts) rw\0" 					\
-	"bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2"	\
-		" rootfstype=jffs2\0" 					\
-	"bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs"		\
-		" ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::"	\
-		"$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
-	"bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage);" \
-		" tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0"	\
-	"bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - "	\
-		"0xfff40000\0" 						\
-		" cp.b 0x400000 0xff040000 $(filesize)\0" 		\
-	"prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; " \
-		"cp.b 0x400000 0xff200000 $(filesize)\0" 		\
-	"prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff;" \
-		" cp.b 0x400000 0xfff40000 $(filesize)\0" 		\
-	"update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff;" \
-		" cp.b 0x400000 0xFFF00000 $(filesize)\0"		\
-	"unlock=yes\0"							\
-	""
-
-#define CONFIG_BOOTCOMMAND		"run bcmd_flash"
-
-/*--------------------------------------------------------------------------
-IPB Bus clocking configuration.
- ---------------------------------------------------------------------------*/
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK	/* define for 133MHz speed */
-
-/*-------------------------------------------------------------------------
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- * -----------------------------------------------------------------------*/
-#define CONFIG_PCI_SCAN_SHOW		1
-#define CONFIG_PCI_MEM_BUS		0x40000000
-#define CONFIG_PCI_MEM_PHYS		CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE		0x10000000
-#define CONFIG_PCI_IO_BUS		0x50000000
-#define CONFIG_PCI_IO_PHYS		CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE		0x01000000
-#define CONFIG_SYS_XLB_PIPELINING	1
-
-/*---------------------------------------------------------------------------
- Flash configuration
----------------------------------------------------------------------------*/
-
-#define CONFIG_SYS_FLASH_BASE		0xff000000
-#define CONFIG_SYS_FLASH_SIZE		0x01000000
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_MAX_FLASH_SECT 260 /* max num of sects on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
-						/* (= chip selects) */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-/*
- * Use also hardware protection. This seems required, as the BDI uses
- * hardware protection. Without this, U-Boot can't work with this sectors,
- * as its protection is software only by default
- */
-#define CONFIG_SYS_FLASH_PROTECTION	1
-
-/*---------------------------------------------------------------------------
- Environment settings
----------------------------------------------------------------------------*/
-
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_OFFSET	0x00	/* environment starts at the */
-					/*beginning of the EEPROM */
-#define CONFIG_ENV_SIZE		2048
-
-#define CONFIG_ENV_OVERWRITE	1
-
-/*-----------------------------------------------------------------------------
-  Memory map
------------------------------------------------------------------------------*/
-#define CONFIG_SYS_MBAR	0xF0000000	/* MBAR has to be switched by other */
-					/* bootloader or debugger config */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR		0x80000000
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used */
-								/* area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-						GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#	define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------------
- Ethernet configuration
------------------------------------------------------------------------------*/
-#define CONFIG_MPC5xxx_FEC		1
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR			0x01
-
-/*---------------------------------------------------------------------------
- GPIO configuration
- ---------------------------------------------------------------------------*/
-
-/* GPIO port configuration
- *
- * Pin mapping:
- *
- * [29:31] = 01x
- * PSC1_0 -> AC97 SDATA out
- * PSC1_1 -> AC97 SDTA in
- * PSC1_2 -> AC97 SYNC out
- * PSC1_3 -> AC97 bitclock out
- * PSC1_4 -> AC97 reset out
- *
- * [25:27] = 001
- * PSC2_0 -> CAN 1 Tx out
- * PSC2_1 -> CAN 1 Rx in
- * PSC2_2 -> CAN 2 Tx out
- * PSC2_3 -> CAN 2 Rx in
- * PSC2_4 -> GPIO (claimed for ATA reset, active low)
- *
- *
- * [20:23] = 1100
- * PSC3_0 -> UART Tx out
- * PSC3_1 -> UART Rx in
- * PSC3_2 -> UART RTS (in/out FIXME)
- * PSC3_3 -> UART CTS (in/out FIXME)
- * PSC3_4 -> LocalPlus Bus CS6 \
- * PSC3_5 -> LocalPlus Bus CS7 / --> see [4] and [5]
- * PSC3_6 -> dedicated SPI MOSI out (master case)
- * PSC3_7 -> dedicated SPI MISO in (master case)
- * PSC3_8 -> dedicated SPI SS out (master case)
- * PSC3_9 -> dedicated SPI CLK out (master case)
- *
- * [18:19] = 01
- * USB_0 -> USB OE out
- * USB_1 -> USB Tx- out
- * USB_2 -> USB Tx+ out
- * USB_3 -> USB RxD (in/out FIXME)
- * USB_4 -> USB Rx+ in
- * USB_5 -> USB Rx- in
- * USB_6 -> USB PortPower out
- * USB_7 -> USB speed out
- * USB_8 -> USB suspend (in/out FIXME)
- * USB_9 -> USB overcurrent in
- *
- * [17] = 0
- * USB differential mode
- *
- * [16] = 0
- * PCI enabled
- *
- * [12:15] = 0101
- * ETH_0 -> ETH Txen
- * ETH_1 -> ETH TxD0
- * ETH_2 -> ETH TxD1
- * ETH_3 -> ETH TxD2
- * ETH_4 -> ETH TxD3
- * ETH_5 -> ETH Txerr
- * ETH_6 -> ETH MDC
- * ETH_7 -> ETH MDIO
- * ETH_8 -> ETH RxDv
- * ETH_9 -> ETH RxCLK
- * ETH_10 -> ETH Collision
- * ETH_11 -> ETH TxD
- * ETH_12 -> ETH RxD0
- * ETH_13 -> ETH RxD1
- * ETH_14 -> ETH RxD2
- * ETH_15 -> ETH RxD3
- * ETH_16 -> ETH Rxerr
- * ETH_17 -> ETH CRS
- *
- * [9:11] = 101
- * PSC6_0 -> UART RxD in
- * PSC6_1 -> UART CTS (in/out FIXME)
- * PSC6_2 -> UART TxD out
- * PSC6_3 -> UART RTS (in/out FIXME)
- *
- * [2:3/6:7] = 00/11
- * TMR_0 -> ATA_CS0 out
- * TMR_1 -> ATA_CS1 out
- * TMR_2 -> GPIO
- * TMR_3 -> GPIO
- * TMR_4 -> GPIO
- * TMR_5 -> GPIO
- * TMR_6 -> GPIO
- * TMR_7 -> GPIO
- * I2C_0 -> I2C 1 Clock out
- * I2C_1 -> I2C 1 IO in/out
- * I2C_2 -> I2C 2 Clock out
- * I2C_3 -> I2C 2 IO in/out
- *
- * [4] = 1
- * PSC3_5 is used as CS7
- *
- * [5] = 1
- * PSC3_4 is used as CS6
- *
- * [1] = 0
- * gpio_wkup_7 is GPIO
- *
- * [0] = 0
- * gpio_wkup_6 is GPIO
- *
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x0f551c12
-
-/*-----------------------------------------------------------------------------
- Miscellaneous configurable options
--------------------------------------------------------------------------------*/
-#define CONFIG_SYS_LONGHELP	/* undef to save memory */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-							/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
-
-/*-----------------------------------------------------------------------------
- Various low-level settings
------------------------------------------------------------------------------*/
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-/* no burst access on the LPB */
-#define CONFIG_SYS_CS_BURST		0x00000000
-/* one deadcycle for the 33MHz statemachine */
-#define CONFIG_SYS_CS_DEADCYCLE		0x33333331
-/* one additional waitstate for the 33MHz statemachine */
-#define CONFIG_SYS_BOOTCS_CFG		0x0001dd00
-#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_RESET_ADDRESS 	0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK		0x0001BBBB
-#define CONFIG_USB_CONFIG		0x00001000
-
-/*---------------------------------------------------------------------------
- IDE/ATA stuff Supports IDE harddisk
-----------------------------------------------------------------------------*/
-
-#undef  CONFIG_IDE_8xx_PCCARD	/* Use IDE with PC Card Adapter */
-#undef	CONFIG_IDE_8xx_DIRECT	/* Direct IDE not supported */
-#undef	CONFIG_IDE_LED		/* LED for ide not supported */
-#define CONFIG_SYS_ATA_CS_ON_TIMER01
-#define	CONFIG_IDE_RESET 1	/* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
-/* Offset for data I/O			*/
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
-/* Offset for normal register accesses	*/
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
-/* Offset for alternate registers	*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE		4
-#define CONFIG_ATAPI			1
-
-/* USB */
-#define CONFIG_USB_OHCI
-
-/* pass open firmware flat tree */
-#define OF_CPU				"PowerPC,5200@0"
-#define OF_TBCLK			CONFIG_SYS_MPC5XXX_CLKIN
-#define OF_SOC				"soc5200@f0000000"
-#define OF_STDOUT_PATH			"/soc5200@f0000000/serial@2400"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h
deleted file mode 100644
index 676d55f5e8..0000000000
--- a/include/configs/pdm360ng.h
+++ /dev/null
@@ -1,420 +0,0 @@
-/*
- * (C) Copyright 2009-2010
- * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * pdm360ng board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_PDM360NG 1
-
-/*
- * Memory map for the PDM360NG board:
- *
- * 0x0000_0000 - 0x1FFF_FFFF	DDR RAM (512 MB)
- * 0x2000_0000 - 0x3FFF_FFFF	reserved (DDR RAM (512 MB)
- * 0x5000_0000 - 0x5001_FFFF	SRAM (128 KB)
- * 0x5004_0000 - 0x5005_FFFF	MRAM (CS2) (128 KB)
- * 0x8000_0000 - 0x803F_FFFF	IMMR (4 MB)
- * 0xF000_0000 - 0xF7FF_FFFF	NOR FLASH (CS0) (128 MB)
- * 0xF800_0000 - 0xFFFF_FFFF	NOR FLASH (CS1) (128 MB) optional
- */
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300		1	/* E300 Family */
-#define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
-
-#define	CONFIG_SYS_TEXT_BASE	0xF0000000
-
-/* Used for silent command in environment */
-#define CONFIG_SYS_DEVICE_NULLDEV
-
-/* Video */
-
-#if defined(CONFIG_VIDEO)
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_RLE8
-#endif
-
-#define CONFIG_SYS_MPC512X_CLKIN	33333333	/* in Hz */
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_IMMR			0x80000000
-#define CONFIG_SYS_DIU_ADDR		((CONFIG_SYS_IMMR) + 0x2100)
-
-/*
- * DDR Setup
- */
-
-/* DDR is system memory */
-#define CONFIG_SYS_DDR_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_MAX_RAM_SIZE		0x40000000
-
-/* DDR pin mux and slew rate */
-#define CONFIG_SYS_IOCTRL_MUX_DDR	0x00000012
-
-/* Manually set all parameters as there's no SPD etc. */
-/*
- * DDR Controller Configuration for Micron DDR2 SDRAM MT47H128M8-3
- *
- * SYS_CFG:
- *	[31:31]	MDDRC Soft Reset:	Diabled
- *	[30:30]	DRAM CKE pin:		Enabled
- *	[29:29]	DRAM CLK:		Enabled
- *	[28:28]	Command Mode:		Enabled (For initialization only)
- *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
- *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
- *	[20:19]	Read Test:		DON'T USE
- *	[18:18]	Self Refresh:		Enabled
- *	[17:17]	16bit Mode:		Disabled
- *	[16:13] Read Delay:		3
- *	[12:12]	Half DQS Delay:		Disabled
- *	[11:11]	Quarter DQS Delay:	Disabled
- *	[10:08]	Write Delay:		2
- *	[07:07]	Early ODT:		Disabled
- *	[06:06]	On DIE Termination:	Enabled
- *	[05:05]	FIFO Overflow Clear:	DON'T USE here
- *	[04:04]	FIFO Underflow Clear:	DON'T USE here
- *	[03:03]	FIFO Overflow Pending:	DON'T USE here
- *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
- *	[01:01]	FIFO Overlfow Enabled:	Enabled
- *	[00:00]	FIFO Underflow Enabled:	Enabled
- * TIME_CFG0
- *	[31:16]	DRAM Refresh Time:	0 CSB clocks
- *	[15:8]	DRAM Command Time:	0 CSB clocks
- *	[07:00]	DRAM Precharge Time:	0 CSB clocks
- * TIME_CFG1
- *	[31:26]	DRAM tRFC:
- *	[25:21]	DRAM tWR1:
- *	[20:17]	DRAM tWRT1:
- *	[16:11]	DRAM tDRR:
- *	[10:05]	DRAM tRC:
- *	[04:00]	DRAM tRAS:
- * TIME_CFG2
- *	[31:28]	DRAM tRCD:
- *	[27:23]	DRAM tFAW:
- *	[22:19]	DRAM tRTW1:
- *	[18:15]	DRAM tCCD:
- *	[14:10] DRAM tRTP:
- *	[09:05]	DRAM tRP:
- *	[04:00] DRAM tRPA
- */
-#define CONFIG_SYS_MDDRC_SYS_CFG	0xEA804A40
-#define CONFIG_SYS_MDDRC_TIME_CFG0	0x030C3D2E
-#define CONFIG_SYS_MDDRC_TIME_CFG1	0x68EC1168
-#define CONFIG_SYS_MDDRC_TIME_CFG2	0x34310864
-
-/*
- * Alternative 1: small RAM (128 MB) configuration
- */
-#define CONFIG_SYS_MDDRC_SYS_CFG_ALT1	0xE8604A40
-#define CONFIG_SYS_MDDRC_TIME_CFG0_ALT1	0x030C3D2E
-#define CONFIG_SYS_MDDRC_TIME_CFG1_ALT1	0x3CEC1168
-#define CONFIG_SYS_MDDRC_TIME_CFG2_ALT1	0x33310863
-
-#define CONFIG_SYS_MDDRC_SYS_CFG_EN	0xF0000000
-
-#define CONFIG_SYS_DDRCMD_NOP		0x01380000
-#define CONFIG_SYS_DDRCMD_PCHG_ALL	0x01100400
-#define CONFIG_SYS_DDRCMD_EM2		0x01020000  /* EMR2 */
-#define CONFIG_SYS_DDRCMD_EM3		0x01030000  /* EMR3 */
-/* EMR with 150 ohm ODT todo: verify */
-#define CONFIG_SYS_DDRCMD_EN_DLL	0x01010040
-#define CONFIG_SYS_DDRCMD_RES_DLL	0x01000100
-#define CONFIG_SYS_DDRCMD_RFSH		0x01080000
-#define CONFIG_SYS_MICRON_INIT_DEV_OP	0x01000432
-/* EMR with 150 ohm ODT todo: verify */
-#define CONFIG_SYS_DDRCMD_OCD_DEFAULT	0x010107C0
-/* EMR new command with 150 ohm ODT todo: verify */
-#define CONFIG_SYS_DDRCMD_OCD_EXIT	0x01010440
-
-/* DDR Priority Manager Configuration */
-#define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
-#define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
-#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
-#define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
-#define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
-#define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
-#define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
-#define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
-#define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
-#define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
-#define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
-#define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
-#define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
-#define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111
-
-/*
- * NOR FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI		/* use Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-#define CONFIG_SYS_FLASH_BASE		0xF0000000 /* start of FLASH-Bank0 */
-#define CONFIG_SYS_FLASH_SIZE		0x08000000 /* max size of a Bank */
-/* start of FLASH-Bank1 */
-#define CONFIG_SYS_FLASH1_BASE		(CONFIG_SYS_FLASH_BASE + \
-					 CONFIG_SYS_FLASH_SIZE)
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max sectors per device */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST \
-	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH1_BASE}
-
-#define CONFIG_SYS_SRAM_BASE		0x50000000
-#define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
-
-#define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH1_BASE
-#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_FLASH_SIZE
-
-/* ALE active low, data size 4 bytes */
-#define CONFIG_SYS_CS0_CFG		0x05059350
-/* ALE active low, data size 4 bytes */
-#define CONFIG_SYS_CS1_CFG		0x05059350
-
-#define CONFIG_SYS_MRAM_BASE		0x50040000
-#define CONFIG_SYS_MRAM_SIZE		0x00020000
-#define CONFIG_SYS_CS2_START		CONFIG_SYS_MRAM_BASE
-#define CONFIG_SYS_CS2_SIZE		CONFIG_SYS_MRAM_SIZE
-
-/* ALE active low, data size 4 bytes */
-#define CONFIG_SYS_CS2_CFG		0x05059110
-
-/* alt. CS timing for CS0, CS1, CS2 */
-#define CONFIG_SYS_CS_ALETIMING		0x00000007
-
-/*
- * NAND FLASH
- */
-#define CONFIG_CMD_NAND			/* enable NAND support */
-#define CONFIG_NAND_MPC5121_NFC
-#define CONFIG_SYS_NAND_BASE            0x40000000
-#define CONFIG_SYS_MAX_NAND_DEVICE      1
-#define CONFIG_SYS_NAND_SELECT_DEVICE	/* driver supports mutipl. chips */
-
-/*
- * Configuration parameters for MPC5121 NAND driver
- */
-#define CONFIG_FSL_NFC_WIDTH 1
-#define CONFIG_FSL_NFC_WRITE_SIZE 2048
-#define CONFIG_FSL_NFC_SPARE_SIZE 64
-#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
-
-/*
- * Dynamic MTD partition support
- */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT		"nor0=f0000000.flash,nor1=f8000000.flash," \
-						"nand0=MPC5121 NAND"
-
-/*
- * Flash layout
- */
-#define MTDPARTS_DEFAULT	"mtdparts=f0000000.flash:512k(u-boot),"	\
-						"256k(environment1),"	\
-						"256k(environment2),"	\
-						"256k(splash-factory)," \
-						"2m(FIT: recovery),"	\
-						"4608k(fs-recovery),"   \
-						"256k(splash-customer),"\
-						"5m(FIT: kernel+dtb),"	\
-						"64m(rootfs squash)ro,"	\
-						"51m(userfs ubi);"	\
-					"f8000000.flash:-(unused);"	\
-					"MPC5121 NAND:1024m(extended-userfs)"
-
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* Start of monitor */
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* 512 kB for monitor */
-#ifdef	CONFIG_FSL_DIU_FB
-#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024) /* for malloc */
-#else
-#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
-#endif
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX     1
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	6	/* console is on PSC6 */
-#if CONFIG_PSC_CONSOLE != 6
-#error CONFIG_PSC_CONSOLE must be 6
-#endif
-
-#define CONSOLE_FIFO_TX_SIZE	FIFOC_PSC6_TX_SIZE
-#define CONSOLE_FIFO_TX_ADDR	FIFOC_PSC6_TX_ADDR
-#define CONSOLE_FIFO_RX_SIZE	FIFOC_PSC6_RX_SIZE
-#define CONSOLE_FIFO_RX_ADDR	FIFOC_PSC6_RX_ADDR
-
-/*
- * Clocks in use
- */
-#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
-			 CLOCK_SCCR1_LPC_EN |				\
-			 CLOCK_SCCR1_NFC_EN |				\
-			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
-			 CLOCK_SCCR1_PSCFIFO_EN |			\
-			 CLOCK_SCCR1_DDR_EN |				\
-			 CLOCK_SCCR1_FEC_EN |				\
-			 CLOCK_SCCR1_TPR_EN)
-
-#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\
-			 CLOCK_SCCR2_SPDIF_EN |		\
-			 CLOCK_SCCR2_DIU_EN |		\
-			 CLOCK_SCCR2_I2C_EN)
-
-/*
- * Used PSC UART devices
- */
-#define CONFIG_SYS_PSC1
-#define CONFIG_SYS_PSC4
-#define CONFIG_SYS_PSC6
-
-/*
- * Co-processor communication parameters
- */
-#define CONFIG_SYS_PDM360NG_COPROC_READ_DELAY	5000
-#define CONFIG_SYS_PDM360NG_COPROC_BAUDRATE	38400
-
-/*
- * IIM - IC Identification Module
- */
-#undef CONFIG_FSL_IIM
-
-/*
- * Enabled only to delete "ethaddr" before testing
- * "ethaddr" setting from EEPROM
- */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC512x_FEC	1
-#define CONFIG_PHY_ADDR		0x1F
-#define CONFIG_MII		1	/* MII PHY management	*/
-#define CONFIG_FEC_AN_TIMEOUT	1
-#define CONFIG_HAS_ETH0
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-/* This has to be a multiple of the Flash sector size */
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
-				 CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x40000		/* one sector (256K) for env */
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-#define CONFIG_CMD_REGINFO
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-#ifdef CONFIG_CMD_KGDB
-	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
-#else
-	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
-#endif
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-/* Max number of command args */
-#define CONFIG_SYS_MAXARGS	16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-/* Decrementer freq: 1ms ticks */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-/* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
-
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE		32768
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#ifdef CONFIG_CMD_KGDB
-/* log base 2 of the above value */
-#define CONFIG_SYS_CACHELINE_SHIFT	5
-#endif
-
-#define CONFIG_SYS_HID0_INIT	0x000000000
-#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
-#define CONFIG_SYS_HID2	HID2_HBE
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#endif
-
-/* POST support */
-#define CONFIG_POST             (CONFIG_SYS_POST_COPROC)
-
-/*
- * Environment Configuration
- */
-#define CONFIG_TIMESTAMP
-
-#define CONFIG_HOSTNAME		pdm360ng
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR		400000
-
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo PDM360NG SAMPLE;" \
-	"echo"
-
-#define CONFIG_BOOTCOMMAND	"run env_cont"
-
-#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES	1
-
-#define OF_CPU			"PowerPC,5121@0"
-#define OF_SOC_COMPAT		"fsl,mpc5121-immr"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc@80000000/serial@11600"
-
-/*
- * Include common options for all mpc5121 boards
- */
-#include "mpc5121-common.h"
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/v38b.h b/include/configs/v38b.h
deleted file mode 100644
index 2bd6cc11ae..0000000000
--- a/include/configs/v38b.h
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering,
- * wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC5200			1	/* This is an MPC5200 CPU */
-#define CONFIG_V38B			1	/* ...on V38B board */
-
-#define	CONFIG_SYS_TEXT_BASE		0xFF000000
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000	/* ...running at 33.000000MHz */
-
-#define CONFIG_RTC_PCF8563		1	/* has PCF8563 RTC */
-#define CONFIG_MPC5200_DDR		1	/* has DDR SDRAM */
-
-#undef CONFIG_HW_WATCHDOG			/* don't use watchdog */
-
-#define CONFIG_NETCONSOLE		1
-
-#define CONFIG_BOARD_EARLY_INIT_R	1	/* do board-specific init */
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_XLB_PIPELINING		1	/* gives better performance */
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * DDR
- */
-#define SDRAM_DDR		1	/* is DDR */
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE		0x018D0000
-#define SDRAM_EMODE		0x40090000
-#define SDRAM_CONTROL		0x704f0f00
-#define SDRAM_CONFIG1		0x73722930
-#define SDRAM_CONFIG2		0x47770000
-#define SDRAM_TAPDELAY		0x10000000
-
-/*
- * PCI - no support
- */
-
-/*
- * USB
- */
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_CLOCK	0x0001BBBB
-#define CONFIG_USB_CONFIG	0x00001000
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_SDRAM
-
-#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-/*
- * Boot low with 16 MB Flash
- */
-#define CONFIG_SYS_LOWBOOT		1
-#define CONFIG_SYS_LOWBOOT16		1
-
-/*
- * Autobooting
- */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"bootcmd=run net_nfs\0"						\
-	"bootdelay=3\0"							\
-	"baudrate=115200\0"						\
-	"preboot=echo;echo Type \"run flash_nfs\" to mount root "	\
-		"filesystem over NFS; echo\0"				\
-	"netdev=eth0\0"							\
-	"ramargs=setenv bootargs root=/dev/ram rw wdt=off \0"		\
-	"addip=setenv bootargs $(bootargs) "				\
-		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
-		"$(netmask):$(hostname):$(netdev):off panic=1\0"	\
-	"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0"		\
-	"flash_self=run ramargs addip;bootm $(kernel_addr) "		\
-		"$(ramdisk_addr)\0"					\
-	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=$(serverip):$(rootpath) wdt=off\0"		\
-	"hostname=v38b\0"						\
-	"ethact=FEC\0"							\
-	"rootpath=/opt/eldk-3.1.1/ppc_6xx\0"				\
-	"update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; "	\
-		"cp.b 200000 ff000000 $(filesize);"			\
-		"prot on ff000000 ff03ffff\0"				\
-	"load=tftp 200000 $(u-boot)\0"					\
-	"netmask=255.255.0.0\0"						\
-	"ipaddr=192.168.160.18\0"					\
-	"serverip=192.168.1.1\0"					\
-	"bootfile=/tftpboot/v38b/uImage\0"				\
-	"u-boot=/tftpboot/v38b/u-boot.bin\0"				\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run net_nfs"
-
-/*
- * IPB Bus clocking configuration.
- */
-#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK			/* define for 133MHz speed */
-
-/*
- * Flash configuration - use CFI driver
- */
-#define CONFIG_SYS_FLASH_CFI		1		/* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER	1		/* Use the common driver */
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1
-#define CONFIG_SYS_FLASH_BASE		0xFF000000
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max num of flash banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_FLASH_SIZE		0x01000000	/* 16 MiB */
-#define CONFIG_SYS_MAX_FLASH_SECT	256		/* max num of sects on one chip */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1	/* flash write speed-up */
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)
-#define CONFIG_ENV_SIZE		0x10000
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_OVERWRITE	1
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Linux initial memory map */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR		0x00
-#define CONFIG_MII		1
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x90001404
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x00047801
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
-
-#define CONFIG_SYS_RESET_ADDRESS	0xff000000
-
-/*
- * IDE/ATA (supports IDE harddisk)
- */
-#undef CONFIG_IDE_8xx_PCCARD		/* Don't use IDE with PC Card Adapter */
-#undef CONFIG_IDE_8xx_DIRECT		/* Direct IDE not supported */
-#undef CONFIG_IDE_LED			/* LED for ide not supported */
-
-#define CONFIG_IDE_RESET		/* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
-
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)	/* data I/O offset */
-
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)	/* normal register accesses offset */
-
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)	/* alternate registers offset */
-
-#define CONFIG_SYS_ATA_STRIDE		4		/* Interval between registers */
-
-/*
- * Status LED
- */
-
-#define CONFIG_SYS_LED_BASE	MPC5XXX_GPT7_ENABLE	/* Timer 7 GPIO */
-#ifndef __ASSEMBLY__
-typedef unsigned int led_id_t;
-
-#define __led_toggle(_msk) \
-	do { \
-		*((volatile long *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \
-	} while(0)
-
-#define __led_set(_msk, _st) \
-	do { \
-		if ((_st)) \
-			*((volatile long *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \
-		else \
-			*((volatile long *) (CONFIG_SYS_LED_BASE)) |= (_msk); \
-	} while(0)
-
-#define __led_init(_msk, st) \
-	do { \
-		*((volatile long *) (CONFIG_SYS_LED_BASE)) |= 0x34; \
-	} while(0)
-#endif /* __ASSEMBLY__ */
-
-#endif /* __CONFIG_H */
diff --git a/include/keyboard.h b/include/keyboard.h
index 5cbd9f8ba8..9b51e20322 100644
--- a/include/keyboard.h
+++ b/include/keyboard.h
@@ -98,7 +98,7 @@ extern int kbd_init_hw(void);
 extern void pckbd_leds(unsigned char leds);
 #endif /* !CONFIG_DM_KEYBOARD */
 
-#if defined(CONFIG_MPC5xxx) || defined(CONFIG_ARCH_MPC8540) || \
+#if defined(CONFIG_ARCH_MPC8540) || \
 		defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
 int ps2ser_check(void);
 #endif
diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h
deleted file mode 100644
index 10daf0944b..0000000000
--- a/include/mpc5xxx.h
+++ /dev/null
@@ -1,893 +0,0 @@
-/*
- * include/asm-ppc/mpc5xxx.h
- *
- * Prototypes, etc. for the Motorola MPC5xxx
- * embedded cpu chips
- *
- * 2003 (c) MontaVista, Software, Inc.
- * Author: Dale Farnsworth <dfarnsworth@mvista.com>
- *
- * 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASMPPC_MPC5XXX_H
-#define __ASMPPC_MPC5XXX_H
-
-#include <asm/types.h>
-
-/* Processor name */
-#define CPU_ID_STR	"MPC5200"
-
-/* Exception offsets (PowerPC standard) */
-#define EXC_OFF_SYS_RESET	0x0100
-#define _START_OFFSET		EXC_OFF_SYS_RESET
-
-/* useful macros for manipulating CSx_START/STOP */
-#define START_REG(start)	((start) >> 16)
-#define STOP_REG(start, size)	(((start) + (size) - 1) >> 16)
-
-/* Internal memory map */
-
-#define MPC5XXX_CS0_START	(CONFIG_SYS_MBAR + 0x0004)
-#define MPC5XXX_CS0_STOP	(CONFIG_SYS_MBAR + 0x0008)
-#define MPC5XXX_CS1_START	(CONFIG_SYS_MBAR + 0x000c)
-#define MPC5XXX_CS1_STOP	(CONFIG_SYS_MBAR + 0x0010)
-#define MPC5XXX_CS2_START	(CONFIG_SYS_MBAR + 0x0014)
-#define MPC5XXX_CS2_STOP	(CONFIG_SYS_MBAR + 0x0018)
-#define MPC5XXX_CS3_START	(CONFIG_SYS_MBAR + 0x001c)
-#define MPC5XXX_CS3_STOP	(CONFIG_SYS_MBAR + 0x0020)
-#define MPC5XXX_CS4_START	(CONFIG_SYS_MBAR + 0x0024)
-#define MPC5XXX_CS4_STOP	(CONFIG_SYS_MBAR + 0x0028)
-#define MPC5XXX_CS5_START	(CONFIG_SYS_MBAR + 0x002c)
-#define MPC5XXX_CS5_STOP	(CONFIG_SYS_MBAR + 0x0030)
-#define MPC5XXX_BOOTCS_START	(CONFIG_SYS_MBAR + 0x004c)
-#define MPC5XXX_BOOTCS_STOP	(CONFIG_SYS_MBAR + 0x0050)
-#define MPC5XXX_ADDECR		(CONFIG_SYS_MBAR + 0x0054)
-
-#define MPC5XXX_CS6_START	(CONFIG_SYS_MBAR + 0x0058)
-#define MPC5XXX_CS6_STOP	(CONFIG_SYS_MBAR + 0x005c)
-#define MPC5XXX_CS7_START	(CONFIG_SYS_MBAR + 0x0060)
-#define MPC5XXX_CS7_STOP	(CONFIG_SYS_MBAR + 0x0064)
-#define MPC5XXX_SDRAM_CS0CFG	(CONFIG_SYS_MBAR + 0x0034)
-#define MPC5XXX_SDRAM_CS1CFG	(CONFIG_SYS_MBAR + 0x0038)
-
-#define MPC5XXX_SDRAM		(CONFIG_SYS_MBAR + 0x0100)
-#define MPC5XXX_CDM		(CONFIG_SYS_MBAR + 0x0200)
-#define MPC5XXX_LPB		(CONFIG_SYS_MBAR + 0x0300)
-#define MPC5XXX_ICTL		(CONFIG_SYS_MBAR + 0x0500)
-#define MPC5XXX_GPT		(CONFIG_SYS_MBAR + 0x0600)
-#define MPC5XXX_GPIO		(CONFIG_SYS_MBAR + 0x0b00)
-#define MPC5XXX_WU_GPIO         (CONFIG_SYS_MBAR + 0x0c00)
-#define MPC5XXX_PCI		(CONFIG_SYS_MBAR + 0x0d00)
-#define MPC5XXX_SPI		(CONFIG_SYS_MBAR + 0x0f00)
-#define MPC5XXX_USB		(CONFIG_SYS_MBAR + 0x1000)
-#define MPC5XXX_SDMA		(CONFIG_SYS_MBAR + 0x1200)
-#define MPC5XXX_XLBARB		(CONFIG_SYS_MBAR + 0x1f00)
-
-#define	MPC5XXX_PSC1		(CONFIG_SYS_MBAR + 0x2000)
-#define	MPC5XXX_PSC2		(CONFIG_SYS_MBAR + 0x2200)
-#define	MPC5XXX_PSC3		(CONFIG_SYS_MBAR + 0x2400)
-#define	MPC5XXX_PSC4		(CONFIG_SYS_MBAR + 0x2600)
-#define	MPC5XXX_PSC5		(CONFIG_SYS_MBAR + 0x2800)
-#define	MPC5XXX_PSC6		(CONFIG_SYS_MBAR + 0x2c00)
-
-#define	MPC5XXX_FEC		(CONFIG_SYS_MBAR + 0x3000)
-#define MPC5XXX_ATA             (CONFIG_SYS_MBAR + 0x3A00)
-
-#define MPC5XXX_I2C1		(CONFIG_SYS_MBAR + 0x3D00)
-#define MPC5XXX_I2C2		(CONFIG_SYS_MBAR + 0x3D40)
-
-#define MPC5XXX_SRAM		(CONFIG_SYS_MBAR + 0x8000)
-#define MPC5XXX_SRAM_SIZE	(16*1024)
-
-/* SDRAM Controller */
-#define MPC5XXX_SDRAM_MODE	(MPC5XXX_SDRAM + 0x0000)
-#define MPC5XXX_SDRAM_CTRL	(MPC5XXX_SDRAM + 0x0004)
-#define MPC5XXX_SDRAM_CONFIG1	(MPC5XXX_SDRAM + 0x0008)
-#define MPC5XXX_SDRAM_CONFIG2	(MPC5XXX_SDRAM + 0x000c)
-#define MPC5XXX_SDRAM_SDELAY	(MPC5XXX_SDRAM + 0x0090)
-
-/* Clock Distribution Module */
-#define MPC5XXX_CDM_JTAGID	(MPC5XXX_CDM + 0x0000)
-#define MPC5XXX_CDM_PORCFG	(MPC5XXX_CDM + 0x0004)
-#define MPC5XXX_CDM_BRDCRMB  	(MPC5XXX_CDM + 0x0008)
-#define MPC5XXX_CDM_CFG		(MPC5XXX_CDM + 0x000c)
-#define MPC5XXX_CDM_48_FDC	(MPC5XXX_CDM + 0x0010)
-#define MPC5XXX_CDM_CLK_ENA	(MPC5XXX_CDM + 0x0014)
-#define MPC5XXX_CDM_SRESET	(MPC5XXX_CDM + 0x0020)
-
-/* Local Plus Bus interface */
-#define MPC5XXX_CS0_CFG		(MPC5XXX_LPB + 0x0000)
-#define MPC5XXX_CS1_CFG		(MPC5XXX_LPB + 0x0004)
-#define MPC5XXX_CS2_CFG		(MPC5XXX_LPB + 0x0008)
-#define MPC5XXX_CS3_CFG		(MPC5XXX_LPB + 0x000c)
-#define MPC5XXX_CS4_CFG		(MPC5XXX_LPB + 0x0010)
-#define MPC5XXX_CS5_CFG		(MPC5XXX_LPB + 0x0014)
-#define MPC5XXX_BOOTCS_CFG	MPC5XXX_CS0_CFG
-#define MPC5XXX_CS_CTRL		(MPC5XXX_LPB + 0x0018)
-#define MPC5XXX_CS_STATUS	(MPC5XXX_LPB + 0x001c)
-#define MPC5XXX_CS6_CFG		(MPC5XXX_LPB + 0x0020)
-#define MPC5XXX_CS7_CFG		(MPC5XXX_LPB + 0x0024)
-#define MPC5XXX_CS_BURST	(MPC5XXX_LPB + 0x0028)
-#define MPC5XXX_CS_DEADCYCLE	(MPC5XXX_LPB + 0x002c)
-
-/* XLB Arbiter registers */
-#define MPC5XXX_XLBARB_CFG		(MPC5XXX_XLBARB + 0x40)
-#define MPC5XXX_XLBARB_MPRIEN	(MPC5XXX_XLBARB + 0x64)
-#define MPC5XXX_XLBARB_MPRIVAL	(MPC5XXX_XLBARB + 0x68)
-
-/* GPIO registers */
-#define MPC5XXX_GPS_PORT_CONFIG	(MPC5XXX_GPIO + 0x0000)
-
-/* Standard GPIO registers (simple, output only and simple interrupt */
-#define MPC5XXX_GPIO_ENABLE     (MPC5XXX_GPIO + 0x0004)
-#define MPC5XXX_GPIO_ODE        (MPC5XXX_GPIO + 0x0008)
-#define MPC5XXX_GPIO_DIR        (MPC5XXX_GPIO + 0x000c)
-#define MPC5XXX_GPIO_DATA_O     (MPC5XXX_GPIO + 0x0010)
-#define MPC5XXX_GPIO_DATA_I     (MPC5XXX_GPIO + 0x0014)
-#define MPC5XXX_GPIO_OO_ENABLE  (MPC5XXX_GPIO + 0x0018)
-#define MPC5XXX_GPIO_OO_DATA    (MPC5XXX_GPIO + 0x001C)
-#define MPC5XXX_GPIO_SI_ENABLE  (MPC5XXX_GPIO + 0x0020)
-#define MPC5XXX_GPIO_SI_ODE     (MPC5XXX_GPIO + 0x0024)
-#define MPC5XXX_GPIO_SI_DIR     (MPC5XXX_GPIO + 0x0028)
-#define MPC5XXX_GPIO_SI_DATA    (MPC5XXX_GPIO + 0x002C)
-#define MPC5XXX_GPIO_SI_IEN     (MPC5XXX_GPIO + 0x0030)
-#define MPC5XXX_GPIO_SI_ITYPE   (MPC5XXX_GPIO + 0x0034)
-#define MPC5XXX_GPIO_SI_MEN     (MPC5XXX_GPIO + 0x0038)
-#define MPC5XXX_GPIO_SI_STATUS  (MPC5XXX_GPIO + 0x003C)
-
-/* WakeUp GPIO registers */
-#define MPC5XXX_WU_GPIO_ENABLE  (MPC5XXX_WU_GPIO + 0x0000)
-#define MPC5XXX_WU_GPIO_ODE     (MPC5XXX_WU_GPIO + 0x0004)
-#define MPC5XXX_WU_GPIO_DIR     (MPC5XXX_WU_GPIO + 0x0008)
-#define MPC5XXX_WU_GPIO_DATA_O  (MPC5XXX_WU_GPIO + 0x000c)
-#define MPC5XXX_WU_GPIO_DATA_I  (MPC5XXX_WU_GPIO + 0x0020)
-
-/* GPIO pins, for Rev.B chip */
-#define GPIO_WKUP_7		0x80000000UL
-#define GPIO_PSC6_0		0x10000000UL
-#define GPIO_PSC3_9		0x04000000UL
-#define GPIO_PSC1_4		0x01000000UL
-#define GPIO_PSC2_4		0x02000000UL
-
-#define MPC5XXX_GPIO_SIMPLE_PSC6_3   0x20000000UL
-#define MPC5XXX_GPIO_SIMPLE_PSC6_2   0x10000000UL
-#define MPC5XXX_GPIO_SIMPLE_PSC3_7   0x00002000UL
-#define MPC5XXX_GPIO_SIMPLE_PSC3_6   0x00001000UL
-#define MPC5XXX_GPIO_SIMPLE_PSC3_3   0x00000800UL
-#define MPC5XXX_GPIO_SIMPLE_PSC3_2   0x00000400UL
-#define MPC5XXX_GPIO_SIMPLE_PSC3_1   0x00000200UL
-#define MPC5XXX_GPIO_SIMPLE_PSC3_0   0x00000100UL
-#define MPC5XXX_GPIO_SIMPLE_PSC2_3   0x00000080UL
-#define MPC5XXX_GPIO_SIMPLE_PSC2_2   0x00000040UL
-#define MPC5XXX_GPIO_SIMPLE_PSC2_1   0x00000020UL
-#define MPC5XXX_GPIO_SIMPLE_PSC2_0   0x00000010UL
-#define MPC5XXX_GPIO_SIMPLE_PSC1_3   0x00000008UL
-#define MPC5XXX_GPIO_SIMPLE_PSC1_2   0x00000004UL
-#define MPC5XXX_GPIO_SIMPLE_PSC1_1   0x00000002UL
-#define MPC5XXX_GPIO_SIMPLE_PSC1_0   0x00000001UL
-
-#define MPC5XXX_GPIO_SINT_ETH_16     0x80
-#define MPC5XXX_GPIO_SINT_ETH_15     0x40
-#define MPC5XXX_GPIO_SINT_ETH_14     0x20
-#define MPC5XXX_GPIO_SINT_ETH_13     0x10
-#define MPC5XXX_GPIO_SINT_USB1_9     0x08
-#define MPC5XXX_GPIO_SINT_PSC3_8     0x04
-#define MPC5XXX_GPIO_SINT_PSC3_5     0x02
-#define MPC5XXX_GPIO_SINT_PSC3_4     0x01
-
-#define MPC5XXX_GPIO_WKUP_7          0x80
-#define MPC5XXX_GPIO_WKUP_6          0x40
-#define MPC5XXX_GPIO_WKUP_PSC6_1     0x20
-#define MPC5XXX_GPIO_WKUP_PSC6_0     0x10
-#define MPC5XXX_GPIO_WKUP_ETH17      0x08
-#define MPC5XXX_GPIO_WKUP_PSC3_9     0x04
-#define MPC5XXX_GPIO_WKUP_PSC2_4     0x02
-#define MPC5XXX_GPIO_WKUP_PSC1_4     0x01
-
-/* PCI registers */
-#define MPC5XXX_PCI_CMD		(MPC5XXX_PCI + 0x04)
-#define MPC5XXX_PCI_CFG		(MPC5XXX_PCI + 0x0c)
-#define MPC5XXX_PCI_BAR0	(MPC5XXX_PCI + 0x10)
-#define MPC5XXX_PCI_BAR1	(MPC5XXX_PCI + 0x14)
-#define MPC5XXX_PCI_GSCR	(MPC5XXX_PCI + 0x60)
-#define MPC5XXX_PCI_TBATR0	(MPC5XXX_PCI + 0x64)
-#define MPC5XXX_PCI_TBATR1	(MPC5XXX_PCI + 0x68)
-#define MPC5XXX_PCI_TCR		(MPC5XXX_PCI + 0x6c)
-#define MPC5XXX_PCI_IW0BTAR	(MPC5XXX_PCI + 0x70)
-#define MPC5XXX_PCI_IW1BTAR	(MPC5XXX_PCI + 0x74)
-#define MPC5XXX_PCI_IW2BTAR	(MPC5XXX_PCI + 0x78)
-#define MPC5XXX_PCI_IWCR	(MPC5XXX_PCI + 0x80)
-#define MPC5XXX_PCI_ICR		(MPC5XXX_PCI + 0x84)
-#define MPC5XXX_PCI_ISR		(MPC5XXX_PCI + 0x88)
-#define MPC5XXX_PCI_ARB		(MPC5XXX_PCI + 0x8c)
-#define MPC5XXX_PCI_CAR		(MPC5XXX_PCI + 0xf8)
-
-/* Interrupt Controller registers */
-#define MPC5XXX_ICTL_PER_MASK	(MPC5XXX_ICTL + 0x0000)
-#define MPC5XXX_ICTL_PER_PRIO1	(MPC5XXX_ICTL + 0x0004)
-#define MPC5XXX_ICTL_PER_PRIO2	(MPC5XXX_ICTL + 0x0008)
-#define MPC5XXX_ICTL_PER_PRIO3	(MPC5XXX_ICTL + 0x000c)
-#define MPC5XXX_ICTL_EXT	(MPC5XXX_ICTL + 0x0010)
-#define MPC5XXX_ICTL_CRIT	(MPC5XXX_ICTL + 0x0014)
-#define MPC5XXX_ICTL_MAIN_PRIO1	(MPC5XXX_ICTL + 0x0018)
-#define MPC5XXX_ICTL_MAIN_PRIO2	(MPC5XXX_ICTL + 0x001c)
-#define MPC5XXX_ICTL_STS	(MPC5XXX_ICTL + 0x0024)
-#define MPC5XXX_ICTL_CRIT_STS	(MPC5XXX_ICTL + 0x0028)
-#define MPC5XXX_ICTL_MAIN_STS	(MPC5XXX_ICTL + 0x002c)
-#define MPC5XXX_ICTL_PER_STS	(MPC5XXX_ICTL + 0x0030)
-#define MPC5XXX_ICTL_BUS_STS	(MPC5XXX_ICTL + 0x0038)
-
-#define NR_IRQS			64
-
-/* IRQ mapping - these are our logical IRQ numbers */
-#define MPC5XXX_CRIT_IRQ_NUM	4
-#define MPC5XXX_MAIN_IRQ_NUM	17
-#define MPC5XXX_SDMA_IRQ_NUM	17
-#define MPC5XXX_PERP_IRQ_NUM	23
-
-#define MPC5XXX_CRIT_IRQ_BASE	1
-#define MPC5XXX_MAIN_IRQ_BASE	(MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM)
-#define MPC5XXX_SDMA_IRQ_BASE	(MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM)
-#define MPC5XXX_PERP_IRQ_BASE	(MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)
-
-#define MPC5XXX_IRQ0			(MPC5XXX_CRIT_IRQ_BASE + 0)
-#define MPC5XXX_SLICE_TIMER_0_IRQ	(MPC5XXX_CRIT_IRQ_BASE + 1)
-#define MPC5XXX_HI_INT_IRQ		(MPC5XXX_CRIT_IRQ_BASE + 2)
-#define MPC5XXX_CCS_IRQ			(MPC5XXX_CRIT_IRQ_BASE + 3)
-
-#define MPC5XXX_IRQ1			(MPC5XXX_MAIN_IRQ_BASE + 1)
-#define MPC5XXX_IRQ2			(MPC5XXX_MAIN_IRQ_BASE + 2)
-#define MPC5XXX_IRQ3			(MPC5XXX_MAIN_IRQ_BASE + 3)
-#define MPC5XXX_RTC_PINT_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 5)
-#define MPC5XXX_RTC_SINT_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 6)
-#define MPC5XXX_RTC_GPIO_STD_IRQ	(MPC5XXX_MAIN_IRQ_BASE + 7)
-#define MPC5XXX_RTC_GPIO_WKUP_IRQ	(MPC5XXX_MAIN_IRQ_BASE + 8)
-#define MPC5XXX_TMR0_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 9)
-#define MPC5XXX_TMR1_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 10)
-#define MPC5XXX_TMR2_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 11)
-#define MPC5XXX_TMR3_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 12)
-#define MPC5XXX_TMR4_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 13)
-#define MPC5XXX_TMR5_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 14)
-#define MPC5XXX_TMR6_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 15)
-#define MPC5XXX_TMR7_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 16)
-
-#define MPC5XXX_SDMA_IRQ		(MPC5XXX_PERP_IRQ_BASE + 0)
-#define MPC5XXX_PSC1_IRQ		(MPC5XXX_PERP_IRQ_BASE + 1)
-#define MPC5XXX_PSC2_IRQ		(MPC5XXX_PERP_IRQ_BASE + 2)
-#define MPC5XXX_PSC3_IRQ		(MPC5XXX_PERP_IRQ_BASE + 3)
-#define MPC5XXX_PSC6_IRQ		(MPC5XXX_PERP_IRQ_BASE + 4)
-#define MPC5XXX_IRDA_IRQ		(MPC5XXX_PERP_IRQ_BASE + 4)
-#define MPC5XXX_FEC_IRQ			(MPC5XXX_PERP_IRQ_BASE + 5)
-#define MPC5XXX_USB_IRQ			(MPC5XXX_PERP_IRQ_BASE + 6)
-#define MPC5XXX_ATA_IRQ			(MPC5XXX_PERP_IRQ_BASE + 7)
-#define MPC5XXX_PCI_CNTRL_IRQ		(MPC5XXX_PERP_IRQ_BASE + 8)
-#define MPC5XXX_PCI_SCIRX_IRQ		(MPC5XXX_PERP_IRQ_BASE + 9)
-#define MPC5XXX_PCI_SCITX_IRQ		(MPC5XXX_PERP_IRQ_BASE + 10)
-#define MPC5XXX_PSC4_IRQ		(MPC5XXX_PERP_IRQ_BASE + 11)
-#define MPC5XXX_PSC5_IRQ		(MPC5XXX_PERP_IRQ_BASE + 12)
-#define MPC5XXX_SPI_MODF_IRQ		(MPC5XXX_PERP_IRQ_BASE + 13)
-#define MPC5XXX_SPI_SPIF_IRQ		(MPC5XXX_PERP_IRQ_BASE + 14)
-#define MPC5XXX_I2C1_IRQ		(MPC5XXX_PERP_IRQ_BASE + 15)
-#define MPC5XXX_I2C2_IRQ		(MPC5XXX_PERP_IRQ_BASE + 16)
-#define MPC5XXX_MSCAN1_IRQ		(MPC5XXX_PERP_IRQ_BASE + 17)
-#define MPC5XXX_MSCAN2_IRQ		(MPC5XXX_PERP_IRQ_BASE + 18)
-#define MPC5XXX_IR_RX_IRQ		(MPC5XXX_PERP_IRQ_BASE + 19)
-#define MPC5XXX_IR_TX_IRQ		(MPC5XXX_PERP_IRQ_BASE + 20)
-#define MPC5XXX_XLB_ARB_IRQ		(MPC5XXX_PERP_IRQ_BASE + 21)
-#define MPC5XXX_BDLC_IRQ		(MPC5XXX_PERP_IRQ_BASE + 22)
-
-/* General Purpose Timers registers */
-#define MPC5XXX_GPT0_ENABLE		(MPC5XXX_GPT + 0x0)
-#define MPC5XXX_GPT0_COUNTER		(MPC5XXX_GPT + 0x4)
-#define MPC5XXX_GPT0_STATUS		(MPC5XXX_GPT + 0x0C)
-#define MPC5XXX_GPT1_ENABLE		(MPC5XXX_GPT + 0x10)
-#define MPC5XXX_GPT1_COUNTER		(MPC5XXX_GPT + 0x14)
-#define MPC5XXX_GPT1_STATUS		(MPC5XXX_GPT + 0x1C)
-#define MPC5XXX_GPT2_ENABLE		(MPC5XXX_GPT + 0x20)
-#define MPC5XXX_GPT2_COUNTER		(MPC5XXX_GPT + 0x24)
-#define MPC5XXX_GPT2_STATUS		(MPC5XXX_GPT + 0x2C)
-#define MPC5XXX_GPT3_ENABLE		(MPC5XXX_GPT + 0x30)
-#define MPC5XXX_GPT3_COUNTER		(MPC5XXX_GPT + 0x34)
-#define MPC5XXX_GPT3_STATUS		(MPC5XXX_GPT + 0x3C)
-#define MPC5XXX_GPT4_ENABLE		(MPC5XXX_GPT + 0x40)
-#define MPC5XXX_GPT4_COUNTER		(MPC5XXX_GPT + 0x44)
-#define MPC5XXX_GPT4_STATUS		(MPC5XXX_GPT + 0x4C)
-#define MPC5XXX_GPT5_ENABLE		(MPC5XXX_GPT + 0x50)
-#define MPC5XXX_GPT5_STATUS		(MPC5XXX_GPT + 0x5C)
-#define MPC5XXX_GPT5_COUNTER		(MPC5XXX_GPT + 0x54)
-#define MPC5XXX_GPT6_ENABLE		(MPC5XXX_GPT + 0x60)
-#define MPC5XXX_GPT6_COUNTER		(MPC5XXX_GPT + 0x64)
-#define MPC5XXX_GPT6_STATUS		(MPC5XXX_GPT + 0x6C)
-#define MPC5XXX_GPT7_ENABLE		(MPC5XXX_GPT + 0x70)
-#define MPC5XXX_GPT7_COUNTER		(MPC5XXX_GPT + 0x74)
-#define MPC5XXX_GPT7_STATUS		(MPC5XXX_GPT + 0x7C)
-
-#define MPC5XXX_GPT_GPIO_PIN(status)	((0x00000100 & (status)) >> 8)
-
-#define MPC5XXX_GPT7_PWMCFG		(MPC5XXX_GPT + 0x78)
-
-/* ATA registers */
-#define MPC5XXX_ATA_HOST_CONFIG         (MPC5XXX_ATA + 0x0000)
-#define MPC5XXX_ATA_PIO1                (MPC5XXX_ATA + 0x0008)
-#define MPC5XXX_ATA_PIO2                (MPC5XXX_ATA + 0x000C)
-#define MPC5XXX_ATA_SHARE_COUNT         (MPC5XXX_ATA + 0x002C)
-
-/* I2Cn control register bits */
-#define I2C_EN		0x80
-#define I2C_IEN		0x40
-#define I2C_STA		0x20
-#define I2C_TX		0x10
-#define I2C_TXAK	0x08
-#define I2C_RSTA	0x04
-#define I2C_INIT_MASK	(I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
-
-/* I2Cn status register bits */
-#define I2C_CF		0x80
-#define I2C_AAS		0x40
-#define I2C_BB		0x20
-#define I2C_AL		0x10
-#define I2C_SRW		0x04
-#define I2C_IF		0x02
-#define I2C_RXAK	0x01
-
-/* SPI control register 1 bits */
-#define SPI_CR_LSBFE	0x01
-#define SPI_CR_SSOE	0x02
-#define SPI_CR_CPHA	0x04
-#define SPI_CR_CPOL	0x08
-#define SPI_CR_MSTR	0x10
-#define SPI_CR_SWOM	0x20
-#define SPI_CR_SPE	0x40
-#define SPI_CR_SPIE	0x80
-
-/* SPI status register bits */
-#define SPI_SR_MODF	0x10
-#define SPI_SR_WCOL	0x40
-#define SPI_SR_SPIF	0x80
-
-/* SPI port data register bits */
-#define SPI_PDR_SS	0x08
-
-/* Programmable Serial Controller (PSC) status register bits */
-#define PSC_SR_CDE		0x0080
-#define PSC_SR_RXRDY		0x0100
-#define PSC_SR_RXFULL		0x0200
-#define PSC_SR_TXRDY		0x0400
-#define PSC_SR_TXEMP		0x0800
-#define PSC_SR_OE		0x1000
-#define PSC_SR_PE		0x2000
-#define PSC_SR_FE		0x4000
-#define PSC_SR_RB		0x8000
-
-/* PSC Command values */
-#define PSC_RX_ENABLE		0x0001
-#define PSC_RX_DISABLE		0x0002
-#define PSC_TX_ENABLE		0x0004
-#define PSC_TX_DISABLE		0x0008
-#define PSC_SEL_MODE_REG_1	0x0010
-#define PSC_RST_RX		0x0020
-#define PSC_RST_TX		0x0030
-#define PSC_RST_ERR_STAT	0x0040
-#define PSC_RST_BRK_CHG_INT	0x0050
-#define PSC_START_BRK		0x0060
-#define PSC_STOP_BRK		0x0070
-
-/* PSC Rx FIFO status bits */
-#define PSC_RX_FIFO_ERR		0x0040
-#define PSC_RX_FIFO_UF		0x0020
-#define PSC_RX_FIFO_OF		0x0010
-#define PSC_RX_FIFO_FR		0x0008
-#define PSC_RX_FIFO_FULL	0x0004
-#define PSC_RX_FIFO_ALARM	0x0002
-#define PSC_RX_FIFO_EMPTY	0x0001
-
-/* PSC interrupt mask bits */
-#define PSC_IMR_TXRDY		0x0100
-#define PSC_IMR_RXRDY		0x0200
-#define PSC_IMR_DB		0x0400
-#define PSC_IMR_IPC		0x8000
-
-/* PSC input port change bits */
-#define PSC_IPCR_CTS		0x01
-#define PSC_IPCR_DCD		0x02
-
-/* PSC mode fields */
-#define PSC_MODE_5_BITS		0x00
-#define PSC_MODE_6_BITS		0x01
-#define PSC_MODE_7_BITS		0x02
-#define PSC_MODE_8_BITS		0x03
-#define PSC_MODE_PAREVEN	0x00
-#define PSC_MODE_PARODD		0x04
-#define PSC_MODE_PARFORCE	0x08
-#define PSC_MODE_PARNONE	0x10
-#define PSC_MODE_ERR		0x20
-#define PSC_MODE_FFULL		0x40
-#define PSC_MODE_RXRTS		0x80
-
-#define PSC_MODE_ONE_STOP_5_BITS	0x00
-#define PSC_MODE_ONE_STOP		0x07
-#define PSC_MODE_TWO_STOP		0x0f
-
-/* ATA config fields */
-#define MPC5xxx_ATA_HOSTCONF_SMR	0x80000000UL	/* State machine
-							   reset */
-#define MPC5xxx_ATA_HOSTCONF_FR		0x40000000UL	/* FIFO Reset */
-#define MPC5xxx_ATA_HOSTCONF_IE		0x02000000UL	/* Enable interrupt
-							   in PIO */
-#define MPC5xxx_ATA_HOSTCONF_IORDY	0x01000000UL	/* Drive supports
-							   IORDY protocol */
-
-#ifndef __ASSEMBLY__
-/* Memory map registers */
-struct mpc5xxx_mmap_ctl {
-	volatile u32	mbar;
-	volatile u32	cs0_start;	/* 0x0004 */
-	volatile u32	cs0_stop;
-	volatile u32	cs1_start;	/* 0x000c */
-	volatile u32	cs1_stop;
-	volatile u32	cs2_start;	/* 0x0014 */
-	volatile u32	cs2_stop;
-	volatile u32	cs3_start;	/* 0x001c */
-	volatile u32	cs3_stop;
-	volatile u32	cs4_start;	/* 0x0024 */
-	volatile u32	cs4_stop;
-	volatile u32	cs5_start;	/* 0x002c */
-	volatile u32	cs5_stop;
-	volatile u32	sdram0;		/* 0x0034 */
-	volatile u32	sdram1;		/* 0x0038 */
-	volatile u32	dummy1[4];	/* 0x003c */
-	volatile u32	boot_start;	/* 0x004c */
-	volatile u32	boot_stop;
-	volatile u32	ipbi_ws_ctrl;	/* 0x0054 */
-	volatile u32	cs6_start;	/* 0x0058 */
-	volatile u32	cs6_stop;
-	volatile u32	cs7_start;	/* 0x0060 */
-	volatile u32	cs7_stop;
-};
-
-/* Clock distribution module */
-struct mpc5xxx_cdm {
-	volatile u32	jtagid;		/* 0x0000 */
-	volatile u32	porcfg;
-	volatile u32	brdcrmb;	/* 0x0008 */
-	volatile u32	cfg;
-	volatile u32	fourtyeight_fdc;/* 0x0010 */
-	volatile u32	clock_enable;
-	volatile u32	system_osc;	/* 0x0018 */
-	volatile u32	ccscr;
-	volatile u32	sreset;		/* 0x0020 */
-	volatile u32	pll_status;
-	volatile u32	psc1_mccr;	/* 0x0028 */
-	volatile u32	psc2_mccr;
-	volatile u32	psc3_mccr;	/* 0x0030 */
-	volatile u32	psc6_mccr;
-};
-
-/* SDRAM controller */
-struct mpc5xxx_sdram {
-	volatile u32	mode;
-	volatile u32	ctrl;
-	volatile u32	config1;
-	volatile u32	config2;
-	volatile u32	dummy[32];
-	volatile u32	sdelay;
-};
-
-struct mpc5xxx_lpb {
-	volatile u32	cs0_cfg;
-	volatile u32	cs1_cfg;
-	volatile u32	cs2_cfg;
-	volatile u32	cs3_cfg;
-	volatile u32	cs4_cfg;
-	volatile u32	cs5_cfg;
-	volatile u32	cs_ctrl;
-	volatile u32	cs_status;
-	volatile u32	cs6_cfg;
-	volatile u32	cs7_cfg;
-	volatile u32	cs_burst;
-	volatile u32	cs_deadcycle;
-};
-
-
-struct mpc5xxx_psc {
-	volatile u8	mode;		/* PSC + 0x00 */
-	volatile u8	reserved0[3];
-	union {				/* PSC + 0x04 */
-		volatile u16	status;
-		volatile u16	clock_select;
-	} sr_csr;
-#define psc_status	sr_csr.status
-#define psc_clock_select sr_csr.clock_select
-	volatile u16	reserved1;
-	volatile u8	command;	/* PSC + 0x08 */
-	volatile u8	reserved2[3];
-	union {				/* PSC + 0x0c */
-		volatile u8	buffer_8;
-		volatile u16	buffer_16;
-		volatile u32	buffer_32;
-	} buffer;
-#define psc_buffer_8	buffer.buffer_8
-#define psc_buffer_16	buffer.buffer_16
-#define psc_buffer_32	buffer.buffer_32
-	union {				/* PSC + 0x10 */
-		volatile u8	ipcr;
-		volatile u8	acr;
-	} ipcr_acr;
-#define psc_ipcr	ipcr_acr.ipcr
-#define psc_acr		ipcr_acr.acr
-	volatile u8	reserved3[3];
-	union {				/* PSC + 0x14 */
-		volatile u16	isr;
-		volatile u16	imr;
-	} isr_imr;
-#define psc_isr		isr_imr.isr
-#define psc_imr		isr_imr.imr
-	volatile u16	reserved4;
-	volatile u8	ctur;		/* PSC + 0x18 */
-	volatile u8	reserved5[3];
-	volatile u8	ctlr;		/* PSC + 0x1c */
-	volatile u8	reserved6[3];
-	volatile u16	ccr;		/* PSC + 0x20 */
-	volatile u8	reserved7[14];
-	volatile u8	ivr;		/* PSC + 0x30 */
-	volatile u8	reserved8[3];
-	volatile u8	ip;		/* PSC + 0x34 */
-	volatile u8	reserved9[3];
-	volatile u8	op1;		/* PSC + 0x38 */
-	volatile u8	reserved10[3];
-	volatile u8	op0;		/* PSC + 0x3c */
-	volatile u8	reserved11[3];
-	volatile u32	sicr;		/* PSC + 0x40 */
-	volatile u8	ircr1;		/* PSC + 0x44 */
-	volatile u8	reserved12[3];
-	volatile u8	ircr2;		/* PSC + 0x44 */
-	volatile u8	reserved13[3];
-	volatile u8	irsdr;		/* PSC + 0x4c */
-	volatile u8	reserved14[3];
-	volatile u8	irmdr;		/* PSC + 0x50 */
-	volatile u8	reserved15[3];
-	volatile u8	irfdr;		/* PSC + 0x54 */
-	volatile u8	reserved16[3];
-	volatile u16	rfnum;		/* PSC + 0x58 */
-	volatile u16	reserved17;
-	volatile u16	tfnum;		/* PSC + 0x5c */
-	volatile u16	reserved18;
-	volatile u32	rfdata;		/* PSC + 0x60 */
-	volatile u16	rfstat;		/* PSC + 0x64 */
-	volatile u16	reserved20;
-	volatile u8	rfcntl;		/* PSC + 0x68 */
-	volatile u8	reserved21[5];
-	volatile u16	rfalarm;	/* PSC + 0x6e */
-	volatile u16	reserved22;
-	volatile u16	rfrptr;		/* PSC + 0x72 */
-	volatile u16	reserved23;
-	volatile u16	rfwptr;		/* PSC + 0x76 */
-	volatile u16	reserved24;
-	volatile u16	rflrfptr;	/* PSC + 0x7a */
-	volatile u16	reserved25;
-	volatile u16	rflwfptr;	/* PSC + 0x7e */
-	volatile u32	tfdata;		/* PSC + 0x80 */
-	volatile u16	tfstat;		/* PSC + 0x84 */
-	volatile u16	reserved26;
-	volatile u8	tfcntl;		/* PSC + 0x88 */
-	volatile u8	reserved27[5];
-	volatile u16	tfalarm;	/* PSC + 0x8e */
-	volatile u16	reserved28;
-	volatile u16	tfrptr;		/* PSC + 0x92 */
-	volatile u16	reserved29;
-	volatile u16	tfwptr;		/* PSC + 0x96 */
-	volatile u16	reserved30;
-	volatile u16	tflrfptr;	/* PSC + 0x9a */
-	volatile u16	reserved31;
-	volatile u16	tflwfptr;	/* PSC + 0x9e */
-};
-
-struct mpc5xxx_intr {
-	volatile u32	per_mask;	/* INTR + 0x00 */
-	volatile u32	per_pri1;	/* INTR + 0x04 */
-	volatile u32	per_pri2;	/* INTR + 0x08 */
-	volatile u32	per_pri3;	/* INTR + 0x0c */
-	volatile u32	ctrl;		/* INTR + 0x10 */
-	volatile u32	main_mask;	/* INTR + 0x14 */
-	volatile u32	main_pri1;	/* INTR + 0x18 */
-	volatile u32	main_pri2;	/* INTR + 0x1c */
-	volatile u32	reserved1;	/* INTR + 0x20 */
-	volatile u32	enc_status;	/* INTR + 0x24 */
-	volatile u32	crit_status;	/* INTR + 0x28 */
-	volatile u32	main_status;	/* INTR + 0x2c */
-	volatile u32	per_status;	/* INTR + 0x30 */
-	volatile u32	reserved2;	/* INTR + 0x34 */
-	volatile u32	per_error;	/* INTR + 0x38 */
-};
-
-struct mpc5xxx_gpio {
-	volatile u32 port_config;	/* GPIO + 0x00 */
-	volatile u32 simple_gpioe;	/* GPIO + 0x04 */
-	volatile u32 simple_ode;	/* GPIO + 0x08 */
-	volatile u32 simple_ddr;	/* GPIO + 0x0c */
-	volatile u32 simple_dvo;	/* GPIO + 0x10 */
-	volatile u32 simple_ival;	/* GPIO + 0x14 */
-	volatile u8 outo_gpioe;		/* GPIO + 0x18 */
-	volatile u8 reserved1[3];	/* GPIO + 0x19 */
-	volatile u8 outo_dvo;		/* GPIO + 0x1c */
-	volatile u8 reserved2[3];	/* GPIO + 0x1d */
-	volatile u8 sint_gpioe;		/* GPIO + 0x20 */
-	volatile u8 reserved3[3];	/* GPIO + 0x21 */
-	volatile u8 sint_ode;		/* GPIO + 0x24 */
-	volatile u8 reserved4[3];	/* GPIO + 0x25 */
-	volatile u8 sint_ddr;		/* GPIO + 0x28 */
-	volatile u8 reserved5[3];	/* GPIO + 0x29 */
-	volatile u8 sint_dvo;		/* GPIO + 0x2c */
-	volatile u8 reserved6[3];	/* GPIO + 0x2d */
-	volatile u8 sint_inten;		/* GPIO + 0x30 */
-	volatile u8 reserved7[3];	/* GPIO + 0x31 */
-	volatile u16 sint_itype;	/* GPIO + 0x34 */
-	volatile u16 reserved8;		/* GPIO + 0x36 */
-	volatile u8 gpio_control;	/* GPIO + 0x38 */
-	volatile u8 reserved9[3];	/* GPIO + 0x39 */
-	volatile u8 sint_istat;		/* GPIO + 0x3c */
-	volatile u8 sint_ival;		/* GPIO + 0x3d */
-	volatile u8 bus_errs;		/* GPIO + 0x3e */
-	volatile u8 reserved10;		/* GPIO + 0x3f */
-};
-
-struct mpc5xxx_wu_gpio {
-	volatile u8 enable;		/* WU_GPIO + 0x00 */
-	volatile u8 reserved1[3];	/* WU_GPIO + 0x01 */
-	volatile u8 ode;		/* WU_GPIO + 0x04 */
-	volatile u8 reserved2[3];	/* WU_GPIO + 0x05 */
-	volatile u8 ddr;		/* WU_GPIO + 0x08 */
-	volatile u8 reserved3[3];	/* WU_GPIO + 0x09 */
-	volatile u8 dvo;		/* WU_GPIO + 0x0c */
-	volatile u8 reserved4[3];	/* WU_GPIO + 0x0d */
-	volatile u8 inten;		/* WU_GPIO + 0x10 */
-	volatile u8 reserved5[3];	/* WU_GPIO + 0x11 */
-	volatile u8 iinten;		/* WU_GPIO + 0x14 */
-	volatile u8 reserved6[3];	/* WU_GPIO + 0x15 */
-	volatile u16 itype;		/* WU_GPIO + 0x18 */
-	volatile u8 reserved7[2];	/* WU_GPIO + 0x1a */
-	volatile u8 master_enable;	/* WU_GPIO + 0x1c */
-	volatile u8 reserved8[3];	/* WU_GPIO + 0x1d */
-	volatile u8 ival;		/* WU_GPIO + 0x20 */
-	volatile u8 reserved9[3];	/* WU_GPIO + 0x21 */
-	volatile u8 status;		/* WU_GPIO + 0x24 */
-	volatile u8 reserved10[3];	/* WU_GPIO + 0x25 */
-};
-
-struct mpc5xxx_sdma {
-	volatile u32 taskBar;		/* SDMA + 0x00 */
-	volatile u32 currentPointer;	/* SDMA + 0x04 */
-	volatile u32 endPointer;	/* SDMA + 0x08 */
-	volatile u32 variablePointer;	/* SDMA + 0x0c */
-
-	volatile u8 IntVect1;		/* SDMA + 0x10 */
-	volatile u8 IntVect2;		/* SDMA + 0x11 */
-	volatile u16 PtdCntrl;		/* SDMA + 0x12 */
-
-	volatile u32 IntPend;		/* SDMA + 0x14 */
-	volatile u32 IntMask;		/* SDMA + 0x18 */
-
-	volatile u16 tcr_0;		/* SDMA + 0x1c */
-	volatile u16 tcr_1;		/* SDMA + 0x1e */
-	volatile u16 tcr_2;		/* SDMA + 0x20 */
-	volatile u16 tcr_3;		/* SDMA + 0x22 */
-	volatile u16 tcr_4;		/* SDMA + 0x24 */
-	volatile u16 tcr_5;		/* SDMA + 0x26 */
-	volatile u16 tcr_6;		/* SDMA + 0x28 */
-	volatile u16 tcr_7;		/* SDMA + 0x2a */
-	volatile u16 tcr_8;		/* SDMA + 0x2c */
-	volatile u16 tcr_9;		/* SDMA + 0x2e */
-	volatile u16 tcr_a;		/* SDMA + 0x30 */
-	volatile u16 tcr_b;		/* SDMA + 0x32 */
-	volatile u16 tcr_c;		/* SDMA + 0x34 */
-	volatile u16 tcr_d;		/* SDMA + 0x36 */
-	volatile u16 tcr_e;		/* SDMA + 0x38 */
-	volatile u16 tcr_f;		/* SDMA + 0x3a */
-
-	volatile u8 IPR0;		/* SDMA + 0x3c */
-	volatile u8 IPR1;		/* SDMA + 0x3d */
-	volatile u8 IPR2;		/* SDMA + 0x3e */
-	volatile u8 IPR3;		/* SDMA + 0x3f */
-	volatile u8 IPR4;		/* SDMA + 0x40 */
-	volatile u8 IPR5;		/* SDMA + 0x41 */
-	volatile u8 IPR6;		/* SDMA + 0x42 */
-	volatile u8 IPR7;		/* SDMA + 0x43 */
-	volatile u8 IPR8;		/* SDMA + 0x44 */
-	volatile u8 IPR9;		/* SDMA + 0x45 */
-	volatile u8 IPR10;		/* SDMA + 0x46 */
-	volatile u8 IPR11;		/* SDMA + 0x47 */
-	volatile u8 IPR12;		/* SDMA + 0x48 */
-	volatile u8 IPR13;		/* SDMA + 0x49 */
-	volatile u8 IPR14;		/* SDMA + 0x4a */
-	volatile u8 IPR15;		/* SDMA + 0x4b */
-	volatile u8 IPR16;		/* SDMA + 0x4c */
-	volatile u8 IPR17;		/* SDMA + 0x4d */
-	volatile u8 IPR18;		/* SDMA + 0x4e */
-	volatile u8 IPR19;		/* SDMA + 0x4f */
-	volatile u8 IPR20;		/* SDMA + 0x50 */
-	volatile u8 IPR21;		/* SDMA + 0x51 */
-	volatile u8 IPR22;		/* SDMA + 0x52 */
-	volatile u8 IPR23;		/* SDMA + 0x53 */
-	volatile u8 IPR24;		/* SDMA + 0x54 */
-	volatile u8 IPR25;		/* SDMA + 0x55 */
-	volatile u8 IPR26;		/* SDMA + 0x56 */
-	volatile u8 IPR27;		/* SDMA + 0x57 */
-	volatile u8 IPR28;		/* SDMA + 0x58 */
-	volatile u8 IPR29;		/* SDMA + 0x59 */
-	volatile u8 IPR30;		/* SDMA + 0x5a */
-	volatile u8 IPR31;		/* SDMA + 0x5b */
-
-	volatile u32 res1;		/* SDMA + 0x5c */
-	volatile u32 res2;		/* SDMA + 0x60 */
-	volatile u32 res3;		/* SDMA + 0x64 */
-	volatile u32 MDEDebug;		/* SDMA + 0x68 */
-	volatile u32 ADSDebug;		/* SDMA + 0x6c */
-	volatile u32 Value1;		/* SDMA + 0x70 */
-	volatile u32 Value2;		/* SDMA + 0x74 */
-	volatile u32 Control;		/* SDMA + 0x78 */
-	volatile u32 Status;		/* SDMA + 0x7c */
-	volatile u32 EU00;		/* SDMA + 0x80 */
-	volatile u32 EU01;		/* SDMA + 0x84 */
-	volatile u32 EU02;		/* SDMA + 0x88 */
-	volatile u32 EU03;		/* SDMA + 0x8c */
-	volatile u32 EU04;		/* SDMA + 0x90 */
-	volatile u32 EU05;		/* SDMA + 0x94 */
-	volatile u32 EU06;		/* SDMA + 0x98 */
-	volatile u32 EU07;		/* SDMA + 0x9c */
-	volatile u32 EU10;		/* SDMA + 0xa0 */
-	volatile u32 EU11;		/* SDMA + 0xa4 */
-	volatile u32 EU12;		/* SDMA + 0xa8 */
-	volatile u32 EU13;		/* SDMA + 0xac */
-	volatile u32 EU14;		/* SDMA + 0xb0 */
-	volatile u32 EU15;		/* SDMA + 0xb4 */
-	volatile u32 EU16;		/* SDMA + 0xb8 */
-	volatile u32 EU17;		/* SDMA + 0xbc */
-	volatile u32 EU20;		/* SDMA + 0xc0 */
-	volatile u32 EU21;		/* SDMA + 0xc4 */
-	volatile u32 EU22;		/* SDMA + 0xc8 */
-	volatile u32 EU23;		/* SDMA + 0xcc */
-	volatile u32 EU24;		/* SDMA + 0xd0 */
-	volatile u32 EU25;		/* SDMA + 0xd4 */
-	volatile u32 EU26;		/* SDMA + 0xd8 */
-	volatile u32 EU27;		/* SDMA + 0xdc */
-	volatile u32 EU30;		/* SDMA + 0xe0 */
-	volatile u32 EU31;		/* SDMA + 0xe4 */
-	volatile u32 EU32;		/* SDMA + 0xe8 */
-	volatile u32 EU33;		/* SDMA + 0xec */
-	volatile u32 EU34;		/* SDMA + 0xf0 */
-	volatile u32 EU35;		/* SDMA + 0xf4 */
-	volatile u32 EU36;		/* SDMA + 0xf8 */
-	volatile u32 EU37;		/* SDMA + 0xfc */
-};
-
-struct mpc5xxx_i2c {
-	volatile u32 madr;		/* I2Cn + 0x00 */
-	volatile u32 mfdr;		/* I2Cn + 0x04 */
-	volatile u32 mcr;		/* I2Cn + 0x08 */
-	volatile u32 msr;		/* I2Cn + 0x0C */
-	volatile u32 mdr;		/* I2Cn + 0x10 */
-};
-
-struct mpc5xxx_spi {
-	volatile u8 cr1;		/* SPI + 0x0F00 */
-	volatile u8 cr2;		/* SPI + 0x0F01 */
-	volatile u8 reserved1[2];
-	volatile u8 brr;		/* SPI + 0x0F04 */
-	volatile u8 sr;			/* SPI + 0x0F05 */
-	volatile u8 reserved2[3];
-	volatile u8 dr;			/* SPI + 0x0F09 */
-	volatile u8 reserved3[3];
-	volatile u8 pdr;		/* SPI + 0x0F0D */
-	volatile u8 reserved4[2];
-	volatile u8 ddr;		/* SPI + 0x0F10 */
-};
-
-
-struct mpc5xxx_gpt {
-	volatile u32 emsr;		/* GPT + Timer# * 0x10 + 0x00 */
-	volatile u32 cir;		/* GPT + Timer# * 0x10 + 0x04 */
-	volatile u32 pwmcr;		/* GPT + Timer# * 0x10 + 0x08 */
-	volatile u32 sr;		/* GPT + Timer# * 0x10 + 0x0c */
-};
-
-struct mpc5xxx_gpt_0_7 {
-	struct mpc5xxx_gpt gpt0;
-	struct mpc5xxx_gpt gpt1;
-	struct mpc5xxx_gpt gpt2;
-	struct mpc5xxx_gpt gpt3;
-	struct mpc5xxx_gpt gpt4;
-	struct mpc5xxx_gpt gpt5;
-	struct mpc5xxx_gpt gpt6;
-	struct mpc5xxx_gpt gpt7;
-};
-
-struct mscan_buffer {
-	volatile u8  idr[0x8];          /* 0x00 */
-	volatile u8  dsr[0x10];         /* 0x08 */
-	volatile u8  dlr;               /* 0x18 */
-	volatile u8  tbpr;              /* 0x19 */      /* This register is not applicable for receive buffers */
-	volatile u16 rsrv1;             /* 0x1A */
-	volatile u8  tsrh;              /* 0x1C */
-	volatile u8  tsrl;              /* 0x1D */
-	volatile u16 rsrv2;             /* 0x1E */
-};
-
-struct mpc5xxx_mscan {
-	volatile u8  canctl0;           /* MSCAN + 0x00 */
-	volatile u8  canctl1;           /* MSCAN + 0x01 */
-	volatile u16 rsrv1;             /* MSCAN + 0x02 */
-	volatile u8  canbtr0;           /* MSCAN + 0x04 */
-	volatile u8  canbtr1;           /* MSCAN + 0x05 */
-	volatile u16 rsrv2;             /* MSCAN + 0x06 */
-	volatile u8  canrflg;           /* MSCAN + 0x08 */
-	volatile u8  canrier;           /* MSCAN + 0x09 */
-	volatile u16 rsrv3;             /* MSCAN + 0x0A */
-	volatile u8  cantflg;           /* MSCAN + 0x0C */
-	volatile u8  cantier;           /* MSCAN + 0x0D */
-	volatile u16 rsrv4;             /* MSCAN + 0x0E */
-	volatile u8  cantarq;           /* MSCAN + 0x10 */
-	volatile u8  cantaak;           /* MSCAN + 0x11 */
-	volatile u16 rsrv5;             /* MSCAN + 0x12 */
-	volatile u8  cantbsel;          /* MSCAN + 0x14 */
-	volatile u8  canidac;           /* MSCAN + 0x15 */
-	volatile u16 rsrv6[3];          /* MSCAN + 0x16 */
-	volatile u8  canrxerr;          /* MSCAN + 0x1C */
-	volatile u8  cantxerr;          /* MSCAN + 0x1D */
-	volatile u16 rsrv7;             /* MSCAN + 0x1E */
-	volatile u8  canidar0;          /* MSCAN + 0x20 */
-	volatile u8  canidar1;          /* MSCAN + 0x21 */
-	volatile u16 rsrv8;             /* MSCAN + 0x22 */
-	volatile u8  canidar2;          /* MSCAN + 0x24 */
-	volatile u8  canidar3;          /* MSCAN + 0x25 */
-	volatile u16 rsrv9;             /* MSCAN + 0x26 */
-	volatile u8  canidmr0;          /* MSCAN + 0x28 */
-	volatile u8  canidmr1;          /* MSCAN + 0x29 */
-	volatile u16 rsrv10;            /* MSCAN + 0x2A */
-	volatile u8  canidmr2;          /* MSCAN + 0x2C */
-	volatile u8  canidmr3;          /* MSCAN + 0x2D */
-	volatile u16 rsrv11;            /* MSCAN + 0x2E */
-	volatile u8  canidar4;          /* MSCAN + 0x30 */
-	volatile u8  canidar5;          /* MSCAN + 0x31 */
-	volatile u16 rsrv12;            /* MSCAN + 0x32 */
-	volatile u8  canidar6;          /* MSCAN + 0x34 */
-	volatile u8  canidar7;          /* MSCAN + 0x35 */
-	volatile u16 rsrv13;            /* MSCAN + 0x36 */
-	volatile u8  canidmr4;          /* MSCAN + 0x38 */
-	volatile u8  canidmr5;          /* MSCAN + 0x39 */
-	volatile u16 rsrv14;            /* MSCAN + 0x3A */
-	volatile u8  canidmr6;          /* MSCAN + 0x3C */
-	volatile u8  canidmr7;          /* MSCAN + 0x3D */
-	volatile u16 rsrv15;            /* MSCAN + 0x3E */
-
-	struct mscan_buffer canrxfg;    /* MSCAN + 0x40 */    /* Foreground receive buffer */
-	struct mscan_buffer cantxfg;    /* MSCAN + 0x60 */    /* Foreground transmit buffer */
-	};
-
-struct mpc5xxx_xlb {
-	volatile u8 reserved[0x40];	/* XLB + 0x00 */
-	volatile u32 config;		/* XLB + 0x40 */
-	volatile u32 version;		/* XLB + 0x44 */
-	volatile u32 status;		/* XLB + 0x48 */
-	volatile u32 int_enable;	/* XLB + 0x4c */
-	volatile u32 addr_capture;	/* XLB + 0x50 */
-	volatile u32 bus_sig_capture;	/* XLB + 0x54 */
-	volatile u32 addr_timeout;	/* XLB + 0x58 */
-	volatile u32 data_timeout;	/* XLB + 0x5c */
-	volatile u32 bus_act_timeout;	/* XLB + 0x60 */
-	volatile u32 master_pri_enable; /* XLB + 0x64 */
-	volatile u32 master_priority;	/* XLB + 0x68 */
-	volatile u32 base_address;	/* XLB + 0x6c */
-	volatile u32 snoop_window;	/* XLB + 0x70 */
-};
-
-struct pci_controller;
-
-/* function prototypes */
-void loadtask(int basetask, int tasks);
-void pci_mpc5xxx_init(struct pci_controller *);
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ASMPPC_MPC5XXX_H */
diff --git a/include/mpc5xxx_sdma.h b/include/mpc5xxx_sdma.h
deleted file mode 100644
index 821ac0ac62..0000000000
--- a/include/mpc5xxx_sdma.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * This file is based on code
- * (C) Copyright Motorola, Inc., 2000
- *
- * odin smartdma header file
- */
-
-#ifndef __MPC5XXX_SDMA_H
-#define __MPC5XXX_SDMA_H
-
-#include <common.h>
-#include <mpc5xxx.h>
-
-/* Task number assignment */
-#define FEC_RECV_TASK_NO            0
-#define FEC_XMIT_TASK_NO            1
-
-/*---------------------------------------------------------------------*/
-
-/* Stuff for Ethernet Tx/Rx tasks                                      */
-
-/*---------------------------------------------------------------------*/
-
-/* Layout of Ethernet controller Parameter SRAM area:
-----------------------------------------------------------------
-0x00: TBD_BASE, base address of TX BD ring
-0x04: TBD_NEXT, address of next TX BD to be processed
-0x08: RBD_BASE, base address of RX BD ring
-0x0C: RBD_NEXT, address of next RX BD to be processed
----------------------------------------------------------------
-ALL PARAMETERS ARE ALL LONGWORDS (FOUR BYTES EACH).
-*/
-
-/* base address of SRAM area to store parameters used by Ethernet tasks */
-#define FEC_PARAM_BASE		(MPC5XXX_SRAM + 0x0800)
-
-/* base address of SRAM area for buffer descriptors */
-#define FEC_BD_BASE		(MPC5XXX_SRAM + 0x0820)
-
-/*---------------------------------------------------------------------*/
-
-/* common shortcuts  used  by driver C code                            */
-
-/*---------------------------------------------------------------------*/
-
-/* Disable SmartDMA task */
-#define SDMA_TASK_DISABLE(tasknum)                     \
-{                                                      \
-    volatile ushort *tcr = (ushort *)(MPC5XXX_SDMA + 0x0000001c + 2 * tasknum); \
-    *tcr = (*tcr) & (~0x8000);                         \
-}
-
-/* Enable SmartDMA task */
-#define SDMA_TASK_ENABLE(tasknum)                      \
-{                                                      \
-    volatile ushort *tcr = (ushort *) (MPC5XXX_SDMA + 0x0000001c + 2 * tasknum); \
-    *tcr = (*tcr)  | 0x8000;                           \
-}
-
-/* Enable interrupt */
-#define SDMA_INT_ENABLE(tasknum)                       \
-{                                                      \
-    struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \
-    sdma->IntMask &= ~(1 << tasknum);                  \
-}
-
-/* Disable interrupt */
-#define SDMA_INT_DISABLE(tasknum)   \
-{                                                      \
-    struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \
-    sdma->IntMask |= (1 << tasknum);                   \
-}
-
-
-/* Clear interrupt pending bits */
-#define SDMA_CLEAR_IEVENT(tasknum)  \
-{                                                      \
-    struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \
-    sdma->IntPend = (1 << tasknum);                    \
-}
-
-/* get interrupt pending bit of a task */
-#define SDMA_GET_PENDINGBIT(tasknum)                   \
-	((*(vu_long *)(MPC5XXX_SDMA + 0x14)) & (1<<(tasknum)))
-
-/* get interrupt mask bit of a task */
-#define SDMA_GET_MASKBIT(tasknum)                      \
-	((*(vu_long *)(MPC5XXX_SDMA + 0x18)) & (1<<(tasknum)))
-
-#endif	/* __MPC5XXX_SDMA_H */
diff --git a/include/netdev.h b/include/netdev.h
index ced761b9ce..c06b90886b 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -57,8 +57,6 @@ int lpc32xx_eth_initialize(bd_t *bis);
 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
 int mcdmafec_initialize(bd_t *bis);
 int mcffec_initialize(bd_t *bis);
-int mpc512x_fec_initialize(bd_t *bis);
-int mpc5xxx_fec_initialize(bd_t *bis);
 int mvgbe_initialize(bd_t *bis);
 int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr);
 int natsemi_initialize(bd_t *bis);
diff --git a/include/post.h b/include/post.h
index 94d5b42d2c..201d7e46b9 100644
--- a/include/post.h
+++ b/include/post.h
@@ -22,14 +22,7 @@
 #define _POST_WORD_ADDR	CONFIG_SYS_POST_WORD_ADDR
 #else
 
-#ifdef CONFIG_MPC5xxx
-#define _POST_WORD_ADDR	(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE)
-
-#elif defined(CONFIG_MPC512X)
-#define _POST_WORD_ADDR \
-	(CONFIG_SYS_SRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-#elif defined(CONFIG_8xx)
+#if defined(CONFIG_8xx)
 #define _POST_WORD_ADDR \
 	(((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + CPM_POST_WORD_ADDR)
 
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
index b317573bff..18783340d9 100644
--- a/include/ppc_asm.tmpl
+++ b/include/ppc_asm.tmpl
@@ -125,11 +125,6 @@
 
 #define PLPRCR	0x00000284
 
-#elif defined(CONFIG_MPC5xxx)
-
-#define HID0_ICE_BITPOS	16
-#define HID0_DCE_BITPOS	17
-
 #endif
 
 #define curptr r2
diff --git a/include/serial.h b/include/serial.h
index 9a5478a8f3..a5b555d14c 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -29,9 +29,8 @@ extern struct serial_device *default_serial_console(void);
 #if	defined(CONFIG_405GP) || \
 	defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
 	defined(CONFIG_405EX) || defined(CONFIG_440) || \
-	defined(CONFIG_MPC5xxx) || \
 	defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
-	defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \
+	defined(CONFIG_MPC86xx) || \
 	defined(CONFIG_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \
 	defined(CONFIG_MICROBLAZE)
 extern struct serial_device serial0_device;
@@ -69,13 +68,6 @@ extern int usbtty_tstc(void);
 
 #endif /* CONFIG_USB_TTY */
 
-#if defined(CONFIG_MPC512X)
-extern struct stdio_dev *open_port(int num, int baudrate);
-extern int close_port(int num);
-extern int write_port(struct stdio_dev *port, char *buf);
-extern int read_port(struct stdio_dev *port, char *buf, int size);
-#endif
-
 struct udevice;
 
 /**
@@ -192,7 +184,6 @@ void marvell_serial_initialize(void);
 void max3100_serial_initialize(void);
 void mcf_serial_initialize(void);
 void ml2_serial_initialize(void);
-void mpc512x_serial_initialize(void);
 void mpc85xx_serial_initialize(void);
 void mpc8xx_serial_initialize(void);
 void mxc_serial_initialize(void);
diff --git a/include/status_led.h b/include/status_led.h
index e377346967..8178e93ebf 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -56,10 +56,6 @@ void status_led_set  (int led, int state);
    * filling this file up with lots of custom board stuff.
    */
 
-#elif defined(CONFIG_V38B)
-
-# define STATUS_LED_ACTIVE	0		/* LED on for bit == 0 */
-
 #elif defined(CONFIG_LED_STATUS_BOARD_SPECIFIC)
 /* led_id_t is unsigned long mask */
 typedef unsigned long led_id_t;
diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h
index 8f3437a208..847b6989a0 100644
--- a/include/usb/ehci-ci.h
+++ b/include/usb/ehci-ci.h
@@ -156,9 +156,6 @@
 #elif defined(CONFIG_MPC85xx)
 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR
 #define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR
-#elif defined(CONFIG_MPC512X)
-#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
-#define CONFIG_SYS_FSL_USB2_ADDR	0
 #elif defined(CONFIG_ARCH_LS1021A)
 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_USB2_ADDR        0
diff --git a/include/watchdog.h b/include/watchdog.h
index e7871e3875..c1e7b7aeb3 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -77,11 +77,6 @@ int init_func_watchdog_reset(void);
 	void reset_8xx_watchdog(volatile immap_t *immr);
 #endif
 
-/* MPC 5xxx */
-#if defined(CONFIG_MPC5xxx) && !defined(__ASSEMBLY__)
-	void reset_5xxx_watchdog(void);
-#endif
-
 /* AMCC 4xx */
 #if defined(CONFIG_4xx) && !defined(__ASSEMBLY__)
 	void reset_4xx_watchdog(void);
diff --git a/post/board/pdm360ng/Makefile b/post/board/pdm360ng/Makefile
deleted file mode 100644
index 9aa96a1f6a..0000000000
--- a/post/board/pdm360ng/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2010 DENX Software Engineering
-# Anatolij Gustschin, agust@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y += coproc_com.o
diff --git a/post/board/pdm360ng/coproc_com.c b/post/board/pdm360ng/coproc_com.c
deleted file mode 100644
index e11b69bdc7..0000000000
--- a/post/board/pdm360ng/coproc_com.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * (C) Copyright 2010 DENX Software Engineering,
- * Anatolij Gustschin, agust@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Co-Processor communication POST
- */
-#include <common.h>
-#include <post.h>
-#include <serial.h>
-
-/*
- * Actually the termination sequence of the coprocessor
- * commands is "\r\n" (CR LF), but here we use a side effect of
- * the putc() routine of the serial driver which checks for LF
- * and sends CR before sending LF. Therefore the termination
- * sequence in the command below is only "\n".
- * "alive" string is the coprocessor response for ping command
- * and not a command, therefore it is terminated with "\r\n".
- */
-char alive[] = "$AL;38\r\n";
-char ping[] = "$PI;2C\n";
-
-int coprocessor_post_test(int flags)
-{
-	struct stdio_dev *cop_port;
-	int ret;
-	char buf[10];
-
-	/* Test IO Coprocessor communication */
-	cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE);
-	if (!cop_port)
-		return -1;
-
-	write_port(cop_port, ping);
-	udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY);
-
-	memset(buf, 0, sizeof(buf));
-	ret = read_port(cop_port, buf, sizeof(buf));
-	close_port(4);
-	if (ret <= 0) {
-		post_log("Error: Can't read IO Coprocessor port.\n");
-		return -1;
-	}
-
-	if (strcmp(buf, alive)) {
-		post_log("Error: IO-Cop. resp.: %s\n", buf);
-		return -1;
-	}
-
-	/* Test WD Coprocessor communication */
-	cop_port = open_port(1, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE);
-	if (!cop_port) {
-		post_log("Error: Can't open WD Coprocessor port.\n");
-		return -1;
-	}
-
-	write_port(cop_port, ping);
-	udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY);
-
-	memset(buf, 0, sizeof(buf));
-	ret = read_port(cop_port, buf, sizeof(buf));
-	close_port(1);
-	if (ret <= 0) {
-		post_log("Error: Can't read WD Coprocessor port.\n");
-		return -1;
-	}
-
-	if (strcmp(buf, alive)) {
-		post_log("Error: WD-Cop. resp.: %s\n", buf);
-		return -1;
-	}
-
-	return 0;
-}
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 46136e6acb..5225819ce6 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -28,7 +28,6 @@ CONFIG_4xx_CONFIG_BLOCKSIZE
 CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR
 CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET
 CONFIG_4xx_DCACHE
-CONFIG_521X
 CONFIG_533MHZ_MODE
 CONFIG_64BIT_PHYS_ADDR
 CONFIG_66
@@ -49,10 +48,6 @@ CONFIG_8xx_GCLK_FREQ
 CONFIG_8xx_OSCLK
 CONFIG_A003399_NOR_WORKAROUND
 CONFIG_A008044_WORKAROUND
-CONFIG_A3M071
-CONFIG_A4M072
-CONFIG_A4M2K
-CONFIG_AC14XX
 CONFIG_ACADIA
 CONFIG_ACX517AKN
 CONFIG_ACX544AKN
@@ -116,8 +111,6 @@ CONFIG_ARCH_USE_BUILTIN_BSWAP
 CONFIG_ARC_MMU_VER
 CONFIG_ARC_SERIAL
 CONFIG_ARC_UART_BASE
-CONFIG_ARIA
-CONFIG_ARIA_FPGA
 CONFIG_ARIES_M28_V10
 CONFIG_ARM926EJS
 CONFIG_ARMADA100
@@ -226,7 +219,6 @@ CONFIG_BCM_SF2_ETH_GMAC
 CONFIG_BD_NUM_CPUS
 CONFIG_BIOSEMU
 CONFIG_BITBANGMII_MULTI
-CONFIG_BKUP_FLASH
 CONFIG_BL1_OFFSET
 CONFIG_BL1_SIZE
 CONFIG_BL2_OFFSET
@@ -239,7 +231,6 @@ CONFIG_BOARDINFO
 CONFIG_BOARDNAME
 CONFIG_BOARDNAME_LOCAL
 CONFIG_BOARD_AXM
-CONFIG_BOARD_BOOTCMD
 CONFIG_BOARD_COMMON
 CONFIG_BOARD_EARLY_INIT_R
 CONFIG_BOARD_ECC_SUPPORT
@@ -248,7 +239,6 @@ CONFIG_BOARD_H2200
 CONFIG_BOARD_IS_OPENRD_BASE
 CONFIG_BOARD_IS_OPENRD_CLIENT
 CONFIG_BOARD_IS_OPENRD_ULTIMATE
-CONFIG_BOARD_MEM_LIMIT
 CONFIG_BOARD_NAME
 CONFIG_BOARD_POSTCLK_INIT
 CONFIG_BOARD_RESET
@@ -333,10 +323,6 @@ CONFIG_BUS_WIDTH
 CONFIG_BZIP2
 CONFIG_CADDY2
 CONFIG_CALXEDA_XGMAC
-CONFIG_CAM5200
-CONFIG_CAM5200_NIOSFLASH
-CONFIG_CANMB
-CONFIG_CAN_DRIVER
 CONFIG_CDP_APPLIANCE_VLAN_TYPE
 CONFIG_CDP_CAPABILITIES
 CONFIG_CDP_DEVICE_ID
@@ -347,7 +333,6 @@ CONFIG_CDP_POWER_CONSUMPTION
 CONFIG_CDP_TRIGGER
 CONFIG_CDP_VERSION
 CONFIG_CFG_DATA_SECTOR
-CONFIG_CFG_FAT
 CONFIG_CFG_USB
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 CONFIG_CF_DSPI
@@ -358,7 +343,6 @@ CONFIG_CF_V3
 CONFIG_CF_V4
 CONFIG_CF_V4E
 CONFIG_CHAIN_BOOT_CMD
-CONFIG_CHARON
 CONFIG_CHIP_SELECTS_PER_CTRL
 CONFIG_CHIP_SELECT_QUAD_CAPABLE
 CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
@@ -374,7 +358,6 @@ CONFIG_CLK_DEBUG
 CONFIG_CLOCKS
 CONFIG_CLOCKS_IN_MHZ
 CONFIG_CLOCK_SYNTHESIZER
-CONFIG_CM5200
 CONFIG_CM922T_XA10
 CONFIG_CMDLINE_EDITING
 CONFIG_CMDLINE_PS_SUPPORT
@@ -542,13 +525,9 @@ CONFIG_DDR_ECC_ENABLE
 CONFIG_DDR_ECC_INIT_VIA_DMA
 CONFIG_DDR_FIXED_SIZE
 CONFIG_DDR_HCLK
-CONFIG_DDR_HYB25D512160BF
 CONFIG_DDR_II
-CONFIG_DDR_K4H511638C
 CONFIG_DDR_LOG_LEVEL
 CONFIG_DDR_MB
-CONFIG_DDR_MT46V16M16
-CONFIG_DDR_MT46V32M16
 CONFIG_DDR_MT47H128M8
 CONFIG_DDR_MT47H32M16
 CONFIG_DDR_MT47H64M16
@@ -587,8 +566,6 @@ CONFIG_DFU_ENV_SETTINGS
 CONFIG_DFU_MTD
 CONFIG_DHCP_MIN_EXT_LEN
 CONFIG_DIALOG_POWER
-CONFIG_DIGSY_MTC
-CONFIG_DIGSY_REV5
 CONFIG_DIMM_SLOTS_PER_CTLR
 CONFIG_DIRECT_NOR_BOOT
 CONFIG_DISABLE_CONSOLE
@@ -818,7 +795,6 @@ CONFIG_EXTRA_ENV_ITB
 CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS
 CONFIG_EXTRA_ENV_SETTINGS
 CONFIG_EXTRA_ENV_SETTINGS_COMMON
-CONFIG_EXTRA_ENV_SETTINGS_DEVEL
 CONFIG_EXTRA_ENV_UNLOCK
 CONFIG_EXTRA_ENV_USBTTY
 CONFIG_EXT_AHB2AHB_BASE
@@ -902,7 +878,6 @@ CONFIG_FLASH_SPANSION_S29WS_N
 CONFIG_FLASH_VERIFY
 CONFIG_FMAN_ENET
 CONFIG_FM_PLAT_CLK_DIV
-CONFIG_FO300
 CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
 CONFIG_FORMIKE
 CONFIG_FPGA_COUNT
@@ -942,10 +917,6 @@ CONFIG_FSL_LBC
 CONFIG_FSL_LINFLEXUART
 CONFIG_FSL_MC9SDZ60
 CONFIG_FSL_MEMAC
-CONFIG_FSL_NFC_CHIPS
-CONFIG_FSL_NFC_SPARE_SIZE
-CONFIG_FSL_NFC_WIDTH
-CONFIG_FSL_NFC_WRITE_SIZE
 CONFIG_FSL_NGPIXIS
 CONFIG_FSL_PCIE_DISABLE_ASPM
 CONFIG_FSL_PCIE_RESET
@@ -1030,7 +1001,6 @@ CONFIG_FTUART010_03_BASE
 CONFIG_FTWDT010_BASE
 CONFIG_FTWDT010_WATCHDOG
 CONFIG_FUNC_ISRAM_ADDR
-CONFIG_FWUPDATE_DEBUG
 CONFIG_FZOTG266HD0A_BASE
 CONFIG_GATEWAYIP
 CONFIG_GCOV_KERNEL
@@ -1285,10 +1255,6 @@ CONFIG_IDE_SWAP_IO
 CONFIG_IDS8313
 CONFIG_IDT8T49N222A
 CONFIG_ID_EEPROM
-CONFIG_IFM_DEFAULT_ENV_NEW
-CONFIG_IFM_DEFAULT_ENV_OLD
-CONFIG_IFM_DEFAULT_ENV_SETTINGS
-CONFIG_IFM_SENSOR_TYPE
 CONFIG_IMA
 CONFIG_IMAGE_FORMAT_LEGACY
 CONFIG_IMX
@@ -1308,7 +1274,6 @@ CONFIG_INI_CASE_INSENSITIVE
 CONFIG_INI_MAX_LINE
 CONFIG_INI_MAX_NAME
 CONFIG_INI_MAX_SECTION
-CONFIG_INKA4X0
 CONFIG_INTEGRITY
 CONFIG_INTEL_ICH6_GPIO
 CONFIG_INTERRUPTS
@@ -1328,7 +1293,6 @@ CONFIG_IPADDR2
 CONFIG_IPAM390_GPIO_BOOTMODE
 CONFIG_IPAM390_GPIO_LED_GREEN
 CONFIG_IPAM390_GPIO_LED_RED
-CONFIG_IPEK01
 CONFIG_IPROC
 CONFIG_IPUV3_CLK
 CONFIG_IP_DEFRAG
@@ -1354,7 +1318,6 @@ CONFIG_JFFS2_PART_SIZE
 CONFIG_JFFS2_SUMMARY
 CONFIG_JRSTARTR_JR0
 CONFIG_JTAG_CONSOLE
-CONFIG_JUPITER
 CONFIG_KASAN
 CONFIG_KATMAI
 CONFIG_KCLK_DIS
@@ -1617,7 +1580,6 @@ CONFIG_MCFTMR
 CONFIG_MCFUART
 CONFIG_MCLK_DIS
 CONFIG_MDIO_TIMEOUT
-CONFIG_MECP5123
 CONFIG_MEMSIZE
 CONFIG_MEMSIZE_IN_BYTES
 CONFIG_MEMSIZE_MASK
@@ -1636,7 +1598,6 @@ CONFIG_MIIM_ADDRESS
 CONFIG_MII_DEFAULT_TSEC
 CONFIG_MII_INIT
 CONFIG_MII_SUPPRESS_PREAMBLE
-CONFIG_MINIFAP
 CONFIG_MIPS_HUGE_TLB_SUPPORT
 CONFIG_MIPS_MT_FPAFF
 CONFIG_MIRQ_EN
@@ -1664,16 +1625,7 @@ CONFIG_MMC_TRACE
 CONFIG_MMU
 CONFIG_MODVERSIONS
 CONFIG_MONITOR_IS_IN_RAM
-CONFIG_MOTIONPRO
 CONFIG_MP
-CONFIG_MPC5121ADS
-CONFIG_MPC5121ADS_REV2
-CONFIG_MPC512x_FEC
-CONFIG_MPC5200
-CONFIG_MPC5200_DDR
-CONFIG_MPC5xxx_FEC
-CONFIG_MPC5xxx_FEC_MII10
-CONFIG_MPC5xxx_FEC_MII100
 CONFIG_MPC823
 CONFIG_MPC8308
 CONFIG_MPC8308RDB
@@ -1723,7 +1675,6 @@ CONFIG_MPC8XX_LCD
 CONFIG_MPC8xxx_DISABLE_BPTR
 CONFIG_MPLL_FREQ
 CONFIG_MPR2
-CONFIG_MPX5200
 CONFIG_MP_CLK_FREQ
 CONFIG_MS7720SE
 CONFIG_MS7722SE
@@ -1755,7 +1706,6 @@ CONFIG_MTD_UBI_DEBUG_PARANOID
 CONFIG_MTD_UBI_GLUEBI
 CONFIG_MTD_UBI_MODULE
 CONFIG_MULTI_CS
-CONFIG_MUNICES
 CONFIG_MUSB_HOST
 CONFIG_MVEBU_MMC
 CONFIG_MVGBE
@@ -1828,7 +1778,6 @@ CONFIG_NAND_KMETER1
 CONFIG_NAND_LPC32XX_MLC
 CONFIG_NAND_LPC32XX_SLC
 CONFIG_NAND_MODE_REG
-CONFIG_NAND_MPC5121_NFC
 CONFIG_NAND_MXC
 CONFIG_NAND_MXC_V1_1
 CONFIG_NAND_NDFC
@@ -1892,7 +1841,6 @@ CONFIG_OF_IDE_FIXUP
 CONFIG_OF_SPI
 CONFIG_OF_SPI_FLASH
 CONFIG_OF_STDOUT_PATH
-CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
 CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
 CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
 CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
@@ -1978,7 +1926,6 @@ CONFIG_PCMCIA_SLOT_B
 CONFIG_PCNET
 CONFIG_PCNET_79C973
 CONFIG_PCNET_79C975
-CONFIG_PDM360NG
 CONFIG_PEN_ADDR_BIG_ENDIAN
 CONFIG_PERIF1_FREQ
 CONFIG_PERIF2_FREQ
@@ -1987,7 +1934,6 @@ CONFIG_PERIF4_FREQ
 CONFIG_PHY1_ADDR
 CONFIG_PHY2_ADDR
 CONFIG_PHY3_ADDR
-CONFIG_PHYCORE_MPC5200B_TINY
 CONFIG_PHYSMEM
 CONFIG_PHY_ADDR
 CONFIG_PHY_BASE_ADR
@@ -2140,9 +2086,6 @@ CONFIG_PS2KBD
 CONFIG_PS2MULT
 CONFIG_PS2MULT_DELAY
 CONFIG_PS2SERIAL
-CONFIG_PSC3_USB
-CONFIG_PSC_CONSOLE
-CONFIG_PSC_CONSOLE2
 CONFIG_PSRAM_SCFG
 CONFIG_PWM
 CONFIG_PWM_IMX
@@ -2265,7 +2208,6 @@ CONFIG_RTC_MC13XXX
 CONFIG_RTC_MC146818
 CONFIG_RTC_MCFRRTC
 CONFIG_RTC_MCP79411
-CONFIG_RTC_MPC5200
 CONFIG_RTC_MPC8xx
 CONFIG_RTC_MV
 CONFIG_RTC_MXS
@@ -2338,7 +2280,6 @@ CONFIG_SDRAM_PPC4xx_IBM_DDR
 CONFIG_SDRAM_PPC4xx_IBM_DDR2
 CONFIG_SDRAM_PPC4xx_IBM_SDRAM
 CONFIG_SDRC
-CONFIG_SDR_MT48LC16M16A2
 CONFIG_SD_BOOT_QSPI
 CONFIG_SECBOOT
 CONFIG_SECURE_BL1_ONLY
@@ -2657,8 +2598,6 @@ CONFIG_STANDALONE_LOAD_ADDR
 CONFIG_STATIC_BOARD_REV
 CONFIG_STATIC_RELA
 CONFIG_STD_DEVICES_SETTINGS
-CONFIG_STK52XX
-CONFIG_STK52XX_REV100
 CONFIG_STM32F4DISCOVERY
 CONFIG_STM32X7_SERIAL
 CONFIG_STM32_FLASH
@@ -2747,10 +2686,6 @@ CONFIG_SYS_APP1_SIZE
 CONFIG_SYS_APP2_BASE
 CONFIG_SYS_APP2_SIZE
 CONFIG_SYS_ARCH_TIMER
-CONFIG_SYS_ARIA_FPGA_BASE
-CONFIG_SYS_ARIA_FPGA_SIZE
-CONFIG_SYS_ARIA_SRAM_BASE
-CONFIG_SYS_ARIA_SRAM_SIZE
 CONFIG_SYS_ARM_CACHE_WRITETHROUGH
 CONFIG_SYS_AT91_CPU_NAME
 CONFIG_SYS_AT91_MAIN_CLOCK
@@ -2759,8 +2694,6 @@ CONFIG_SYS_AT91_PLLB
 CONFIG_SYS_AT91_SLOW_CLOCK
 CONFIG_SYS_ATA_ALT_OFFSET
 CONFIG_SYS_ATA_BASE_ADDR
-CONFIG_SYS_ATA_CS_ON_I2C2
-CONFIG_SYS_ATA_CS_ON_TIMER01
 CONFIG_SYS_ATA_DATA_OFFSET
 CONFIG_SYS_ATA_IDE0_OFFSET
 CONFIG_SYS_ATA_IDE1_OFFSET
@@ -2816,9 +2749,6 @@ CONFIG_SYS_BOOTCOUNT_ADDR
 CONFIG_SYS_BOOTCOUNT_BE
 CONFIG_SYS_BOOTCOUNT_LE
 CONFIG_SYS_BOOTCOUNT_SINGLEWORD
-CONFIG_SYS_BOOTCS_CFG
-CONFIG_SYS_BOOTCS_SIZE
-CONFIG_SYS_BOOTCS_START
 CONFIG_SYS_BOOTFILE
 CONFIG_SYS_BOOTFILE_PREFIX
 CONFIG_SYS_BOOTMAPSZ
@@ -2846,7 +2776,6 @@ CONFIG_SYS_BR6_8M
 CONFIG_SYS_BR6_PRELIM
 CONFIG_SYS_BR7_PRELIM
 CONFIG_SYS_BRGCLK_PRESCALE
-CONFIG_SYS_BRIGHTNESS
 CONFIG_SYS_BUSCLK
 CONFIG_SYS_CACHELINE_SHIFT
 CONFIG_SYS_CACHE_ACR0
@@ -2879,7 +2808,6 @@ CONFIG_SYS_CFI_FLASH_CONFIG_REGS
 CONFIG_SYS_CFI_FLASH_STATUS_POLL
 CONFIG_SYS_CF_BASE
 CONFIG_SYS_CF_INTC_REG1
-CONFIG_SYS_CF_SIZE
 CONFIG_SYS_CH7301_I2C
 CONFIG_SYS_CKEN
 CONFIG_SYS_CLK
@@ -2936,7 +2864,6 @@ CONFIG_SYS_CPRI_CLK
 CONFIG_SYS_CPUSPEED
 CONFIG_SYS_CPU_CLK
 CONFIG_SYS_CS0_BASE
-CONFIG_SYS_CS0_CFG
 CONFIG_SYS_CS0_CTRL
 CONFIG_SYS_CS0_FTIM0
 CONFIG_SYS_CS0_FTIM1
@@ -2944,9 +2871,7 @@ CONFIG_SYS_CS0_FTIM2
 CONFIG_SYS_CS0_FTIM3
 CONFIG_SYS_CS0_MASK
 CONFIG_SYS_CS0_SIZE
-CONFIG_SYS_CS0_START
 CONFIG_SYS_CS1_BASE
-CONFIG_SYS_CS1_CFG
 CONFIG_SYS_CS1_CTRL
 CONFIG_SYS_CS1_FLASH_BASE
 CONFIG_SYS_CS1_FTIM0
@@ -2954,10 +2879,7 @@ CONFIG_SYS_CS1_FTIM1
 CONFIG_SYS_CS1_FTIM2
 CONFIG_SYS_CS1_FTIM3
 CONFIG_SYS_CS1_MASK
-CONFIG_SYS_CS1_SIZE
-CONFIG_SYS_CS1_START
 CONFIG_SYS_CS2_BASE
-CONFIG_SYS_CS2_CFG
 CONFIG_SYS_CS2_CTRL
 CONFIG_SYS_CS2_FLASH_BASE
 CONFIG_SYS_CS2_FTIM0
@@ -2965,10 +2887,7 @@ CONFIG_SYS_CS2_FTIM1
 CONFIG_SYS_CS2_FTIM2
 CONFIG_SYS_CS2_FTIM3
 CONFIG_SYS_CS2_MASK
-CONFIG_SYS_CS2_SIZE
-CONFIG_SYS_CS2_START
 CONFIG_SYS_CS3_BASE
-CONFIG_SYS_CS3_CFG
 CONFIG_SYS_CS3_CTRL
 CONFIG_SYS_CS3_FLASH_BASE
 CONFIG_SYS_CS3_FTIM0
@@ -2976,10 +2895,7 @@ CONFIG_SYS_CS3_FTIM1
 CONFIG_SYS_CS3_FTIM2
 CONFIG_SYS_CS3_FTIM3
 CONFIG_SYS_CS3_MASK
-CONFIG_SYS_CS3_SIZE
-CONFIG_SYS_CS3_START
 CONFIG_SYS_CS4_BASE
-CONFIG_SYS_CS4_CFG
 CONFIG_SYS_CS4_CTRL
 CONFIG_SYS_CS4_FLASH_BASE
 CONFIG_SYS_CS4_FTIM0
@@ -2987,10 +2903,7 @@ CONFIG_SYS_CS4_FTIM1
 CONFIG_SYS_CS4_FTIM2
 CONFIG_SYS_CS4_FTIM3
 CONFIG_SYS_CS4_MASK
-CONFIG_SYS_CS4_SIZE
-CONFIG_SYS_CS4_START
 CONFIG_SYS_CS5_BASE
-CONFIG_SYS_CS5_CFG
 CONFIG_SYS_CS5_CTRL
 CONFIG_SYS_CS5_FLASH_BASE
 CONFIG_SYS_CS5_FTIM0
@@ -2998,28 +2911,20 @@ CONFIG_SYS_CS5_FTIM1
 CONFIG_SYS_CS5_FTIM2
 CONFIG_SYS_CS5_FTIM3
 CONFIG_SYS_CS5_MASK
-CONFIG_SYS_CS5_SIZE
-CONFIG_SYS_CS5_START
 CONFIG_SYS_CS6_BASE
-CONFIG_SYS_CS6_CFG
 CONFIG_SYS_CS6_CTRL
 CONFIG_SYS_CS6_FTIM0
 CONFIG_SYS_CS6_FTIM1
 CONFIG_SYS_CS6_FTIM2
 CONFIG_SYS_CS6_FTIM3
 CONFIG_SYS_CS6_MASK
-CONFIG_SYS_CS6_SIZE
-CONFIG_SYS_CS6_START
 CONFIG_SYS_CS7_BASE
-CONFIG_SYS_CS7_CFG
 CONFIG_SYS_CS7_CTRL
 CONFIG_SYS_CS7_FTIM0
 CONFIG_SYS_CS7_FTIM1
 CONFIG_SYS_CS7_FTIM2
 CONFIG_SYS_CS7_FTIM3
 CONFIG_SYS_CS7_MASK
-CONFIG_SYS_CS7_SIZE
-CONFIG_SYS_CS7_START
 CONFIG_SYS_CSOR0
 CONFIG_SYS_CSOR0_EXT
 CONFIG_SYS_CSOR1
@@ -3056,10 +2961,6 @@ CONFIG_SYS_CSPR6
 CONFIG_SYS_CSPR6_EXT
 CONFIG_SYS_CSPR7
 CONFIG_SYS_CSPR7_EXT
-CONFIG_SYS_CS_ALETIMING
-CONFIG_SYS_CS_BURST
-CONFIG_SYS_CS_DEADCYCLE
-CONFIG_SYS_CS_HOLDCYCLE
 CONFIG_SYS_DA850_CS2CFG
 CONFIG_SYS_DA850_CS3CFG
 CONFIG_SYS_DA850_DDR2_DDRPHYCR
@@ -3148,15 +3049,6 @@ CONFIG_SYS_DDR2_TIMING_1
 CONFIG_SYS_DDR2_TIMING_2
 CONFIG_SYS_DDRCDR
 CONFIG_SYS_DDRCDR_VALUE
-CONFIG_SYS_DDRCMD_EM2
-CONFIG_SYS_DDRCMD_EM3
-CONFIG_SYS_DDRCMD_EN_DLL
-CONFIG_SYS_DDRCMD_NOP
-CONFIG_SYS_DDRCMD_OCD_DEFAULT
-CONFIG_SYS_DDRCMD_OCD_EXIT
-CONFIG_SYS_DDRCMD_PCHG_ALL
-CONFIG_SYS_DDRCMD_RES_DLL
-CONFIG_SYS_DDRCMD_RFSH
 CONFIG_SYS_DDRD
 CONFIG_SYS_DDRTC
 CONFIG_SYS_DDRUA
@@ -3297,7 +3189,6 @@ CONFIG_SYS_DEBUG_SERVER_FW_ADDR
 CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 CONFIG_SYS_DECREMENT_PATTERNS
 CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
-CONFIG_SYS_DEFAULT_MBAR
 CONFIG_SYS_DEFAULT_VIDEO_MODE
 CONFIG_SYS_DEF_EEPROM_ADDR
 CONFIG_SYS_DELAYED_ICACHE
@@ -3311,7 +3202,6 @@ CONFIG_SYS_DIMM_SLOTS_PER_CTLR
 CONFIG_SYS_DIRECT_FLASH_NFS
 CONFIG_SYS_DIRECT_FLASH_TFTP
 CONFIG_SYS_DISCOVER_PHY
-CONFIG_SYS_DISP_CHR_RAM
 CONFIG_SYS_DIU_ADDR
 CONFIG_SYS_DM36x_PINMUX0
 CONFIG_SYS_DM36x_PINMUX1
@@ -3386,9 +3276,6 @@ CONFIG_SYS_EHCI_USB1_ADDR
 CONFIG_SYS_ELBC_BASE
 CONFIG_SYS_ELBC_BASE_PHYS
 CONFIG_SYS_ELO3_DMA3
-CONFIG_SYS_ELPIDA_INIT_DEV_OP
-CONFIG_SYS_ELPIDA_OCD_EXIT
-CONFIG_SYS_ELPIDA_RES_DLL
 CONFIG_SYS_EMAC_TI_CLKDIV
 CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 CONFIG_SYS_ENABLE_PADS_ALL
@@ -3459,7 +3346,6 @@ CONFIG_SYS_FLASH_BASE1
 CONFIG_SYS_FLASH_BASE2
 CONFIG_SYS_FLASH_BASE_1
 CONFIG_SYS_FLASH_BASE_2
-CONFIG_SYS_FLASH_BASE_CS1
 CONFIG_SYS_FLASH_BASE_PHYS
 CONFIG_SYS_FLASH_BASE_PHYS_EARLY
 CONFIG_SYS_FLASH_BASE_PHYS_H
@@ -3988,14 +3874,11 @@ CONFIG_SYS_GPIO_CRAM_ADV
 CONFIG_SYS_GPIO_CRAM_CLK
 CONFIG_SYS_GPIO_CRAM_CRE
 CONFIG_SYS_GPIO_CRAM_WAIT
-CONFIG_SYS_GPIO_DATADIR
-CONFIG_SYS_GPIO_DATAVALUE
 CONFIG_SYS_GPIO_DSPIC_READY
 CONFIG_SYS_GPIO_EEPROM_EXT_WP
 CONFIG_SYS_GPIO_EEPROM_INT_WP
 CONFIG_SYS_GPIO_EEPROM_WP
 CONFIG_SYS_GPIO_EN
-CONFIG_SYS_GPIO_ENABLE
 CONFIG_SYS_GPIO_EREADY
 CONFIG_SYS_GPIO_FLASH_WP
 CONFIG_SYS_GPIO_FUNC
@@ -4013,7 +3896,6 @@ CONFIG_SYS_GPIO_LSB_ENABLE
 CONFIG_SYS_GPIO_M66EN
 CONFIG_SYS_GPIO_MONARCH_N
 CONFIG_SYS_GPIO_ODR
-CONFIG_SYS_GPIO_OPENDRAIN
 CONFIG_SYS_GPIO_OR
 CONFIG_SYS_GPIO_OUT
 CONFIG_SYS_GPIO_PCIE_CLKREQ
@@ -4038,9 +3920,6 @@ CONFIG_SYS_GPSR0_VAL
 CONFIG_SYS_GPSR1_VAL
 CONFIG_SYS_GPSR2_VAL
 CONFIG_SYS_GPSR3_VAL
-CONFIG_SYS_GPS_PORT_CONFIG
-CONFIG_SYS_GPS_PORT_CONFIG_1
-CONFIG_SYS_GPS_PORT_CONFIG_2
 CONFIG_SYS_HALT_BEFOR_RAM_JUMP
 CONFIG_SYS_HELP_CMD_WIDTH
 CONFIG_SYS_HID0_FINAL
@@ -4141,7 +4020,6 @@ CONFIG_SYS_I2C_IHS_SPEED_2_1
 CONFIG_SYS_I2C_IHS_SPEED_3
 CONFIG_SYS_I2C_IHS_SPEED_3_1
 CONFIG_SYS_I2C_INIT_BOARD
-CONFIG_SYS_I2C_IO
 CONFIG_SYS_I2C_KEYBD_ADDR
 CONFIG_SYS_I2C_KONA
 CONFIG_SYS_I2C_LDI_ADDR
@@ -4322,10 +4200,8 @@ CONFIG_SYS_INTSRAM
 CONFIG_SYS_INTSRAMSZ
 CONFIG_SYS_INT_FLASH_BASE
 CONFIG_SYS_INT_FLASH_ENABLE
-CONFIG_SYS_IOCTRL_MUX_DDR
 CONFIG_SYS_IO_BASE
 CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
-CONFIG_SYS_IPBSPEED_133
 CONFIG_SYS_IR_REG_BASE_ADDR
 CONFIG_SYS_ISA_BASE
 CONFIG_SYS_ISA_IO
@@ -4442,8 +4318,6 @@ CONFIG_SYS_LOCAL_CONF_REGS
 CONFIG_SYS_LONGHELP
 CONFIG_SYS_LOW
 CONFIG_SYS_LOWBOOT
-CONFIG_SYS_LOWBOOT16
-CONFIG_SYS_LOWBOOT32
 CONFIG_SYS_LOWMEM_BASE
 CONFIG_SYS_LOW_RES_TIMER
 CONFIG_SYS_LPAE_SDRAM_BASE
@@ -4504,7 +4378,6 @@ CONFIG_SYS_MAX_MTD_BANKS
 CONFIG_SYS_MAX_NAND_CHIPS
 CONFIG_SYS_MAX_NAND_DEVICE
 CONFIG_SYS_MAX_PCI_EPS
-CONFIG_SYS_MAX_RAM_SIZE
 CONFIG_SYS_MB862xx_CCF
 CONFIG_SYS_MB862xx_MMR
 CONFIG_SYS_MBAR
@@ -4529,41 +4402,6 @@ CONFIG_SYS_MCMEM1_VAL
 CONFIG_SYS_MDC1_PIN
 CONFIG_SYS_MDCNFG_VAL
 CONFIG_SYS_MDC_PIN
-CONFIG_SYS_MDDRCGRP_HIPRIO_CFG
-CONFIG_SYS_MDDRCGRP_LUT0_AL
-CONFIG_SYS_MDDRCGRP_LUT0_AU
-CONFIG_SYS_MDDRCGRP_LUT0_ML
-CONFIG_SYS_MDDRCGRP_LUT0_MU
-CONFIG_SYS_MDDRCGRP_LUT1_AL
-CONFIG_SYS_MDDRCGRP_LUT1_AU
-CONFIG_SYS_MDDRCGRP_LUT1_ML
-CONFIG_SYS_MDDRCGRP_LUT1_MU
-CONFIG_SYS_MDDRCGRP_LUT2_AL
-CONFIG_SYS_MDDRCGRP_LUT2_AU
-CONFIG_SYS_MDDRCGRP_LUT2_ML
-CONFIG_SYS_MDDRCGRP_LUT2_MU
-CONFIG_SYS_MDDRCGRP_LUT3_AL
-CONFIG_SYS_MDDRCGRP_LUT3_AU
-CONFIG_SYS_MDDRCGRP_LUT3_ML
-CONFIG_SYS_MDDRCGRP_LUT3_MU
-CONFIG_SYS_MDDRCGRP_LUT4_AL
-CONFIG_SYS_MDDRCGRP_LUT4_AU
-CONFIG_SYS_MDDRCGRP_LUT4_ML
-CONFIG_SYS_MDDRCGRP_LUT4_MU
-CONFIG_SYS_MDDRCGRP_PM_CFG1
-CONFIG_SYS_MDDRCGRP_PM_CFG2
-CONFIG_SYS_MDDRC_SYS_CFG
-CONFIG_SYS_MDDRC_SYS_CFG_ALT1
-CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA
-CONFIG_SYS_MDDRC_SYS_CFG_EN
-CONFIG_SYS_MDDRC_TIME_CFG0
-CONFIG_SYS_MDDRC_TIME_CFG0_ALT1
-CONFIG_SYS_MDDRC_TIME_CFG1
-CONFIG_SYS_MDDRC_TIME_CFG1_ALT1
-CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA
-CONFIG_SYS_MDDRC_TIME_CFG2
-CONFIG_SYS_MDDRC_TIME_CFG2_ALT1
-CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA
 CONFIG_SYS_MDIO1_OFFSET
 CONFIG_SYS_MDIO1_PIN
 CONFIG_SYS_MDIO_BASE_ADDR
@@ -4585,18 +4423,6 @@ CONFIG_SYS_MEM_SIZE
 CONFIG_SYS_MEM_TOP_HIDE
 CONFIG_SYS_MFD
 CONFIG_SYS_MHZ
-CONFIG_SYS_MICRON_BMODE
-CONFIG_SYS_MICRON_BMODE_PARAM
-CONFIG_SYS_MICRON_BMODE_RSTDLL
-CONFIG_SYS_MICRON_EMODE
-CONFIG_SYS_MICRON_EMODE2
-CONFIG_SYS_MICRON_EMODE3
-CONFIG_SYS_MICRON_EMODE_PARAM
-CONFIG_SYS_MICRON_EMR
-CONFIG_SYS_MICRON_EMR2
-CONFIG_SYS_MICRON_EMR3
-CONFIG_SYS_MICRON_EMR_OCD
-CONFIG_SYS_MICRON_INIT_DEV_OP
 CONFIG_SYS_MII_MODE
 CONFIG_SYS_MIPS_CACHE_MODE
 CONFIG_SYS_MIPS_TIMER_FREQ
@@ -4623,10 +4449,6 @@ CONFIG_SYS_MONITOR_BASE_EARLY
 CONFIG_SYS_MONITOR_LEN
 CONFIG_SYS_MONITOR_SEC
 CONFIG_SYS_MOR_VAL
-CONFIG_SYS_MPC512X_CLKIN
-CONFIG_SYS_MPC512x_USB1_ADDR
-CONFIG_SYS_MPC512x_USB1_OFFSET
-CONFIG_SYS_MPC5XXX_CLKIN
 CONFIG_SYS_MPC83xx_DMA_ADDR
 CONFIG_SYS_MPC83xx_DMA_OFFSET
 CONFIG_SYS_MPC83xx_ESDHC_ADDR
@@ -4706,8 +4528,6 @@ CONFIG_SYS_MPC8xxx_DDR_OFFSET
 CONFIG_SYS_MPC8xxx_GUTS_ADDR
 CONFIG_SYS_MPC8xxx_PIC_ADDR
 CONFIG_SYS_MPC92469AC
-CONFIG_SYS_MPEG_BASE
-CONFIG_SYS_MPEG_SIZE
 CONFIG_SYS_MRAM_BASE
 CONFIG_SYS_MRAM_SIZE
 CONFIG_SYS_MRS_OFFS
@@ -5059,7 +4879,6 @@ CONFIG_SYS_PCI2_MMIO_PHYS
 CONFIG_SYS_PCI2_MMIO_SIZE
 CONFIG_SYS_PCI64_MEMORY_BUS
 CONFIG_SYS_PCI9054_IOBASE
-CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
 CONFIG_SYS_PCIE
 CONFIG_SYS_PCIE0_CFGBASE
 CONFIG_SYS_PCIE0_CFGMASK
@@ -5157,7 +4976,6 @@ CONFIG_SYS_PCIE_MMAP_SIZE
 CONFIG_SYS_PCIE_NR_PORTS
 CONFIG_SYS_PCIE_PHYS
 CONFIG_SYS_PCIE_VIRT
-CONFIG_SYS_PCISPEED_66
 CONFIG_SYS_PCI_64BIT
 CONFIG_SYS_PCI_BAR0
 CONFIG_SYS_PCI_BAR1
@@ -5259,10 +5077,7 @@ CONFIG_SYS_PCMCIA_POR4
 CONFIG_SYS_PCMCIA_POR5
 CONFIG_SYS_PCMCIA_POR6
 CONFIG_SYS_PCMCIA_POR7
-CONFIG_SYS_PCMCIA_TIMING
 CONFIG_SYS_PDCNT
-CONFIG_SYS_PDM360NG_COPROC_BAUDRATE
-CONFIG_SYS_PDM360NG_COPROC_READ_DELAY
 CONFIG_SYS_PEHLPAR
 CONFIG_SYS_PEPAR
 CONFIG_SYS_PERIPHERAL_BASE
@@ -5353,10 +5168,6 @@ CONFIG_SYS_PPC_DDR_WIMGE
 CONFIG_SYS_PQSPAR
 CONFIG_SYS_PRELIM_OR_AM
 CONFIG_SYS_PROMPT_HUSH_PS2
-CONFIG_SYS_PSC1
-CONFIG_SYS_PSC3
-CONFIG_SYS_PSC4
-CONFIG_SYS_PSC6
 CONFIG_SYS_PSDPAR
 CONFIG_SYS_PSSR_VAL
 CONFIG_SYS_PTA_PER_CLK
@@ -5538,7 +5349,6 @@ CONFIG_SYS_SDRAM_CL
 CONFIG_SYS_SDRAM_CONF1HB
 CONFIG_SYS_SDRAM_CONF1LL
 CONFIG_SYS_SDRAM_CONFPATHB
-CONFIG_SYS_SDRAM_CS1
 CONFIG_SYS_SDRAM_CTP
 CONFIG_SYS_SDRAM_CTRL
 CONFIG_SYS_SDRAM_DRVSTRENGTH
@@ -5713,8 +5523,6 @@ CONFIG_SYS_TEMP_STACK_OCM
 CONFIG_SYS_TEXT_ADDR
 CONFIG_SYS_TEXT_BASE_NOR
 CONFIG_SYS_TEXT_BASE_SPL
-CONFIG_SYS_TFP410_ADDR
-CONFIG_SYS_TFP410_BUS
 CONFIG_SYS_TIMERBASE
 CONFIG_SYS_TIMER_BASE
 CONFIG_SYS_TIMER_COUNTER
@@ -5870,8 +5678,6 @@ CONFIG_SYS_VCXK_RESET_PORT
 CONFIG_SYS_VGA_RAM_EN
 CONFIG_SYS_VIDEO
 CONFIG_SYS_VIDEO_LOGO_MAX_SIZE
-CONFIG_SYS_VPC3_BASE
-CONFIG_SYS_VPC3_SIZE
 CONFIG_SYS_VSC7385_BASE
 CONFIG_SYS_VSC7385_BASE_PHYS
 CONFIG_SYS_VSC7385_BR_PRELIM
@@ -5895,7 +5701,6 @@ CONFIG_SYS_XHCI_USB2_ADDR
 CONFIG_SYS_XHCI_USB3_ADDR
 CONFIG_SYS_XILINX_SPI_LIST
 CONFIG_SYS_XIMG_LEN
-CONFIG_SYS_XLB_PIPELINING
 CONFIG_SYS_XSVF_DEFAULT_ADDR
 CONFIG_SYS_XWAY_EBU_BOOTCFG
 CONFIG_SYS_ZYNQ_QSPI_WAIT
@@ -5940,15 +5745,10 @@ CONFIG_TI_KEYSTONE_SERDES
 CONFIG_TI_KSNAV
 CONFIG_TI_SPI_MMAP
 CONFIG_TMU_TIMER
-CONFIG_TOTAL5200
 CONFIG_TPL_DRIVERS_MISC_SUPPORT
 CONFIG_TPL_PAD_TO
 CONFIG_TPM_TIS_BASE_ADDRESS
 CONFIG_TPS6586X_POWER
-CONFIG_TQM5200
-CONFIG_TQM5200S
-CONFIG_TQM5200_B
-CONFIG_TQM5200_REV100
 CONFIG_TRACE
 CONFIG_TRACE_BUFFER_SIZE
 CONFIG_TRACE_EARLY
@@ -6063,8 +5863,6 @@ CONFIG_USB_ATMEL_CLK_SEL_UPLL
 CONFIG_USB_BIN_FIXUP
 CONFIG_USB_BOOTING
 CONFIG_USB_CABLE_CHECK
-CONFIG_USB_CLOCK
-CONFIG_USB_CONFIG
 CONFIG_USB_DEVICE
 CONFIG_USB_DEV_BASE
 CONFIG_USB_DEV_PULLUP_GPIO
@@ -6237,7 +6035,6 @@ CONFIG_WATCHDOG_PRESC
 CONFIG_WATCHDOG_RC
 CONFIG_WATCHDOG_TIMEOUT
 CONFIG_WATCHDOG_TIMEOUT_MSECS
-CONFIG_WDOG_GPIO_PIN
 CONFIG_WD_MAX_RATE
 CONFIG_WD_PERIOD
 CONFIG_X600
