From patchwork Wed Jan 19 11:40:06 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baidu Boy X-Patchwork-Id: 79448 X-Patchwork-Delegate: kim.phillips@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id E2C42B7043 for ; Wed, 19 Jan 2011 22:40:35 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8B96D28093; Wed, 19 Jan 2011 12:40:34 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ud27kxH7G+4L; Wed, 19 Jan 2011 12:40:34 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C9C1D28114; Wed, 19 Jan 2011 12:40:32 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 129F728114 for ; Wed, 19 Jan 2011 12:40:31 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BHMujnUTgcvY for ; Wed, 19 Jan 2011 12:40:29 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-qy0-f172.google.com (mail-qy0-f172.google.com [209.85.216.172]) by theia.denx.de (Postfix) with ESMTPS id 0D3BC28122 for ; Wed, 19 Jan 2011 12:40:25 +0100 (CET) Received: by qyk34 with SMTP id 34so470142qyk.3 for ; Wed, 19 Jan 2011 03:40:24 -0800 (PST) Received: by 10.224.60.136 with SMTP id p8mr582186qah.239.1295437224436; Wed, 19 Jan 2011 03:40:24 -0800 (PST) Received: from LENOVOE5CA6843 ([180.109.101.248]) by mx.google.com with ESMTPS id nb15sm4643426qcb.2.2011.01.19.03.40.11 (version=SSLv3 cipher=RC4-MD5); Wed, 19 Jan 2011 03:40:23 -0800 (PST) From: "Leo Liu" To: , , , Date: Wed, 19 Jan 2011 19:40:06 +0800 Message-ID: <000b01cbb7cd$a96d91a0$6401a8c0@LENOVOE5CA6843> MIME-Version: 1.0 X-Mailer: Microsoft Office Outlook 11 Thread-Index: Acu3zZ5wRTymoh2WQIi3Kr3KQUmC5w== X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3350 Subject: [U-Boot] [PATCH V4] mpc83xx:fix pcie configuration space read/write X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller. Signed-off-by: Baidu Boy --- Changes for V2: - Avoid line wrap in the patch Changes for V3 - Add space between ) and { Changes for V4 - Add and use priv_data pointer in pci_controller to save the mpc83xx pcie private data arch/powerpc/cpu/mpc83xx/pcie.c | 20 +++++++++++++++++++- include/pci.h | 2 ++ 2 files changed, 21 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c index 46a706d..ee94a8b 100644 --- a/arch/powerpc/cpu/mpc83xx/pcie.c +++ b/arch/powerpc/cpu/mpc83xx/pcie.c @@ -30,6 +30,21 @@ DECLARE_GLOBAL_DATA_PTR; #define PCIE_MAX_BUSES 2 +/*private structure for mpc83xx pcie hose*/ +static struct mpc83xx_pcie_priv { + u8 index; +} pcie_priv[PCIE_MAX_BUSES] = { + { + /*pcie controller 1*/ + .index = 0, + }, + { + /*pcie controller 2*/ + .index = 1, + }, +}; + + static struct { u32 base; u32 size; @@ -52,7 +67,8 @@ static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev) { int bus = PCI_BUS(dev) - hose->first_busno; immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - pex83xx_t *pex = &immr->pciexp[bus]; + struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data; + pex83xx_t *pex = &immr->pciexp[pcie_priv->index]; struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0]; u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev); u32 dev_base = bus << 24 | devfn << 16; @@ -142,6 +158,8 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base; + hose->priv_data = &pcie_priv[bus]; + pci_set_ops(hose, pcie_read_config_byte, pcie_read_config_word, diff --git a/include/pci.h b/include/pci.h index c456006..8b3bdbb 100644 --- a/include/pci.h +++ b/include/pci.h @@ -420,6 +420,8 @@ struct pci_controller { /* Used by ppc405 autoconfig*/ struct pci_region *pci_fb; int current_busno; + + void *priv_data; }; extern __inline__ void pci_set_ops(struct pci_controller *hose,