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[U-Boot,0/2] spi: cadence_spi_apb: fix using bouncebuf with writeback dcache

Message ID FD897F46D140444CAB8DC80B08F0742B0185AC6AAE@PFDE-MX11.EU.P-F.BIZ
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Series spi: cadence_spi_apb: fix using bouncebuf with writeback dcache | expand

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Simon Goldschmidt Nov. 15, 2017, 2:17 p.m. UTC 
Currently, cadence_spi_apb is broken at least on mach-socfpga:

Commits 57897c13de03ac0136d64641a3eab526c6810387 and
b63b46313ed29e9b0c36b3d6b9407f6eade40c8f added bounce buffer handling to
cadence_qspi_apb. This is the first usage of bounce buffers for non-DMA
transfer. As it turns out, bounce buffers like they were did not work
with writeback data cache.

Since the TI K2G SoC seems to need aligned buffers, I chose to make it
work with bounce buffers by adding a new flag that tells bouncebuf to
not issue dcach commands (instead of reverting the above commits).

To make cadence_qspi_apb work on mach-socfpga, we still need the 'Sync
DT bindings with Linux' patches from Jason Rush, but this patch is one
of the required things we need to get qspi support working again on
mach-socfpga.