From patchwork Mon Jun 12 07:35:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1793778 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Qfk6p1yVZz20QH for ; Mon, 12 Jun 2023 17:37:38 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A034F86166; Mon, 12 Jun 2023 09:37:23 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=tinylab.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id B986D85C2B; Mon, 12 Jun 2023 09:37:20 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H2, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from bg4.exmail.qq.com (bg4.exmail.qq.com [43.154.221.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C538A86140 for ; Mon, 12 Jun 2023 09:37:16 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=tinylab.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=bmeng@tinylab.org X-QQ-mid: bizesmtp77t1686555365tejegjhk Received: from pek-vx-bsp2.wrs.com ( [60.247.85.88]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 12 Jun 2023 15:35:51 +0800 (CST) X-QQ-SSF: 01200000000000E0G000000A0000000 X-QQ-FEAT: rZJGTgY0+YN3JFo6TkNDG7PUedsWE+St0pHjOslccizBtlKnY9eRwtuTyyDlr z6sOsK8RWj59czwCJBSdar/ctcZxP20cz/0kUO2CPOCPqb0BZzSeEAcK4JxrAyvg4lNkml6 lo3/g+xBCrzcX49Alz1YHSl05dOtVmA5x+KFKNv+SfNzpy9+WL3B81xw0KF8k/XKKCdPqAR rlQgdDid6lSmQsOE/a7k3jaDR6CpkEIUpNvBPUXDr7CjlI4cmc9sV2vQVRN+OBPxdUBmby9 xyd5jnOM7arpo7DofpWdum3TPKR+tUufc2l99IWEK8+S6TgyzAYay9B6VtSiwaZGY0gb8Ez F9YkajpzNingS89ZYLKz21qD6aJPvGGVfd0CfwUVfih3pTo0T4= X-QQ-GoodBg: 0 X-BIZMAIL-ID: 11956505564409440654 From: Bin Meng To: u-boot@lists.denx.de Cc: Andre Przywara , Anup Patel , Anup Patel , Atish Patra , Bin Meng , =?utf-8?q?Jonas_Schw=C3=B6bel?= , Kautuk Consul , Leo , Michael Walle , Michal Simek , Nikita Shubin , Palmer Dabbelt , Paul Walmsley , Rick Chen , Sean Anderson , Sergei Antonov , Simon Glass , Stefan Herbrechtsmeier , Svyatoslav Ryhel , Tianrui Wei , William Zhang , Yanhong Wang , Yu Chien Peter Lin Subject: [PATCH 0/3] riscv: Add ACLINT mtimer and mswi devices support Date: Mon, 12 Jun 2023 15:35:47 +0800 Message-Id: <20230612073551.885100-1-bmeng@tinylab.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:tinylab.org:qybglogicsvrgz:qybglogicsvrgz7a-0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This RISC-V ACLINT specification [1] defines a set of memory mapped devices which provide inter-processor interrupts (IPI) and timer functionalities for each HART on a multi-HART RISC-V platform. This seriesl updates U-Boot existing SiFive CLINT driver to handle the ACLINT changes, and is now able to support both CLINT and ACLINT. With this series, U-Boot is able to boot on: - QEMU 'virt' machine with 'aclint=on' - Rocket Chip with ACLINT changes [2] [1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc [2] https://github.com/chipsalliance/rocket-chip/pull/3330 Bin Meng (3): riscv: timer: Update the sifive clint timer driver to support aclint riscv: clint: Update the sifive clint ipi driver to support aclint riscv: Rename SiFive CLINT to RISC-V ALINT MAINTAINERS | 2 +- arch/riscv/Kconfig | 12 ++- arch/riscv/cpu/fu540/Kconfig | 2 +- arch/riscv/cpu/fu740/Kconfig | 2 +- arch/riscv/cpu/generic/Kconfig | 4 +- arch/riscv/cpu/jh7110/Kconfig | 2 +- arch/riscv/include/asm/global_data.h | 4 +- arch/riscv/include/asm/syscon.h | 2 +- arch/riscv/lib/Makefile | 2 +- .../lib/{sifive_clint.c => aclint_ipi.c} | 31 ++++++-- board/openpiton/riscv64/Kconfig | 2 +- board/sipeed/maix/Kconfig | 2 +- drivers/timer/Makefile | 2 +- drivers/timer/riscv_aclint_timer.c | 74 +++++++++++++++++++ drivers/timer/sifive_clint_timer.c | 68 ----------------- include/configs/ae350.h | 2 +- include/configs/qemu-riscv.h | 2 +- include/configs/sifive-unleashed.h | 2 +- include/configs/starfive-visionfive2.h | 1 + 19 files changed, 124 insertions(+), 94 deletions(-) rename arch/riscv/lib/{sifive_clint.c => aclint_ipi.c} (53%) create mode 100644 drivers/timer/riscv_aclint_timer.c delete mode 100644 drivers/timer/sifive_clint_timer.c