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[0/3] Improve AST26x0 DDR4 timing and signal quality

Message ID 20221111073008.16364-1-dylan_hung@aspeedtech.com
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Series Improve AST26x0 DDR4 timing and signal quality | expand

Message

Dylan Hung Nov. 11, 2022, 7:30 a.m. UTC 
This patch series fine-tunes the read & write DQS/DQ timing, CLK/CA
timing and termination (RTT_NOM, RTT_PARK and RTT_WR) for Aspeed AST26x0
SOC to get better signal quality and hence improve the stability.  Also,
a typing error of the DDR-PHY status polling is fixed.

Dylan Hung (3):
  ram: ast2600: Fix incorrect statement of the register polling
  ram: ast2600: Improve ddr4 timing and signal quality
  ram: ast2600: Align the RL and WL setting

 .../include/asm/arch-aspeed/sdram_ast2600.h   |   4 +
 drivers/ram/aspeed/sdram_ast2600.c            | 179 +++++++++++++++---
 2 files changed, 152 insertions(+), 31 deletions(-)