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[118.93.106.206]) by smtp.gmail.com with ESMTPSA id k21sm19968918pfi.28.2021.04.06.21.32.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Apr 2021 21:32:44 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Simon Glass , Andy Shevchenko , Bernhard Messerklinger , Bin Meng , Christian Gmeiner , Heinrich Schuchardt , Ilias Apalodimas , Jaehoon Chung , Jagan Teki , Jagannadha Sutradharudu Teki , Laurentiu Tudor , Matthias Brugger , Nicolas Saenz Julienne , Rayagonda Kokatanur , Stefan Roese , Suneel Garapati , Sylwester Nawrocki , Walter Lozano , Wolfgang Wallner Subject: [PATCH 00/17] misc: Some more misc patches Date: Wed, 7 Apr 2021 16:32:10 +1200 Message-Id: <20210407043228.2268429-1-sjg@chromium.org> X-Mailer: git-send-email 2.31.0.208.g409f899ff0-goog MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Various issues were discovered in getting Chromium OS verified boot running on top of coreboot, booting into U-Boot. Improvements include: - enable serial console if even coreboot doesn't - enable cache always - show the BIOS date since Chromium OS's coreboot doesn't have a version - update docs - allow SPI driver to work without a PCH - fix mtrr command when multi-processing (CONFIG_MP) is disabled - add documentation about the memory map Simon Glass (17): pci: Use const for pci_find_device_id() etc. x86: pci: Allow binding of some devices before relocation x86: Allow coreboot serial driver to guess the UART spi: ich: Don't require the PCH tpm: cr50: Drop unnecessary coral headers x86: Don't set up MTRRs if previously done x86: Update the MP constants to avoid conflicts x86: Do cache set-up by default when booting from coreboot x86: coreboot: Show the BIOS date x86: coral: Allow booting from coreboot x86: Add function comments to cb_sysinfo.h x86: coreboot: Use vendor in the Kconfig x86: coreboot: Enable the cbsysinfo command x86: coreboot: Document the memory map x86: Check ROM exists before building vboot dtoc: Check that a parent is not missing doc: Update documentation for cros-2021.04 release arch/x86/cpu/coreboot/Kconfig | 3 +- arch/x86/cpu/i386/cpu.c | 2 +- arch/x86/dts/chromebook_coral.dts | 2 +- arch/x86/dts/chromebook_samus.dts | 2 +- arch/x86/include/asm/cb_sysinfo.h | 16 ++++++ arch/x86/include/asm/mp.h | 12 +++-- arch/x86/lib/init_helpers.c | 5 +- board/coreboot/coreboot/Kconfig | 12 +++-- board/coreboot/coreboot/coreboot.c | 3 ++ board/google/chromebook_coral/coral.c | 28 ++++++++++ doc/board/coreboot/coreboot.rst | 19 +++++++ doc/chromium/run_vboot.rst | 15 +++--- doc/device-tree-bindings/pci/x86-pci.txt | 7 ++- drivers/pci/pci-uclass.c | 39 ++++++++++++-- drivers/serial/serial_coreboot.c | 68 +++++++++++++++++++++--- drivers/spi/ich.c | 4 +- drivers/tpm/cr50_i2c.c | 2 - include/dt-bindings/pci/pci.h | 12 +++++ include/pci.h | 5 +- include/pci_ids.h | 1 + tools/dtoc/dtb_platdata.py | 9 ++++ tools/dtoc/test/dtoc_test_noparent.dts | 32 +++++++++++ tools/dtoc/test_dtoc.py | 10 ++++ 23 files changed, 264 insertions(+), 44 deletions(-) create mode 100644 include/dt-bindings/pci/pci.h create mode 100644 tools/dtoc/test/dtoc_test_noparent.dts