From patchwork Fri Dec 18 03:28:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siew Chin Lim X-Patchwork-Id: 1418009 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CxvVH6gNgz9sWW for ; Fri, 18 Dec 2020 14:29:11 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 19CDD82BA1; Fri, 18 Dec 2020 04:29:06 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 057E982BEC; Fri, 18 Dec 2020 04:29:04 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-3.2 required=5.0 tests=AC_FROM_MANY_DOTS,BAYES_00, RCVD_IN_DNSWL_MED,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id E43308279A for ; Fri, 18 Dec 2020 04:28:59 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=elly.siew.chin.lim@intel.com IronPort-SDR: U2u1hxa1tPaF1zBCzMYmNcA51MAsNqPNScx/f7Q0Mz/cT5e8bwZeBjo2CYH4VV8vWblsyp7zYW 0WrH0Ob6JT5g== X-IronPort-AV: E=McAfee;i="6000,8403,9838"; a="172806943" X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="172806943" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2020 19:28:58 -0800 IronPort-SDR: JO3JXu0k3EhzJepGAHCGFyz3h7DzAutw08qOLl/2SYM3AYjpBA0pCKcidnFhUcWLDSQJbALn/B FP0n+R3tvJyg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,428,1599548400"; d="scan'208";a="558549250" Received: from pg-iccf0306.altera.com ([10.104.2.59]) by fmsmga006.fm.intel.com with ESMTP; 17 Dec 2020 19:28:55 -0800 From: Siew Chin Lim To: u-boot@lists.denx.de Cc: Marek Vasut , Ley Foon Tan , Chin Liang See , Simon Goldschmidt , Tien Fong Chee , Dalon Westergreen , Simon Glass , Yau Wai Gan , Siew Chin Lim Subject: [v4 00/17] Enable ARM Trusted Firmware for U-Boot Date: Fri, 18 Dec 2020 11:28:36 +0800 Message-Id: <20201218032853.46839-1-elly.siew.chin.lim@intel.com> X-Mailer: git-send-email 2.13.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean This is the 4th version of patchset to enable ARM Trusted Firmware for U-Boot for Intel Stratix10 and Agilex platform. New U-boot flow with ARM Trusted Firmware (ATF) support: SPL (EL3) -> ATF-BL31 (EL3) -> U-Boot Proper (EL2) -> Linux (EL1) SPL loads the u-boot.itb which consist of: 1) u-boot-nodtb.bin (U-Boot Proper image) 2) u-boot.dtb (U-Boot Proper DTB) 3) bl31.bin (ATF-BL31 image) Patch status: Have changes: Patch 7, 8, 9, 16 Other patches unchanged. Detail changelog can find in commit message. v3->v4: -------- Patch 7: - Add secure register access helper functions for SoC 64bits These secure register access functions allow U-Boot proper running at EL2 (non-secure) to access System Manager's secure registers by calling the ATF's PSCI runtime services (EL3/secure). Patch 8: - Call secure register access helper function to set SDMMC's DRVSEL and SMPLSEL. Patch 9: - Call secure register access helper function to setup the PHY interface. patch 16: - Adjust BINMAN sequence in code, sorted by alphabetical order. No change on functionality. History: -------- [v1]: https://patchwork.ozlabs.org/project/uboot/cover/20200817043431.28718-1-chee.hong.ang@intel.com/ [v2]: https://patchwork.ozlabs.org/project/uboot/cover/20201001091614.184612-1-elly.siew.chin.lim@intel.com/ [v3]: https://patchwork.ozlabs.org/project/uboot/cover/20201015122955.10259-1-elly.siew.chin.lim@intel.com/ These patchsets have dependency on: arm: socfpga: soc64: Add timeout waiting for NOC idle ACK https://lists.denx.de/pipermail/u-boot/2020-August/423029.html Rename Stratix10 FPGA driver and support Agilex https://lists.denx.de/pipermail/u-boot/2020-August/422798.html SoCFPGA mailbox driver fixes and enhancements https://lists.denx.de/pipermail/u-boot/2020-August/423140.html arm: socfpga: soc64: Initialize timer in SPL only https://lists.denx.de/pipermail/u-boot/2020-July/419692.html arm: socfpga: soc64: Remove PHY interface setup from misc arch init https://lists.denx.de/pipermail/u-boot/2020-July/419690.html Enable sysreset support for SoCFPGA SoC64 platforms https://lists.denx.de/pipermail/u-boot/2020-August/422509.html arm: socfpga: soc64: Disable CONFIG_PSCI_RESET https://lists.denx.de/pipermail/u-boot/2020-August/423373.html Chee Hong Ang (14): arm: socfpga: Add function for checking description from FIT image arm: socfpga: soc64: Load FIT image with ATF support arm: socfpga: soc64: Override 'lowlevel_init' to support ATF arm: socfpga: Disable "spin-table" method for booting Linux arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits) arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services mmc: dwmmc: socfpga: Add ATF support for MMC driver net: designware: socfpga: Add ATF support for MAC driver arm: socfpga: soc64: Add ATF support for Reset Manager driver arm: socfpga: soc64: Add ATF support for FPGA reconfig driver arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold() arm: socfpga: soc64: SSBL shall not setup stack on OCRAM arm: socfpga: soc64: Skip handoff data access in SSBL configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support Siew Chin Lim (3): arm: socfpga: Add secure register access helper functions for SoC 64bits arm: socfpga: dts: soc64: Add binman node of FIT image with ATF support arm: socfpga: soc64: Enable FIT image generation using binman Makefile | 7 + arch/arm/dts/socfpga_agilex-u-boot.dtsi | 4 +- arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 120 +++++ arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 8 + arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 4 +- arch/arm/mach-socfpga/Kconfig | 4 +- arch/arm/mach-socfpga/Makefile | 5 + arch/arm/mach-socfpga/board.c | 12 +- .../mach-socfpga/include/mach/secure_reg_helper.h | 19 + arch/arm/mach-socfpga/include/mach/smc_api.h | 13 + arch/arm/mach-socfpga/lowlevel_init_soc64.S | 76 +++ arch/arm/mach-socfpga/mailbox_s10.c | 5 + arch/arm/mach-socfpga/reset_manager_s10.c | 13 + arch/arm/mach-socfpga/secure_reg_helper.c | 73 +++ arch/arm/mach-socfpga/smc_api.c | 56 ++ arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 +- configs/socfpga_agilex_atf_defconfig | 72 +++ configs/socfpga_stratix10_atf_defconfig | 74 +++ drivers/fpga/intel_sdm_mb.c | 139 +++++ drivers/mmc/socfpga_dw_mmc.c | 8 + drivers/net/dwmac_socfpga.c | 34 +- include/configs/socfpga_soc64_common.h | 24 +- include/linux/intel-smc.h | 573 +++++++++++++++++++++ 23 files changed, 1333 insertions(+), 13 deletions(-) create mode 100644 arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_stratix10-u-boot.dtsi create mode 100644 arch/arm/mach-socfpga/include/mach/secure_reg_helper.h create mode 100644 arch/arm/mach-socfpga/include/mach/smc_api.h create mode 100644 arch/arm/mach-socfpga/lowlevel_init_soc64.S create mode 100644 arch/arm/mach-socfpga/secure_reg_helper.c create mode 100644 arch/arm/mach-socfpga/smc_api.c create mode 100644 configs/socfpga_agilex_atf_defconfig create mode 100644 configs/socfpga_stratix10_atf_defconfig create mode 100644 include/linux/intel-smc.h