From patchwork Fri Sep 27 04:43:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Raghavendra, Vignesh" X-Patchwork-Id: 1168230 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="sqa2ghxy"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46ffLW3v63z9sPK for ; Fri, 27 Sep 2019 14:43:13 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 09C7DC21DFB; Fri, 27 Sep 2019 04:43:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 69D26C21C29; Fri, 27 Sep 2019 04:43:03 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 80BABC21C50; Fri, 27 Sep 2019 04:43:01 +0000 (UTC) Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lists.denx.de (Postfix) with ESMTPS id 03EE3C21BE5 for ; Fri, 27 Sep 2019 04:43:00 +0000 (UTC) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8R4gvFR129268; Thu, 26 Sep 2019 23:42:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1569559377; bh=Oztq5z+7vyLFzK97S0yqXiGESt0RNYJoJ3vq7zL+4JQ=; h=From:To:CC:Subject:Date; b=sqa2ghxyc8rE86JrEc5nH7KjYmOUMoxynPkuE8/O1X4o9X5xmttBxqnFo6izeiM9Y GnANDlogWfhXTdYbElTrJtxjecbd06mPzVCpxFqMUWTk07HpIHNLChCXPLbqXLPr6M boeod7vJ04AYoqciVZwtKeQO/QS0LOpigMsc3eu0= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8R4gvkb112501; Thu, 26 Sep 2019 23:42:57 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 26 Sep 2019 23:42:50 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 26 Sep 2019 23:42:50 -0500 Received: from a0132425.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8R4gsOV092411; Thu, 26 Sep 2019 23:42:55 -0500 From: Vignesh Raghavendra To: Jagan Teki , Eugeniy Paltsev , Simon Goldschmidt Date: Fri, 27 Sep 2019 10:13:26 +0530 Message-ID: <20190927044329.21145-1-vigneshr@ti.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de, Tom Rini Subject: [U-Boot] [PATCH RFT v2 0/3] spi-nor: spi-nor-ids: Fix 4 Byte addressing X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" n25q variants do not support stateless 4 byte addressing opcodes by default, therefore first patch disables this flag for those parts. Second patch adds entries for mt25q variants which are similar to n25q but supports stateless 4 byte opcodes. Third patch adds USE_FSR flag for mt25qu512a as flash supports flag registers Tested on mt25qu512a variant Simon, Euginey, Could you test this patch series on your boards as well? Changes since v1: Rename newer variants as mt25* Add a patch to enable flag register parsing for mt25qu512a Vignesh Raghavendra (3): spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256* spi-nor: spi-nor-ids: Add entries for mt25q variants spi-nor: spi-nor-ids: Add USE_FSR flag for mt25qu512a entry drivers/mtd/spi/spi-nor-ids.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-)