From patchwork Mon Jun 3 13:22:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sekhar Nori X-Patchwork-Id: 1109266 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="vxYwDE1B"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45HbNw40f9z9s1c for ; Mon, 3 Jun 2019 23:24:00 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 0381CC21DD3; Mon, 3 Jun 2019 13:23:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 17653C21D74; Mon, 3 Jun 2019 13:23:08 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id EB303C21BE5; Mon, 3 Jun 2019 13:23:05 +0000 (UTC) Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lists.denx.de (Postfix) with ESMTPS id 5EE83C21C29 for ; Mon, 3 Jun 2019 13:23:05 +0000 (UTC) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x53DMu31002485; Mon, 3 Jun 2019 08:22:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1559568176; bh=2U2n4Xm+EK96ZXRS5myLfX4k7YxQQ8xWf75evqNK/c8=; h=From:To:CC:Subject:Date; b=vxYwDE1BmnNR2Eq9xAcrI5cbOfLAUbLUSiGPJ459GEGf2v5C3g5rD5OHSxItGWEn7 3GUpb/7kJ/0Fb4jhnAQ+QnluTi0/8BNEcN1hiTRm4XHGHCBl7c0ElvkHOmvo/pAnhE PEI6bFYDflOAu9sme7Z2GgIS3uN6x5J14usFe6Bk= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x53DMuJC025730 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 3 Jun 2019 08:22:56 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 3 Jun 2019 08:22:55 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Mon, 3 Jun 2019 08:22:55 -0500 Received: from psplinux063.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x53DMrrr100266; Mon, 3 Jun 2019 08:22:54 -0500 From: Sekhar Nori To: Tom Rini , Lokesh Vutla , Simon Glass Date: Mon, 3 Jun 2019 18:52:45 +0530 Message-ID: <20190603132252.14012-1-nsekhar@ti.com> X-Mailer: git-send-email 2.16.2 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: U-Boot Mailing List Subject: [U-Boot] [PATCH v2 0/7] Add PCIe root complex support for AM654x SoC X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Hi, This patch series adds PCIe root complex support for AM654x SoC. The device-tree files are based on bindings accepted in linux. See files Documentation/devicetree/bindings/phy/ti,phy-am654-serdes.txt and Documentation/devicetree/bindings/pci/pci-keystone.txt in latest mainline master. I have not posted the actual board-specific device-tree bits yet. The reason is that PCIe slot is on a daughter card on the AM65x EVM. I want to see how we can support that as an overlay in U-Boot. That needs some more attention. Meanwhile I have tested this using a patch that simply enables PCIe in the baseboard device-tree file itself. v2: - add unit tests for new clock and dm APIs introduced - add Lokesh's Reviewed-by: for patches #1 and #2 Sekhar Nori (7): clk: add support for clk_is_match() dm: core: add support for getting register address and size pcie: ti: add driver for AM65x PCIe RC phy: add support for AM654x SERDES configs: am65x_evm_a53: enable PCIe support arm: dts: k3-am65: add support for PCIe and SERDES configs: am65x_evm_a53: enable support for PCIe ethernet cards arch/arm/dts/k3-am65-main.dtsi | 108 +++++ arch/arm/dts/k3-am65.dtsi | 1 + configs/am65x_evm_a53_defconfig | 9 + drivers/clk/clk-uclass.c | 13 + drivers/core/fdtaddr.c | 17 + drivers/core/read.c | 20 + drivers/pci/Kconfig | 6 + drivers/pci/Makefile | 1 + drivers/pci/pcie_dw_ti.c | 725 +++++++++++++++++++++++++++++ drivers/phy/Kconfig | 9 + drivers/phy/Makefile | 1 + drivers/phy/phy-ti-am654.c | 411 ++++++++++++++++ include/clk.h | 13 + include/dm/fdtaddr.h | 18 + include/dm/read.h | 41 ++ include/dt-bindings/phy/phy-am654-serdes.h | 13 + test/dm/clk.c | 1 + test/dm/test-fdt.c | 16 +- 18 files changed, 1419 insertions(+), 4 deletions(-) create mode 100644 drivers/pci/pcie_dw_ti.c create mode 100644 drivers/phy/phy-ti-am654.c create mode 100644 include/dt-bindings/phy/phy-am654-serdes.h