From patchwork Thu May 9 01:24:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andes X-Patchwork-Id: 1097298 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44zwqY541sz9sBV for ; Thu, 9 May 2019 11:34:17 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 5C5D8C21E0D; Thu, 9 May 2019 01:32:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=RDNS_DYNAMIC autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D8417C21EBD; Thu, 9 May 2019 01:31:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 93E1EC21EF0; Thu, 9 May 2019 01:31:12 +0000 (UTC) Received: from ATCSQR.andestech.com (59-120-53-16.HINET-IP.hinet.net [59.120.53.16]) by lists.denx.de (Postfix) with ESMTPS id 88B5AC21DF3 for ; Thu, 9 May 2019 01:29:45 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id x491PR4V040668; Thu, 9 May 2019 09:25:27 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.15.117) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Thu, 9 May 2019 09:29:16 +0800 From: Andes To: Date: Thu, 9 May 2019 09:24:53 +0800 Message-ID: <20190509012459.8100-1-uboot@andestech.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-Originating-IP: [10.0.15.117] X-DNSRBL: X-MAIL: ATCSQR.andestech.com x491PR4V040668 Cc: rickchen36@gmail.com, greentime@andestech.com, palmer@sifive.com Subject: [U-Boot] [PATCH v5 0/6] AE350 support SMP boot from flash X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Rick Chen In current RISC-V SMP flow, AE350 will encounter the the write failure problem since hart_lottery and available_harts_lock was not in ram address but in flash address when booing from flash. This patch can help to fix the failure problem when AE350 was booting from flash by disabling this two features. Changes in v5: - New patch [PATCH v5 6/6] riscv: configs: add ae350_rv[32|64]_xip_defconfig to MAINTAINERS It will fix Travis failure item : https://travis-ci.org/rickchen36/u-boot-riscv/jobs/529605196 Changes in v4: - Use CONFIG_OF_SEPARATE instead of CONFIG_OF_BOARD in ae350_rv32_xip_defconfig and ae350_rv64_xip_defconfig. - Remove prior_stage_fdt_address in board_fdt_blob_setup. - Modify CONFIG_SYS_FDT_BASE as flash address. Changes in v3: - Modify CONFIG_XIP descriptions - Use #ifdef CONFIG_OF_PRIOR_STAGE to replace # if CONFIG_IS_ENABLED(OF_PRIOR_STAGE) - Recovery some blank lines - Add CONFIG_SF_DEFAULT_MODE=0x0 in ae350_rv32_xip_defconfig and ae350_rv64_xip_defconfig - #ifdef CONFIG_OF_PRIOR_STAGE shall also surround SREG s1, 0(t0) - Modify CONFIG_SYS_FDT_BASE from 0x000f0000 as 0x800f0000 in ax25-ae350.h Changes in v2: - Fix some typos - Also surround the declaration of prior_stage_fdt_address in arch/riscv/cpu/cpu.c with OF_PRIOR_STAGE - Use CONFIP_XIP to replace CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS Rick Chen (6): riscv: Introduce CONFIG_XIP to support booting from flash riscv: configs: Support AE350 SMP booting from flash flow riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled riscv: configs: AE350 will use CONFIG_OF_PRIOR_STAGE when boots from ram riscv: configs: AE350 will use CONFIG_OF_SEPARATE when boots from flash riscv: configs: add ae350_rv[32|64]_xip_defconfig to MAINTAINERS arch/riscv/Kconfig | 7 ++++++ arch/riscv/cpu/cpu.c | 4 ++++ arch/riscv/cpu/start.S | 8 +++++++ arch/riscv/include/asm/global_data.h | 2 ++ arch/riscv/lib/asm-offsets.c | 2 ++ arch/riscv/lib/smp.c | 2 ++ board/AndesTech/ax25-ae350/MAINTAINERS | 2 ++ board/AndesTech/ax25-ae350/ax25-ae350.c | 4 ---- configs/ae350_rv32_defconfig | 2 +- configs/ae350_rv32_xip_defconfig | 37 ++++++++++++++++++++++++++++++++ configs/ae350_rv64_defconfig | 2 +- configs/ae350_rv64_xip_defconfig | 38 +++++++++++++++++++++++++++++++++ include/configs/ax25-ae350.h | 2 +- 13 files changed, 105 insertions(+), 7 deletions(-) create mode 100644 configs/ae350_rv32_xip_defconfig create mode 100644 configs/ae350_rv64_xip_defconfig