Message ID | 20190325073520.452-1-uboot@andestech.com |
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Headers | show
Return-Path: <u-boot-bounces@lists.denx.de> X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44SR3r2rlkz9sSd for <incoming@patchwork.ozlabs.org>; Mon, 25 Mar 2019 18:39:36 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id DEE1BC21F0B; Mon, 25 Mar 2019 07:39:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=RDNS_DYNAMIC autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E4C8CC21E4E; Mon, 25 Mar 2019 07:39:27 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A97FFC21D72; Mon, 25 Mar 2019 07:39:26 +0000 (UTC) Received: from ATCSQR.andestech.com (59-120-53-16.HINET-IP.hinet.net [59.120.53.16]) by lists.denx.de (Postfix) with ESMTPS id 93781C21D72 for <u-boot@lists.denx.de>; Mon, 25 Mar 2019 07:39:25 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id x2P7cf3N053842; Mon, 25 Mar 2019 15:38:41 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.15.117) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Mon, 25 Mar 2019 15:39:00 +0800 From: Andes <uboot@andestech.com> To: <u-boot@lists.denx.de> Date: Mon, 25 Mar 2019 15:35:13 +0800 Message-ID: <20190325073520.452-1-uboot@andestech.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-Originating-IP: [10.0.15.117] X-DNSRBL: X-MAIL: ATCSQR.andestech.com x2P7cf3N053842 Cc: rickchen36@gmail.com, greentime@andestech.com, palmer@sifive.com Subject: [U-Boot] [PATCH v2 0/7] AE350 SMP support RISC-V X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion <u-boot.lists.denx.de> List-Unsubscribe: <https://lists.denx.de/options/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=unsubscribe> List-Archive: <http://lists.denx.de/pipermail/u-boot/> List-Post: <mailto:u-boot@lists.denx.de> List-Help: <mailto:u-boot-request@lists.denx.de?subject=help> List-Subscribe: <https://lists.denx.de/listinfo/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=subscribe> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de> |
Series |
AE350 SMP support RISC-V
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From: Rick Chen <rick@andestech.com> Changes in v2: - Drop patch1 and replace by simple-bus driver - Rename nds_plic as andes_plic - Move initialize plic to PLIC_BASE_GET() and called automatically - Rename nds_plmt as andes_plmt - Recovery dts isa string Rick Chen (7): riscv: Add a SYSCON driver for Andestech's PLIC riscv: Add a SYSCON driver for Andestech's PLMT riscv: ae350: disable ATCPIT100 timer riscv: ax25: Add platform-specific Kconfig options riscv: ax25: Andes specific cache shall only support in M-mode riscv: dts: ae350 support SMP riscv: ae350: enable SMP arch/riscv/Kconfig | 18 ++++++ arch/riscv/cpu/ax25/Kconfig | 7 +++ arch/riscv/dts/ae350_32.dts | 81 ++++++++++++++++++------- arch/riscv/dts/ae350_64.dts | 47 +++++++++++++-- arch/riscv/include/asm/global_data.h | 6 ++ arch/riscv/include/asm/syscon.h | 3 +- arch/riscv/lib/Makefile | 2 + arch/riscv/lib/andes_plic.c | 111 +++++++++++++++++++++++++++++++++++ arch/riscv/lib/andes_plmt.c | 53 +++++++++++++++++ board/AndesTech/ax25-ae350/Kconfig | 1 + configs/ae350_rv32_defconfig | 1 - configs/ae350_rv64_defconfig | 1 - 12 files changed, 301 insertions(+), 30 deletions(-) create mode 100644 arch/riscv/lib/andes_plic.c create mode 100644 arch/riscv/lib/andes_plmt.c