From patchwork Wed Jan 30 03:58:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1033236 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="LkdRHgQr"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43q8lM5Djlz9sBb for ; Wed, 30 Jan 2019 14:59:55 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id A9D1DC21DA6; Wed, 30 Jan 2019 03:59:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 196B4C21C2C; Wed, 30 Jan 2019 03:59:47 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 124DAC21C2C; Wed, 30 Jan 2019 03:59:44 +0000 (UTC) Received: from mail-io1-f71.google.com (mail-io1-f71.google.com [209.85.166.71]) by lists.denx.de (Postfix) with ESMTPS id B1F83C21C27 for ; Wed, 30 Jan 2019 03:59:42 +0000 (UTC) Received: by mail-io1-f71.google.com with SMTP id p4so18276126iod.17 for ; Tue, 29 Jan 2019 19:59:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=date:message-id:mime-version:subject:from:to:cc; bh=yvDDgWZdliRMbPvMSBg+MqwA4/9xXwSO+4rGNVn921E=; b=LkdRHgQr17fQYL7o54gj+zvbkOHLl4kUr5wqjG+uD+EPgH/W5yztoycJD+IycSMcKn 1nG9onLARYjVc8Aq3wyodRvxNHMzY7Dh6l8ucpnvVKu6uIJnvjoIWYszdhhZATH40+sl IyDpbw1xUB9jXrkpToHpNC+KadNOUprSZBMO4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:message-id:mime-version:subject:from:to:cc; bh=yvDDgWZdliRMbPvMSBg+MqwA4/9xXwSO+4rGNVn921E=; b=MflGHNSM3lt/6Hj3W79V+szqH+bjnrMdVx0Xt4l01Dx1rehUWvE4vQ4wsWcGVG7XZF ZYRRvUmJe57utZckf3h0mpl+23dYjQ9A1cUOtN/Vs1Rb1zmhYtyhfhINQ8w21GhE+Q4Z tU9RiBZD3cfMmChxMqwXFgRtUR6qSgozzA4feb7qe0edjyPPk7nLZ7kdlfGX5PP5jn5z EGZoFP2o5nGc7cJOXvPX3oMCRKUqmMpBZ+rAK3m1aplhlcD62678GcI2RjkPfq0JzbIs oCxSbjDzOg0QxhgCvD6bLl/mtQ2Z5Q7KrZSWi8uuX1F4RzfNPcaNhe07YeTCszpqycLI kXhw== X-Gm-Message-State: AHQUAua4OOhKFqL3gAkQXo6xYpIRywe5A63zCfRb5lKghcl9mQucYByp i82NWJEKk+wBivv73fSlAT9VZkLQx4slwMQY X-Google-Smtp-Source: AHgI3IZ5A4P4UX+AeTU5r7HiOhPiC9WvabG0lLpgWlpjV6HvHeLOBwOwb9PjPY7njfJjw7TayGIC+FXa1VmDhArK X-Received: by 2002:a24:2951:: with SMTP id p78mr4765259itp.28.1548820780308; Tue, 29 Jan 2019 19:59:40 -0800 (PST) Date: Tue, 29 Jan 2019 20:58:55 -0700 Message-Id: <20190130035935.235565-1-sjg@chromium.org> Mime-Version: 1.0 X-Mailer: git-send-email 2.20.1.495.gaa96b0ce6b-goog From: Simon Glass To: U-Boot Mailing List Cc: Pavel Herrmann Subject: [U-Boot] [PATCH 00/40] x86: Add support for booting from TPL X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" At present SPL is used on 64-bit platforms, to allow SPL to be built as a 32-bit program and U-Boot proper to be built as 64-bit. However it is useful to be able to use SPL on any x86 platform, where U-Boot needs to be updated in the field. Then SPL can select which U-Boot to run (A or B) and most of the code can be updated. Similarly, using TPL allows both SPL and U-Boot to be updated. This is the best approach, since it means that all of U-Boot proper as well as SPL (in particular SDRAM init) can be updated in the field. This provides for the smallest possible amount of read-only (non-updateable) code: just the TPL code. This series contains a number of changes to allow x86 boards to use TPL, SPL and U-Boot proper. As a test, it is enabled for samus with a new chromebook_samus_tpl board. Simon Glass (40): binman: Don't generate an error in 'text' entry constructor binman: Don't show image-skip message by default binman: Add a missing comment in Entry_vblock dm: core: Fix translate condition in ofnode_get_addr_size() cros_ec: Use a hyphen in the uclass name spl: Allow sandbox to build a device-tree file RFC: binman: Allow sections to have an offset x86: start64: Fix copyright message x86: mp_init: Use proper error numbers x86: Add a way to reinit the cpu x86: dts: Add device-tree labels for rtc and reset x86: Update a stale comment about ifdtool x86: Support SPL and TPL x86: Support booting with TPL x86: Add a handoff header file x86: broadwell: Improve SDRAM debugging output x86: broadwell: Allow SDRAM init from SPL x86: Move init of debug UART to cpu.c x86: broadwell: Split CPU init x86: Add support for starting from SPL/TPL x86: Allow 16-bit init to be in TPL x86: broadwell: Allow booting from SPL x86: broadwell: Select refcode and CPU code for SPL x86: Add common Intel code for SPL x86: Support saving MRC data from SPL x86: Add a simple TPL implementations x86: mrccache: Add more debugging x86: Add a sysreset driver for the Intel PCH x86: Support TPL in Intel common code x86: Don't set up MTRRs in SPL x86: Don't generate a bootstage report in SPL x86: Support PCI VGA ROM when TPL is used x86: sysreset: Implement the get_last() method x86: Add documention on the samus flashmap x86: samus: Update device tree for SPL x86: samus: Update device tree for verified boot x86: Update device tree for TPL x86: Update device tree for Chromium OS verified boot x86: Fix device-tree indentation x86: samus: Add a target to boot through TPL Makefile | 1 + arch/Kconfig | 30 + arch/x86/Kconfig | 10 +- arch/x86/Makefile | 16 +- arch/x86/cpu/Makefile | 15 +- arch/x86/cpu/broadwell/Kconfig | 1 + arch/x86/cpu/broadwell/Makefile | 23 +- arch/x86/cpu/broadwell/cpu.c | 676 +-------------------- arch/x86/cpu/broadwell/cpu_from_spl.c | 63 ++ arch/x86/cpu/broadwell/cpu_full.c | 694 ++++++++++++++++++++++ arch/x86/cpu/broadwell/northbridge.c | 93 +++ arch/x86/cpu/broadwell/sdram.c | 136 +---- arch/x86/cpu/i386/cpu.c | 113 ++-- arch/x86/cpu/intel_common/Makefile | 17 +- arch/x86/cpu/intel_common/car.S | 2 +- arch/x86/cpu/intel_common/cpu_from_spl.c | 27 + arch/x86/cpu/mp_init.c | 10 +- arch/x86/cpu/start64.S | 2 +- arch/x86/cpu/start_from_spl.S | 71 +++ arch/x86/cpu/start_from_tpl.S | 50 ++ arch/x86/cpu/u-boot-spl.lds | 2 +- arch/x86/cpu/x86_64/cpu.c | 5 + arch/x86/dts/chromebook_samus.dts | 60 +- arch/x86/dts/reset.dtsi | 2 +- arch/x86/dts/rtc.dtsi | 2 +- arch/x86/dts/u-boot.dtsi | 154 +++-- arch/x86/include/asm/handoff.h | 15 + arch/x86/include/asm/mrccache.h | 11 + arch/x86/include/asm/spl.h | 17 +- arch/x86/include/asm/u-boot-x86.h | 20 + arch/x86/lib/Makefile | 9 +- arch/x86/lib/bootm.c | 2 +- arch/x86/lib/init_helpers.c | 5 +- arch/x86/lib/mrccache.c | 52 +- arch/x86/lib/spl.c | 44 +- arch/x86/lib/tpl.c | 118 ++++ board/google/Kconfig | 8 + board/google/chromebook_samus/Kconfig | 14 +- board/google/chromebook_samus/MAINTAINERS | 7 + configs/chromebook_samus_tpl_defconfig | 80 +++ doc/README.x86 | 14 + drivers/core/ofnode.c | 2 +- drivers/misc/cros_ec.c | 2 +- drivers/pci/pci_rom.c | 2 +- drivers/sysreset/Kconfig | 9 + drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_intel_pch.c | 125 ++++ drivers/sysreset/sysreset_x86.c | 6 + include/configs/chromebook_link.h | 3 - include/configs/chromebook_samus.h | 3 + include/configs/qemu-x86.h | 3 - scripts/Makefile.spl | 24 +- tools/binman/bsection.py | 5 +- tools/binman/control.py | 4 +- tools/binman/etype/section.py | 3 +- tools/binman/etype/text.py | 4 +- tools/binman/etype/vblock.py | 1 + 57 files changed, 1933 insertions(+), 955 deletions(-) create mode 100644 arch/x86/cpu/broadwell/cpu_from_spl.c create mode 100644 arch/x86/cpu/broadwell/cpu_full.c create mode 100644 arch/x86/cpu/intel_common/cpu_from_spl.c create mode 100644 arch/x86/cpu/start_from_spl.S create mode 100644 arch/x86/cpu/start_from_tpl.S create mode 100644 arch/x86/include/asm/handoff.h create mode 100644 arch/x86/lib/tpl.c create mode 100644 configs/chromebook_samus_tpl_defconfig create mode 100644 drivers/sysreset/sysreset_intel_pch.c