From patchwork Wed Dec 5 17:10:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 1008354 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4394zf3BBhz9s6w for ; Thu, 6 Dec 2018 04:12:30 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id EAD0DC2266D; Wed, 5 Dec 2018 17:11:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9ABA1C22681; Wed, 5 Dec 2018 17:11:07 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0BD1FC21F82; Wed, 5 Dec 2018 17:11:04 +0000 (UTC) Received: from mail.bootlin.com (mail.bootlin.com [62.4.15.54]) by lists.denx.de (Postfix) with ESMTP id B5BEEC22003 for ; Wed, 5 Dec 2018 17:11:03 +0000 (UTC) Received: by mail.bootlin.com (Postfix, from userid 110) id 3C9C12073D; Wed, 5 Dec 2018 18:11:02 +0100 (CET) Received: from localhost (242.171.71.37.rev.sfr.net [37.71.171.242]) by mail.bootlin.com (Postfix) with ESMTPSA id 0E25B20729; Wed, 5 Dec 2018 18:11:02 +0100 (CET) From: Gregory CLEMENT To: Daniel Schwierzeck Date: Wed, 5 Dec 2018 18:10:47 +0100 Message-Id: <20181205171054.926-1-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.19.2 MIME-Version: 1.0 Cc: Antoine Tenart , Steen.Hegelund@microchip.com, u-boot@lists.denx.de, Allan Nielsen , Thomas Petazzoni , =?utf-8?b?TWlxdcOo?= =?utf-8?q?l_Raynal?= Subject: [U-Boot] [PATCH v3 0/7] ] Add support for the SoCs found in Microsemi switches X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Hello, For the record this the third version of the series adding the support of 2 SoCs: Ocelot and Luton from Microsemi. Both of them belongs to the same family Vcore III. We found them on various advanced switches product. The support for Ocelot already have been submit to Linux, but not yet the Luton support. Since the v2, U-boot was continued to be tested internally and besides the changes asked by Daniel, we also made several fixes and improvements. Most of them come from Lars Povlsen and Horatiu Vultur. I tried to address all the comment from Daniel and for the part I kept more or less as is, I added comment explaining the rational for this choice inside the code itself. Gregory Changelog: v2 -> v3: - Added n entry in the MAINTAINER file for the SoCs - Fixup the last errors from checkpatch, the remaining ones are only about volatile, long line and Kconfig, but each ones have good reason to be here. - Add SPI NAND flash support in device tree and configuration files, the driver are already be merged in U-Boot. - In order to improve boot time, setup the TLB to allow using cache in the memory mapped to the SPI NOR. - Removed all the macro REG_CFG to only keep direct access to memory. - Put back the setting of the interrupt map as it is needed by mainline kernel (without it the kernel doesn't finish to boot) - During DDR training, prevent the compiler reordering the instruction. - Add early debug support to Ocelot (it was already done for Luton) v1 -> v2: - a big clean-up for indentation and some style issue - usage of the clrsetbits family functions where it was possible - split the patches for Ocelot and Luton - add a new patch to introduce the icache_lock function which was in the mscc directory in the first version - remove more unused define in the platform header files - use the automatic cache size detection instead of hard coding it - reduce the tlb init to only two entries for the IO as needed by the kernel - remove the interrupt disabling - fix the ddr init for luton Gregory CLEMENT (7): MIPS: move create_tlb() in an proper header: mipsregs.h MIPS: Allow to prefetch and lock instructions into cache MSCC: add support for Ocelot SoCs MSCC: add support for Luton SoCs MSCC: add board support for the Ocelots based evaluation boards MSCC: add board support for the Luton based evaluation board MIPS: bootm: Add support for Vcore III linux kernel MAINTAINERS | 13 + arch/mips/Kconfig | 6 + arch/mips/Makefile | 1 + arch/mips/cpu/cpu.c | 10 - arch/mips/dts/luton_pcb091.dts | 35 + arch/mips/dts/mscc,luton.dtsi | 87 ++ arch/mips/dts/mscc,ocelot.dtsi | 152 ++++ arch/mips/dts/mscc,ocelot_pcb.dtsi | 42 + arch/mips/dts/ocelot_pcb120.dts | 12 + arch/mips/dts/ocelot_pcb123.dts | 12 + arch/mips/include/asm/cacheops.h | 19 + arch/mips/include/asm/mipsregs.h | 11 + arch/mips/lib/bootm.c | 78 +- arch/mips/mach-mscc/Kconfig | 86 ++ arch/mips/mach-mscc/Makefile | 6 + arch/mips/mach-mscc/cpu.c | 102 +++ arch/mips/mach-mscc/dram.c | 73 ++ arch/mips/mach-mscc/include/ioremap.h | 51 ++ arch/mips/mach-mscc/include/mach/common.h | 28 + arch/mips/mach-mscc/include/mach/ddr.h | 798 ++++++++++++++++++ .../mips/mach-mscc/include/mach/luton/luton.h | 24 + .../include/mach/luton/luton_devcpu_gcb.h | 14 + .../include/mach/luton/luton_icpu_cfg.h | 245 ++++++ .../mach-mscc/include/mach/ocelot/ocelot.h | 24 + .../include/mach/ocelot/ocelot_devcpu_gcb.h | 21 + .../include/mach/ocelot/ocelot_icpu_cfg.h | 274 ++++++ arch/mips/mach-mscc/include/mach/tlb.h | 55 ++ arch/mips/mach-mscc/lowlevel_init.S | 30 + arch/mips/mach-mscc/lowlevel_init_luton.S | 62 ++ arch/mips/mach-mscc/reset.c | 36 + board/mscc/luton/Kconfig | 14 + board/mscc/luton/Makefile | 3 + board/mscc/luton/luton.c | 28 + board/mscc/ocelot/Kconfig | 14 + board/mscc/ocelot/Makefile | 4 + board/mscc/ocelot/ocelot.c | 58 ++ configs/mscc_luton_defconfig | 66 ++ configs/mscc_ocelot_defconfig | 73 ++ configs/mscc_ocelot_pcb120_defconfig | 66 ++ include/configs/vcoreiii.h | 82 ++ 40 files changed, 2785 insertions(+), 30 deletions(-) create mode 100644 arch/mips/dts/luton_pcb091.dts create mode 100644 arch/mips/dts/mscc,luton.dtsi create mode 100644 arch/mips/dts/mscc,ocelot.dtsi create mode 100644 arch/mips/dts/mscc,ocelot_pcb.dtsi create mode 100644 arch/mips/dts/ocelot_pcb120.dts create mode 100644 arch/mips/dts/ocelot_pcb123.dts create mode 100644 arch/mips/mach-mscc/Kconfig create mode 100644 arch/mips/mach-mscc/Makefile create mode 100644 arch/mips/mach-mscc/cpu.c create mode 100644 arch/mips/mach-mscc/dram.c create mode 100644 arch/mips/mach-mscc/include/ioremap.h create mode 100644 arch/mips/mach-mscc/include/mach/common.h create mode 100644 arch/mips/mach-mscc/include/mach/ddr.h create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton.h create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h create mode 100644 arch/mips/mach-mscc/include/mach/tlb.h create mode 100644 arch/mips/mach-mscc/lowlevel_init.S create mode 100644 arch/mips/mach-mscc/lowlevel_init_luton.S create mode 100644 arch/mips/mach-mscc/reset.c create mode 100644 board/mscc/luton/Kconfig create mode 100644 board/mscc/luton/Makefile create mode 100644 board/mscc/luton/luton.c create mode 100644 board/mscc/ocelot/Kconfig create mode 100644 board/mscc/ocelot/Makefile create mode 100644 board/mscc/ocelot/ocelot.c create mode 100644 configs/mscc_luton_defconfig create mode 100644 configs/mscc_ocelot_defconfig create mode 100644 configs/mscc_ocelot_pcb120_defconfig create mode 100644 include/configs/vcoreiii.h