Message ID | 20180809121949.17305-1-laurentiu.tudor@nxp.com |
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Headers | show
Return-Path: <u-boot-bounces@lists.denx.de> X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41mS4w4nwHz9s1c for <incoming@patchwork.ozlabs.org>; Thu, 9 Aug 2018 22:20:14 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 57D82C21E15; Thu, 9 Aug 2018 12:20:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6E5BAC21C27; Thu, 9 Aug 2018 12:20:02 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8A6A5C21C51; Thu, 9 Aug 2018 12:20:01 +0000 (UTC) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lists.denx.de (Postfix) with ESMTPS id 3A1A2C21C27 for <u-boot@lists.denx.de>; Thu, 9 Aug 2018 12:20:01 +0000 (UTC) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 6CA891A0075; Thu, 9 Aug 2018 14:20:00 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 571511A0082; Thu, 9 Aug 2018 14:20:00 +0200 (CEST) Received: from fsr-ub1864-101.ea.freescale.net (fsr-ub1864-101.ea.freescale.net [10.171.82.97]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id DD5A5205EC; Thu, 9 Aug 2018 14:19:59 +0200 (CEST) From: laurentiu.tudor@nxp.com To: u-boot@lists.denx.de, prabhakar.kushwaha@nxp.com, york.sun@nxp.com Date: Thu, 9 Aug 2018 15:19:41 +0300 Message-Id: <20180809121949.17305-1-laurentiu.tudor@nxp.com> X-Mailer: git-send-email 2.17.1 X-Virus-Scanned: ClamAV using ClamSMTP Subject: [U-Boot] [PATCH v8 0/8] NXP LS1046A SMMU enabling patches X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion <u-boot.lists.denx.de> List-Unsubscribe: <https://lists.denx.de/options/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=unsubscribe> List-Archive: <http://lists.denx.de/pipermail/u-boot/> List-Post: <mailto:u-boot@lists.denx.de> List-Help: <mailto:u-boot-request@lists.denx.de?subject=help> List-Subscribe: <https://lists.denx.de/listinfo/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=subscribe> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de> |
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NXP LS1046A SMMU enabling patches
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From: Laurentiu Tudor <laurentiu.tudor@nxp.com> This patch series adds the required devices setup and device tree fixups for SMMU enablement on NXP LS1046A chips. The approach taken tries to mimic the implementation of PAMU LIODN setup on booke powerpc. First 4 patches contain some fixes and add some missing bits & pieces. Last 4 patches add the actual infrastructure for ICID setup, qman portals, fman ICID and SEC configuration. Changes in v8: - fix link error introduced by patch [6/8] on LS1043A targets: "drivers/built-in.o: relocation R_AARCH64_ADR_PREL_PG_HI21 against external symbol `qp_info' can not be used when making a shared object;" - added missed "Reviewed-By:" tags except patch [6/8] which changed - compile tested all frescale boards with buildman Changes in v7: - fix this build breakage introduced by patch [6/8] on booke ppc appearing with certain tool chain versions: "drivers/misc/fsl_portals.c: In function 'fdt_fixup_qportals': drivers/misc/fsl_portals.c:256:3: error: 'for' loop initial declarations are only allowed in C99 or C11 mode" - fixed linker error on LS1012A targets: "arch/arm/cpu/armv8/built-in.o: In function `fsl_lsch2_early_init_f': arch/arm/cpu/armv8/fsl-layerscape/soc.c:691: undefined reference to `set_icids'" Changes in v6: - distinct ICIDs for all SEC blocks (Horia, Bharat) Changes in v5: - use distinct ICID for SEC JRs (Horia, Bharat) - moved an #include in the file it's used (Horia) - fix broken compilation of multiple targets due to removal of SEC related config (Horia) - add a missing #include in qds board file - drop few uses of CONFIG_SYS_FMAN_V3 and consistently use CONFIG_SYS_DPAA_FMAN everywhere Changes in v4: - added missing SEC ICID config - updated macro params to match arguments - supplemental comments Changes in v3: - cleaner QMAN_BAR setup - moved SoC specific bits from generic ICID arch setup to board code Changes in v2: - drop CONFIG_SYS_ prefix from newly introduced defines in patch [1/8] Laurentiu Tudor (8): armv8: fsl-layerscape: add missing register blocks base address defines armv8: ls1046a: advertise QMan v3 in configuration misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms armv8: fsl-layerscape: add missing debug stream ID armv8: ls1046a: initial icid setup support armv8: ls1046a: add icid setup for qman portals armv8: ls1046a: setup fman ports ICIDs and device tree armv8: ls1046a: setup SEC ICIDs and fix up device tree arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + arch/arm/cpu/armv8/fsl-layerscape/icid.c | 192 ++++++++++++++++++ .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 89 ++++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 5 + .../include/asm/arch-fsl-layerscape/config.h | 1 + .../asm/arch-fsl-layerscape/fsl_icid.h | 115 +++++++++++ .../asm/arch-fsl-layerscape/fsl_portals.h | 24 +++ .../asm/arch-fsl-layerscape/immap_lsch2.h | 15 +- .../asm/arch-fsl-layerscape/stream_id_lsch2.h | 1 + board/freescale/ls1046aqds/ls1046aqds.c | 3 + board/freescale/ls1046ardb/ls1046ardb.c | 3 + drivers/misc/fsl_portals.c | 45 +++- 12 files changed, 486 insertions(+), 8 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/icid.c create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h