From patchwork Tue May 8 22:18:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 910508 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ziswiler.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40gYp76xXVz9s2t for ; Wed, 9 May 2018 08:20:15 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id AB936C21E07; Tue, 8 May 2018 22:19:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E82CDC21E52; Tue, 8 May 2018 22:19:26 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5B9E3C21DCA; Tue, 8 May 2018 22:19:09 +0000 (UTC) Received: from mout.perfora.net (mout.perfora.net [74.208.4.194]) by lists.denx.de (Postfix) with ESMTPS id 7F5B6C21E2C for ; Tue, 8 May 2018 22:19:05 +0000 (UTC) Received: from localhost.net ([84.227.20.26]) by mrelay.perfora.net (mreueus001 [74.208.5.2]) with ESMTPA (Nemesis) id 0MLxKE-1fF6cJ1B88-007haa; Wed, 09 May 2018 00:18:51 +0200 From: Marcel Ziswiler To: u-boot@lists.denx.de Date: Wed, 9 May 2018 00:18:37 +0200 Message-Id: <20180508221840.32463-1-marcel@ziswiler.com> X-Mailer: git-send-email 2.14.3 X-Provags-ID: V03:K1:JuKA0sB+iupeby/JqHOncEK3Abo0yofI2WHJ1XVdy2qeXPs8IGZ YKe+D5M795SJRyBEp2O7rSYM6MdGyG1+8s35euQm2rxhMwrj6DTVvuqqajGFzr9V74uwp+X xwjqbRYYO2ZlaTCxuhs27RjCxdF5E9v5U8aLL5Hi0aFshMDMBmEgfUKUYo9LgmNrQ94WPVG OV0O+nVSH5J5nGiJTbhaw== X-UI-Out-Filterresults: notjunk:1; V01:K0:eLOGdFPiplU=:rINuxjpErUE1J+SDOY3lxR PgFM44IntHOCJIu5TMwZ4SiotVxad8IqMTJjSq+thGMT5plQ5wQtz+QgroXv0FOoTP9A1CoZQ 55RDoJ7LTaHpxTMxKcCz7OQdPCEqgs7Jfs/dpRWOBiinM6GSyu/5VeyfPIwYH6dF1kEoqGsFp ia37zrLR7GsfJMlvxD5TVKN/d89J6N/xwFOATtEsNgd+iP+NWqgmrGxg+AMUgq6SfFcXZSQkX L4XRR98mphpbnf55UHZhjhtOXhwa5VlawyvgfxxE23POLUiWlqdw47996rAQ59x0NheJNSRW2 /Hpc/HCGNM125zdYSAF3UFFwtS5qYBjg71CTgHk/DVXNiXxv9r2+alM5l07sIECxQsoRhWBsu FnWOSyStoVodErOtlX1Mf6EUk9YwZKFQ4V4NolAT6K7VtFOxs2FvL4Udv+TFCzlui60Yw9W7j Hmv6VN5TCJECbF2dMg8sQnkIFIMsqEIdzFr75Nsifx/pxRSPyxYrt4FP3HvTm0wXXtJyf631Q Q6EQV9BpVe7VRhs67Quj2Pi1wCed/3efQ/RlUn6KyXgk35byaF/5HwRlioDpK/6HBnTst9pFR qlLBhfrmJ/s5mgeMom4WfkheBWqQbYLu5Hz/b8JFk3BaOlVna0GBUexALeaBAB29xOQnDOeuA 2l57lofQC8o4b/hsul63hZkCHY+q7gX7xA8hbvi2/kGzcJ+BAlNVmUNK9P44gV5Z5Gag= Cc: Marcel Ziswiler , Marcel Ziswiler , Tom Warren Subject: [U-Boot] [PATCH v4 0/3] fix apalis_t30 optional pcie operation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This series addresses a PCIe reliability issue as observed on Apalis T30 related to a PCIe reset timing violation. This series is available at http://git.toradex.com/cgit/u-boot-toradex.git/log/?h=for-next Changes in v4: - Fix spelling of losing vs. loosing. Changes in v3: - Updated copyright period to 2014-2018. - Added a blank line after declarations as warned by patman. - Added Stephen's acked-by. - Rebased and resend as series so far never got applied! Changes in v2: - Leave resp. enable all port 0 pins input drivers as a customer may optionally want to use some of those MXM3 pins as inputs as well. - Stick to struct tegra_pcie_port as suggested by Stephen. - Introduce proper CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT Kconfig option as suggested by Stephen. - Improved the ifdef vs. if curly braces sequencing as suggested by Stephen. - Keep PCIe port reset status in order to safeguard for future changes to the port reset order or even allow for re-initialisation should that ever be implemented in the higher levels of the driver model. Marcel Ziswiler (3): apalis_t30: describe pcie ports apalis_t30: fix pcie port 0 and 1 pin muxing apalis_t30: fix optional pcie port reset for reliable pcie operation arch/arm/dts/tegra30-apalis.dts | 3 ++ board/toradex/apalis_t30/Kconfig | 9 ++++ board/toradex/apalis_t30/apalis_t30.c | 57 +++++++++++++++++++++- .../toradex/apalis_t30/pinmux-config-apalis_t30.h | 16 +++--- 4 files changed, 77 insertions(+), 8 deletions(-)