From patchwork Fri Nov 8 02:38:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 1191562 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 478PbP1zvZz9sP3 for ; Fri, 8 Nov 2019 13:38:41 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id E9234C21DB6; Fri, 8 Nov 2019 02:38:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C8079C21C3F; Fri, 8 Nov 2019 02:38:34 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 91D7EC21C3F; Fri, 8 Nov 2019 02:38:33 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lists.denx.de (Postfix) with ESMTPS id AEB20C21BE5 for ; Fri, 8 Nov 2019 02:38:32 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Nov 2019 18:38:30 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,280,1569308400"; d="scan'208";a="205865868" Received: from unknown (HELO ubuntu) ([10.226.241.141]) by orsmga003.jf.intel.com with SMTP; 07 Nov 2019 18:38:27 -0800 Received: by ubuntu (sSMTP sendmail emulation); Fri, 08 Nov 2019 10:38:23 +0800 From: Ley Foon Tan To: u-boot@lists.denx.de, Marek Vasut Date: Fri, 8 Nov 2019 10:38:17 +0800 Message-Id: <1573180701-6478-1-git-send-email-ley.foon.tan@intel.com> X-Mailer: git-send-email 2.7.4 Cc: Tien Fong Chee , Chin Liang See , Chee Hong Ang Subject: [U-Boot] [PATCH v6 0/4] arm: socfpga: Convert drivers from struct to defines X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This is 6th version of patchset to convert reset, system and clock manager drivers to use #define instead of struct. Patch 1 unchanged, patch 2,3,4 have changes. Tested on Cyclone 5, Arria 10 and Stratix 10 devices. Changes in v6: - Call to socfpga_get_*mgr_addr() function, instead of access to global variable directly. - Update socfpga_get_base_addr() to return error code, instead of return 0. History: v1: https://patchwork.ozlabs.org/cover/1149731/ v2: https://patchwork.ozlabs.org/cover/1160079/ v3: https://patchwork.ozlabs.org/cover/1174327/ v4: https://patchwork.ozlabs.org/cover/1174347/ v5: https://patchwork.ozlabs.org/cover/1190831/ Ley Foon Tan (4): arm: dts: socfpga: Add u-boot,dm-pre-reloc for sysmgr and clkmgr nodes arm: socfpga: Convert reset manager from struct to defines arm: socfpga: Convert system manager from struct to defines arm: socfpga: Convert clock manager from struct to defines arch/arm/dts/socfpga-common-u-boot.dtsi | 8 + arch/arm/dts/socfpga.dtsi | 2 +- arch/arm/dts/socfpga_arria10.dtsi | 2 +- arch/arm/dts/socfpga_arria10_socdk.dtsi | 8 + arch/arm/dts/socfpga_stratix10.dtsi | 2 +- .../dts/socfpga_stratix10_socdk-u-boot.dtsi | 8 + arch/arm/mach-socfpga/clock_manager.c | 14 +- arch/arm/mach-socfpga/clock_manager_arria10.c | 155 +++++++------ arch/arm/mach-socfpga/clock_manager_gen5.c | 211 ++++++++++------- arch/arm/mach-socfpga/clock_manager_s10.c | 217 ++++++++++-------- .../mach-socfpga/include/mach/clock_manager.h | 2 + .../include/mach/clock_manager_arria10.h | 133 ++++------- .../include/mach/clock_manager_gen5.h | 112 ++++----- .../include/mach/clock_manager_s10.h | 115 ++++------ arch/arm/mach-socfpga/include/mach/misc.h | 1 + .../mach-socfpga/include/mach/reset_manager.h | 2 + .../include/mach/reset_manager_arria10.h | 43 +--- .../include/mach/reset_manager_gen5.h | 22 +- .../include/mach/reset_manager_s10.h | 33 +-- .../include/mach/system_manager.h | 2 + .../include/mach/system_manager_arria10.h | 94 +++----- .../include/mach/system_manager_gen5.h | 123 ++-------- .../include/mach/system_manager_s10.h | 184 ++++++--------- arch/arm/mach-socfpga/mailbox_s10.c | 6 +- arch/arm/mach-socfpga/misc.c | 61 +++++ arch/arm/mach-socfpga/misc_arria10.c | 11 +- arch/arm/mach-socfpga/misc_gen5.c | 33 +-- arch/arm/mach-socfpga/misc_s10.c | 9 +- arch/arm/mach-socfpga/reset_manager_arria10.c | 73 +++--- arch/arm/mach-socfpga/reset_manager_gen5.c | 37 ++- arch/arm/mach-socfpga/reset_manager_s10.c | 55 ++--- arch/arm/mach-socfpga/scan_manager.c | 6 +- arch/arm/mach-socfpga/spl_a10.c | 12 +- arch/arm/mach-socfpga/spl_gen5.c | 26 +-- arch/arm/mach-socfpga/spl_s10.c | 24 +- arch/arm/mach-socfpga/system_manager_gen5.c | 42 ++-- arch/arm/mach-socfpga/system_manager_s10.c | 42 ++-- arch/arm/mach-socfpga/wrap_pll_config_s10.c | 13 +- drivers/ddr/altera/sdram_gen5.c | 12 +- drivers/ddr/altera/sdram_s10.c | 6 +- drivers/fpga/socfpga_arria10.c | 7 +- drivers/fpga/socfpga_gen5.c | 4 +- drivers/mmc/socfpga_dw_mmc.c | 17 +- drivers/sysreset/sysreset_socfpga.c | 6 +- 44 files changed, 945 insertions(+), 1050 deletions(-)