From patchwork Tue Oct 1 17:00:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sagar Shrikant Kadam X-Patchwork-Id: 1170074 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="IMoiXjGN"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46jQX7477Xz9sN1 for ; Wed, 2 Oct 2019 03:01:11 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id EEB8DC21DD3; Tue, 1 Oct 2019 17:01:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 51C12C21C38; Tue, 1 Oct 2019 17:01:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 18912C21C38; Tue, 1 Oct 2019 17:01:05 +0000 (UTC) Received: from mail-pg1-f193.google.com (mail-pg1-f193.google.com [209.85.215.193]) by lists.denx.de (Postfix) with ESMTPS id 71B02C21BE5 for ; Tue, 1 Oct 2019 17:01:04 +0000 (UTC) Received: by mail-pg1-f193.google.com with SMTP id q7so10041155pgi.12 for ; Tue, 01 Oct 2019 10:01:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id; bh=sYCsUVNQcXIN6JfA1K5UGaXF8tIS5tWFKVZydXoJT4M=; b=IMoiXjGNoGR1KhYllka4wOlsOxpKZsVTcKzeiSXvrU/2jLajt62h6IeMNFsFojYayO Seg1fJBl1z78+bQ3rvuCk+uuoPF2Jfm/KojOsA3odWz7Y4SO3mtHr4OjzHLRcvguNaFW 0aJX5kawvKoLcZr2gyHNyumRKUuESeDycU0bMIyWT/Mp/Ardu5Zyg4EuMECr3lLLx629 K6oj4M+N37hrVLvYeZw8O5TAQMLLFc6Rr/zXefl6BtiC/rcygjzAR+Vka8NAzRbhm1Qk dQ4CaWaP6Srb7uMb6cu5GQKBVODelHUd0fp4eguLyNtMzBGAGWpe5CLdtqJFnbsAPRfx jKsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=sYCsUVNQcXIN6JfA1K5UGaXF8tIS5tWFKVZydXoJT4M=; b=q0BHMjWAW1L6xDvyJQwwZNcomekRUN7dAI0mmEQDZ1if3hKAaDZ+geLIB3LlaiUG4a D4incf1zbsFSqLYCWNtLR25Olr9lQda+EMCaKDkPPNcKNNrgZzoGZ9S0HYf6lY22nvJW jfIR5tR9Zh5xiCUYfpaawnTj5M8LctqXyjeGYEewN1BEtw/oQ1Us5a8toJ2/Ll6nqsXl lJhT2hHLytgG+wA7k4vMBvBxYV0w1Iy7/np/L9JGnmdgm/o2qT25Tpmtv7xaV4BQDZHq k5Q6uI4Z86HVrcgpQBXiWW5zAePlnmMbFq3hm+nLXQm15ckli5HQ5SCnqSy5PdCjKCxp WhOQ== X-Gm-Message-State: APjAAAV5CG3mJ7Vf/w7VOkNUtzlIFjUT+TwZJdnq66+HaFBBHSVtZTSr JLoq7qYfLGsoMH3u9TXNpVpaAoPvBRk= X-Google-Smtp-Source: APXvYqzdLZ51z/AmpiVAXwg/SPsFbX5fhptHmgaLkP7LKrVSoYrEzD1mzYVw2jfLh/NcEL9W7CtERw== X-Received: by 2002:aa7:9d8d:: with SMTP id f13mr29325490pfq.196.1569949260746; Tue, 01 Oct 2019 10:01:00 -0700 (PDT) Received: from gamma07.internal.sifive.com ([64.62.193.194]) by smtp.googlemail.com with ESMTPSA id k5sm26096667pfp.109.2019.10.01.10.00.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 01 Oct 2019 10:00:59 -0700 (PDT) From: Sagar Shrikant Kadam To: u-boot@lists.denx.de, rick@andestech.com, paul.walmsley@sifive.com, palmer@sifive.com, anup.patel@wdc.com, atish.patra@wdc.com Date: Tue, 1 Oct 2019 10:00:45 -0700 Message-Id: <1569949247-17895-1-git-send-email-sagar.kadam@sifive.com> X-Mailer: git-send-email 2.7.4 Cc: wesley@sifive.com Subject: [U-Boot] [U-BOOT PATCH v2 0/2] add gpio support for HiFive Unleashed A00 board. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" U-Boot currently is missing GPIO support for FU540-C000 SoC which is mounted on HiFive Unleashed A00 board. This patch is intended to add DM based GPIO controller driver in order to access GPIO pins within the SoC using GPIO command in U-Boot. More details on the GPIO controller within the SoC can be found at[1] The driver is based above master branch of u-boot-riscv.git and provides a method to configure Input/Output mode of the GPIO pin along with an option to set or clear state of the GPIO pin. The patch is available in dev/sagark/gpio_v4 branch here[2]. GPIO device node added to the mainline bound device tree for HiFive Unleashed is available in dev/sagark/mlv5.3-rc5 branch of repo here[3]. This implementation is ported from linux driver submitted for review at [4]. More details of GPIO pin routing on J1 header is available in schematic document[5] [1] https://static.dev.sifive.com/FU540-C000-v1.0.pdf [2] https://github.com/sagsifive/u-boot [3] https://github.com/sagsifive/riscv-linux-hifive/ [4] https://lkml.org/lkml/2018/10/9/1103 [5] https://static.dev.sifive.com/dev-kits/hifive-unleashed/hifive-unleashed-a00-schematics.pdf Driver Testing: # Show status of all gpio's # Pin description will shown pins as unused/output/input. => gpio status -a Bank gpio@10060000_: gpio@10060000_0: unused: 0 [ ] gpio@10060000_1: unused: 0 [ ] ............................... ............................... ............................... gpio@10060000_15: unused: 0 [ ] #Show status of pin 0 => gpio status gpio@10060000_0 Bank gpio@10060000_: gpio@10060000_0: unused: 0 [ ] #Set GPIO1 high. =>gpio set 1 => gpio status gpio@10060000_1 Bank gpio@10060000_: gpio@10060000_1: output: 1 [ ] #Set GPIO1 low =>gpio clear 0 #Toggle GPIO1 =>gpio toggle 1 #Toggle value of GPIO1 =>gpio toggle 1 #Toggle value of GPIO1 #Configure pin as input =>gpio input 3 #Configure gpio line 3 as input. #Error check #16 is not a valid GPIO number for FU540-C000 so return error. =>gpio set 16 GPIO: '16' not found Command 'gpio' failed: Error -22 Patch history: v2: -Added get_function handler which is used by "gpio status" command. -Incorporated review comments on v1 patch series. -Updated driver testing information. v1: -Set gpio_count either from the device tree or with a MACRO if ngpio's property is not mentioned in device node. -Check if gpio number passed from the command line is within the valid range. Incorporated review comment from Bin Meng -Renamed driver from fu540-gpio to sifive-gpio -Include a proper header file -Use dev->name as bank_name. v0: Base version Sagar Shrikant Kadam (2): gpio: sifive: add support for DM based gpio driver for FU540-SoC configs: fu540: enable gpio driver arch/riscv/include/asm/arch-generic/gpio.h | 35 ++++++ arch/riscv/include/asm/gpio.h | 6 + board/sifive/fu540/Kconfig | 3 + drivers/gpio/Kconfig | 7 ++ drivers/gpio/Makefile | 1 + drivers/gpio/sifive-gpio.c | 177 +++++++++++++++++++++++++++++ 6 files changed, 229 insertions(+) create mode 100644 arch/riscv/include/asm/arch-generic/gpio.h create mode 100644 arch/riscv/include/asm/gpio.h create mode 100644 drivers/gpio/sifive-gpio.c