From patchwork Tue Aug 13 16:59:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sagar Shrikant Kadam X-Patchwork-Id: 1146516 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="MLelmv4+"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 467K3j1hBwz9sN1 for ; Wed, 14 Aug 2019 03:10:41 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id CFC31C21FFC; Tue, 13 Aug 2019 17:02:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3F2B2C21FE5; Tue, 13 Aug 2019 17:02:25 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8F96AC21FC1; Tue, 13 Aug 2019 16:59:50 +0000 (UTC) Received: from mail-pg1-f179.google.com (mail-pg1-f179.google.com [209.85.215.179]) by lists.denx.de (Postfix) with ESMTPS id B6764C21F8E for ; Tue, 13 Aug 2019 16:59:47 +0000 (UTC) Received: by mail-pg1-f179.google.com with SMTP id o13so51552821pgp.12 for ; Tue, 13 Aug 2019 09:59:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id; bh=mYSEoEnxIBKY2JHWAwDlWPPPr4IssAJWaWjpaHTzESA=; b=MLelmv4+JteFkXitE0vAGD9iuz0uzoclZcwZMEkLTVuzdL7iAcPwf65wv+FXLGWNmK U0TCQznS0AYd+KgV2rpsl447HRX/O4bZolnbYUeQ8li4NOJaxRrUd6YX9uhmXqW9w9Rk whAFjyWBcvKTsfr22+iTMIFr1wX11fgabbB8WcLBO9BJ3ik+yXuHkzIlp38QnH5Eu4Z5 Kg532tGVrhwFGfTz5d/XDpK7J4IyAHzkG7/RRNTT33XzXWQUjpzc3TSApM4vwwc9bgtm 4Ota5ln21Z+kESW+75L0k1w6FD0NoxrSxVxjo62kzE0u7yELUKDMdSrmHUDJHHWulH0V XdIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=mYSEoEnxIBKY2JHWAwDlWPPPr4IssAJWaWjpaHTzESA=; b=sHMeycwYC1ZmdVfiYXVjA+aCdEJXpmb0XOedjfySKgsjFUHQd3bJLNQYdKNcw5P1Xd VIKpBJX5I1VJQa2xazviVJq/dZEKXuvGmK6a75aG9g0A4PQiA9EgZwQs3810u53R6R67 V2BddgdN/n8FFLVbLc7cw3+TAsGu41dpeP61uZRSHoYLsYBiXdrHX3ZS1wzpFONmSyjk vSmyUGt67aKyyKaukwrEgMbASBqhk/qoYVxGsBmc8P8ByOh7QoR+1rbyqrrjZvuER9qC 6vm2ctSNuAvwAPJqRNZOomNSq4g9P+vhWp6s6kTwrEiHl2rwAHoG8llwFQOac4kg3KG9 Vsbw== X-Gm-Message-State: APjAAAXey6u8DIRW5xAtg7NI0Bfhc1loDc8im/+XNpxj4EC2YJD/PX6X LcCK6Wgs17LlGPGgyNxYKpOh2ndSzZhk/A== X-Google-Smtp-Source: APXvYqyVWizQqVbmY3tz2gIDg2xu89LIgzwUY9Kh1yY/6V80jcbdhmJczN6ZQFkdWU1/vPDnFfsxEA== X-Received: by 2002:aa7:8611:: with SMTP id p17mr8304788pfn.41.1565715585582; Tue, 13 Aug 2019 09:59:45 -0700 (PDT) Received: from gamma07.internal.sifive.com ([64.62.193.194]) by smtp.googlemail.com with ESMTPSA id w11sm6040857pfi.105.2019.08.13.09.59.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 13 Aug 2019 09:59:44 -0700 (PDT) From: Sagar Shrikant Kadam To: u-boot@lists.denx.de, paul.walmsley@sifive.com, palmer@sifive.com, anup.patel@wdc.com, atish.patra@wdc.com, jagan@amarulasolutions.com, vigneshr@ti.com Date: Tue, 13 Aug 2019 09:59:28 -0700 Message-Id: <1565715571-26558-1-git-send-email-sagar.kadam@sifive.com> X-Mailer: git-send-email 2.7.4 Subject: [U-Boot] [U-BOOT PATCH 0/3] add support for spi-nor device on HiFive Unleashed board X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch series adds support for 32MiB SPI-NOR flash (is25wp256 from ISSI). Many thanks to Bhargav Shah for porting the spi-nor patches from linux to U-boot in order to support this device. Ref: linux patches which are under review https://lkml.org/lkml/2019/7/2/859 Linux has an option of registering post-bfpt fixups in order to over-ride the incorrect configuration of flash devices due to wrong SFDP entries read from the flash device during nor scan phase. The 1st patch introduces this support to register post bfpt fixup hook similar to that done in linux. The second patch in the series enables support for the flash device in single I/O mode. A post bfpt fixup is registered because the flash device gets BFPT_DWORD1_ADDRESS_BYTES_3_ONLY from BFPT table for address width, whereas the flash can support 4 byte address width. The SPI_NOR_HAS_BP3 bit indicates that the flash protection block has BP0 to BP3 bits. Lock/Unlock mechanism: The implementation is based on stm_lock/unlock scheme and is validated for different number of blocks passed to sf command. Unlock scheme unilateraly clears all the protection bits of all blocks in the status register. The series is based on the master branch of[1] [1] https://gitlab.denx.de/u-boot/custodians/u-boot-riscv and is available in dev/sagark/hifive-spi-nor_v2 branch of[2] [2] https://github.com/sagsifive/u-boot. Flash operations like erase/read/write lock/unlock are verified and data integrity is checked using sf commands as follows: => sf write 0x80600000 0x0 0x2000000 device 0 whole chip SF: 33554432 bytes @ 0x0 Written: OK => sf read 0x82700000 0x0 0x2000000 device 0 whole chip SF: 33554432 bytes @ 0x0 Read: OK => cmp.b 0x80600000 0x82700000 0x2000000 Total of 33554432 byte(s) were the same => sf protect lock 0x1000000 0x1000000 => mw 0x80600000 0x12345678 0x2000000 => sf write 0x80600000 0x0 0x2000000 Reset the board to flush out data from memory => sf probe => sf read 0x80600000 0x0 0x2000000 In memory dump after sf read from address 0x80600000 we can see that upper 16MiB flash section is protected. Sagar Shrikant Kadam (3): spi: nor: add spi-nor-fixup handlers for nor devices spi: nor: add support for is25wp256 spi: riscv: use single bit mode for spi transfers board/sifive/fu540/Kconfig | 5 + drivers/mtd/spi/sf_internal.h | 23 +++ drivers/mtd/spi/spi-nor-core.c | 373 +++++++++++++++++++++++++++++++++++------ drivers/mtd/spi/spi-nor-ids.c | 5 + drivers/spi/spi-sifive.c | 7 +- include/linux/mtd/spi-nor.h | 8 + 6 files changed, 363 insertions(+), 58 deletions(-)