From patchwork Tue Jan 30 15:01:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 867511 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="Nw9pDbjz"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zW8nm4KTqz9s4q for ; Wed, 31 Jan 2018 02:05:32 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 4261CC21E55; Tue, 30 Jan 2018 15:04:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C0D7BC21EA2; Tue, 30 Jan 2018 15:02:26 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 118C2C21EA2; Tue, 30 Jan 2018 15:02:09 +0000 (UTC) Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by lists.denx.de (Postfix) with ESMTPS id D385DC21E37 for ; Tue, 30 Jan 2018 15:02:04 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w0UF1v6T024851; Tue, 30 Jan 2018 09:01:57 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517324517; bh=iGRVUobSYQQoSfg7NPhg+euYcah+bp7we180srM6zKE=; h=From:To:CC:Subject:Date; b=Nw9pDbjzZkP4BXrJUDI59JAIoFSieOPN+BIU25F4d8QCBdxFFdrrIq2jV5k7Zx/6v ZgJXt2hH+SoW0bEZcfZKJlKNkRn+bdULzPDKZVq5J1pi/xbg6nQB1P1H9ycFO9/i3T UViqG3w37sEVzAo4L+lC9mN1oi9zJHlSooh9m3Qg= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF1v9s004655; Tue, 30 Jan 2018 09:01:57 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 30 Jan 2018 09:01:56 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 30 Jan 2018 09:01:56 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF1tG2031746; Tue, 30 Jan 2018 09:01:56 -0600 From: Jean-Jacques Hiblot To: , , , Date: Tue, 30 Jan 2018 16:01:29 +0100 Message-ID: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Praneeth Bajjuri , u-boot@lists.denx.de, Vishal Mahaveer Subject: [U-Boot] [PATCH v3 00/24] omap_hsmmc: Add support for HS200 and UHS modes X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This series adds the missing bits to enable the UHS and HS200 modes for the TI platforms. Enabling support for high speed modes on omap5 requires implementing: * io signal voltage selection * tuning support * pin configuration (IO delays) The few last patches enable the high speed modes for the DRA7 platforms and also take care of disabling those modes in the dts for the platforms that cannot support either the UHS or the HS200 because the voltage regulators on board would not allow using those modes (not a SOC limitation). With this in place we observe significant improvements in the performances: on a DRA72 evm: eMMC HS200: 124 MB/s eMMC DDR52: 78 MB/s sd SDR104: 71 MB/s sd SDR50: 44 MB/s For the record, the original performances were: SD High speed: 18 MB/s MMC High speed: 18 MB/s This series has been tested on: * DRA71-evm * DRA72-evm * DRA7x-evm * DRA76-evm * AM57x-evm * Beaglebone Black (dt and non-dt) Changes in v2: - rebased on top of u-boot/master - enable the H200 and UHS support in the defconfigs of the DRA7 platforms Changes in v3: - in omap_hsmmc_set_clock(), if mmc->clock is zero, use the max divider. - prefer the usage of the BIT() macro over the construct ( 1 << x ) - fixed build issue with omap3 platforms Jean-Jacques Hiblot (13): mmc: omap_hsmmc: cleanup clock configuration mmc: omap_hsmmc: set MMC mode in the UHSMS bit field mmc: omap_hsmmc: Add tuning support mmc: omap_hsmmc: Workaround for errata id i802 mmc: omap_hsmmc: Reduce the max timeout for reset controller fsm mmc: omap_hsmmc: allow the simple HS modes to use the default pinctrl mmc: omap_hsmmc: update mmc->clock with the actual bus speed mmc: omap_hsmmc: implement send_init_stream callback mmc: omap_hsmmc: add signal voltage selection support ARM: dts: dra7: Add supported MMC/SD modes in MMC dt nodes dts: am57xx-beagle-x15: disable UHS and HS200 support dts: am57xx-idk: disable HS200 support configs: dra7xx_evm/dra7xx_hs_evm: Enable MMC HS200 and SD UHS support Kishon Vijay Abraham I (11): mmc: omap_hsmmc: cleanup omap_hsmmc_set_ios mmc: omap_hsmmc: add support to set default io voltage mmc: omap_hsmmc: Enable DDR mode support mmc: omap_hsmmc: use mmc_of_parse to populate mmc_config ARM: OMAP5/DRA7: Enable iodelay recalibration to be done from uboot mmc: omap_hsmmc: Add support to set IODELAY values mmc: omap_hsmmc: Add support to get pinctrl values and max frequency for different hw revisions mmc: omap_hsmmc: allow mmc clock to be gated ARM: OMAP5: set mmc clock frequency to 192MHz ARM: dts: DRA7: use new dra7-specific compatible string ARM: DRA7x/AM57x: Add MMC/SD fixups for rev1.0 and rev 1.1 arch/arm/dts/am57xx-beagle-x15.dts | 6 + arch/arm/dts/am57xx-idk-common.dtsi | 2 + arch/arm/dts/dra7.dtsi | 22 +- arch/arm/include/asm/arch-omap5/clock.h | 2 +- arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h | 3 + arch/arm/include/asm/arch-omap5/sys_proto.h | 7 + arch/arm/include/asm/omap_mmc.h | 59 +- arch/arm/mach-omap2/omap5/dra7xx_iodelay.c | 30 + arch/arm/mach-omap2/omap5/hw_data.c | 10 +- board/ti/am57xx/board.c | 30 + board/ti/dra7xx/evm.c | 29 + configs/dra7xx_evm_defconfig | 3 + configs/dra7xx_hs_evm_defconfig | 3 + drivers/mmc/omap_hsmmc.c | 952 +++++++++++++++++++++-- include/configs/am57xx_evm.h | 2 - include/configs/dra7xx_evm.h | 2 - 16 files changed, 1087 insertions(+), 75 deletions(-)