From patchwork Wed Nov 15 12:14:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 838152 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ycNk21Xkxz9sDB for ; Wed, 15 Nov 2017 23:20:10 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id CDA0BC21D65; Wed, 15 Nov 2017 12:16:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0C2A3C21D8D; Wed, 15 Nov 2017 12:15:42 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 953C1C21D65; Wed, 15 Nov 2017 12:15:38 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lists.denx.de (Postfix) with ESMTPS id 53D64C21D65 for ; Wed, 15 Nov 2017 12:15:35 +0000 (UTC) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id vAFCETXR002494; Wed, 15 Nov 2017 13:15:30 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2e8mbpgb84-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 15 Nov 2017 13:15:30 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 8804F34; Wed, 15 Nov 2017 12:15:29 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 425D3274; Wed, 15 Nov 2017 12:15:29 +0000 (GMT) Received: from localhost (10.75.127.50) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 15 Nov 2017 13:15:28 +0100 From: To: , , , , Date: Wed, 15 Nov 2017 13:14:42 +0100 Message-ID: <1510748093-16433-1-git-send-email-patrice.chotard@st.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [10.75.127.50] X-ClientProxiedBy: SFHDAG3NODE2.st.com (10.75.127.8) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-11-15_06:, , signatures=0 Subject: [U-Boot] [PATCH 00/11] Extend clk_stm32f7 driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Patrice Chotard It's the second step to prepare STM32F4 conversion to driver model and device tree support. STM32F4 and STM32F7 RCC IPs are similar, differences between these 2 SoCs can be managed with different compatible string and allows to use a common clock driver. This series update the clk_stm32f7 driver : _ retrieve PWR IP base address from DT instead of using hardcoded value. _ update compatible string to manage differences between STM32F4 and STM32F7 _ introduce STM32F4 support. _ enable RCC MFD support which allows reset support for STM32F7/F4. _ add MMC clock configuration for MMC usag for STM32F4/F7. _ migrate some defines/struct to common include/stm32_rcc.h to factorize code between STM32F4/F7. Patrice Chotard (11): ARM: DTS: stm32: add pwrcfg node for stm32f746 clk: stm32f7: retrieve PWR base address from DT clk: stm32f7: add dedicated STM32F7 compatible string ARM: DTS: stm32: update rcc compatible for STM32F746 clk: stm32f7: add STM32F4 support clk: stm32f7: rename clk_stm32f7.c to clk_stm32f.c clk: stm32fx: migrate define from rcc.h to driver configs: stm32f746-disco: enable MISC/DM_RESET/STM32_RESET and STM32_RCC dm: misc: bind STM32F4/F7 clock from rcc MFD driver clk: clk_stm32fx: add clock configuration for mmc usage stm32: migrate clock structs in include/stm32_rcc.h arch/arm/dts/stm32f7-u-boot.dtsi | 4 + arch/arm/dts/stm32f746.dtsi | 9 +- arch/arm/include/asm/arch-stm32f4/stm32.h | 35 --- arch/arm/include/asm/arch-stm32f4/stm32_pwr.h | 23 ++ arch/arm/include/asm/arch-stm32f7/rcc.h | 31 --- arch/arm/include/asm/arch-stm32f7/stm32.h | 41 ---- arch/arm/include/asm/arch-stm32f7/stm32_pwr.h | 25 ++ arch/arm/mach-stm32/stm32f4/clock.c | 27 +- arch/arm/mach-stm32/stm32f4/timer.c | 1 + arch/arm/mach-stm32/stm32f7/timer.c | 1 + board/st/stm32f429-discovery/stm32f429-discovery.c | 1 + configs/stm32f746-disco_defconfig | 4 + drivers/clk/Kconfig | 8 + drivers/clk/Makefile | 2 +- drivers/clk/{clk_stm32f7.c => clk_stm32f.c} | 272 +++++++++++++++------ drivers/misc/stm32_rcc.c | 42 +++- include/dt-bindings/mfd/stm32f7-rcc.h | 1 + include/stm32_rcc.h | 91 +++++++ 18 files changed, 401 insertions(+), 217 deletions(-) create mode 100644 arch/arm/include/asm/arch-stm32f4/stm32_pwr.h delete mode 100644 arch/arm/include/asm/arch-stm32f7/rcc.h create mode 100644 arch/arm/include/asm/arch-stm32f7/stm32_pwr.h rename drivers/clk/{clk_stm32f7.c => clk_stm32f.c} (56%) create mode 100644 include/stm32_rcc.h