| Message ID | 20221222114635.1251934-8-andrzej.hajda@intel.com |
|---|---|
| State | New |
| Headers | show
Return-Path: <SRS0=l9p9=4U=vger.kernel.org=sparclinux-owner@ozlabs.org>
X-Original-To: incoming@patchwork.ozlabs.org
Delivered-To: patchwork-incoming@legolas.ozlabs.org
Authentication-Results: legolas.ozlabs.org;
spf=pass (sender SPF authorized) smtp.mailfrom=ozlabs.org
(client-ip=2404:9400:2221:ea00::3; helo=gandalf.ozlabs.org;
envelope-from=srs0=l9p9=4u=vger.kernel.org=sparclinux-owner@ozlabs.org;
receiver=<UNKNOWN>)
Authentication-Results: legolas.ozlabs.org;
dkim=pass (2048-bit key;
unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256
header.s=Intel header.b=hapVsBVp;
dkim-atps=neutral
Received: from gandalf.ozlabs.org (mail.ozlabs.org
[IPv6:2404:9400:2221:ea00::3])
(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)
key-exchange X25519 server-signature ECDSA (P-384))
(No client certificate requested)
by legolas.ozlabs.org (Postfix) with ESMTPS id 4Nd7sc3D73z23dC
for <incoming@patchwork.ozlabs.org>; Thu, 22 Dec 2022 22:50:12 +1100 (AEDT)
Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76])
by gandalf.ozlabs.org (Postfix) with ESMTP id 4Nd7sc2jH1z4xND
for <incoming@patchwork.ozlabs.org>; Thu, 22 Dec 2022 22:50:12 +1100 (AEDT)
Received: by gandalf.ozlabs.org (Postfix)
id 4Nd7sc2gfMz4xP3; Thu, 22 Dec 2022 22:50:12 +1100 (AEDT)
Delivered-To: patchwork-incoming@ozlabs.org
Authentication-Results: gandalf.ozlabs.org;
dmarc=pass (p=none dis=none) header.from=intel.com
Authentication-Results: gandalf.ozlabs.org;
spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org
(client-ip=2620:137:e000::1:20; helo=out1.vger.email;
envelope-from=sparclinux-owner@vger.kernel.org; receiver=<UNKNOWN>)
Authentication-Results: gandalf.ozlabs.org;
dkim=pass (2048-bit key;
unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256
header.s=Intel header.b=hapVsBVp;
dkim-atps=neutral
Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20])
by gandalf.ozlabs.org (Postfix) with ESMTP id 4Nd7sc2bGKz4xND
for <patchwork-incoming@ozlabs.org>; Thu, 22 Dec 2022 22:50:12 +1100 (AEDT)
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
id S235529AbiLVLuI (ORCPT <rfc822;patchwork-incoming@ozlabs.org>);
Thu, 22 Dec 2022 06:50:08 -0500
Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48278 "EHLO
lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
with ESMTP id S235549AbiLVLsT (ORCPT
<rfc822;sparclinux@vger.kernel.org>); Thu, 22 Dec 2022 06:48:19 -0500
Received: from mga04.intel.com (mga04.intel.com [192.55.52.120])
by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46E2B29357;
Thu, 22 Dec 2022 03:48:07 -0800 (PST)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple;
d=intel.com; i=@intel.com; q=dns/txt; s=Intel;
t=1671709687; x=1703245687;
h=from:to:cc:subject:date:message-id:in-reply-to:
references:mime-version:content-transfer-encoding;
bh=HqehGh0ckEYfFGXBXebYCNsma95awkbnu5950FMjD0o=;
b=hapVsBVpNxXESnwSl6R41uwfyC8I2TCoBQ8PbUCDjIkicJYqOUOrnxys
+cU7XIetp+KjCqIuc7ZvR6UsXr2md/3/0vbpsxHvCFKWeA6R+Yzj4vF7F
WB0/ycDj+whNIc2jmmbGCtX0njBArmZtjg0a6SovyfKdCcYYzCWT5qDuQ
RZqld9t7wYlGlzNqToVZS/lVbmwvRrZGJJfr37I9BIhTdMKiWgx0LLKST
bIGJy709zIYEe9AVl1cDo6F7lQ5xFtgjfIJmZyprZ2GAUbfLJU1eNVdth
//+YfWiKZDesc/kHWuvgIsgACiUpToBKudrumsDSthNQNAD3KBc0pCSND
A==;
X-IronPort-AV: E=McAfee;i="6500,9779,10568"; a="318804633"
X-IronPort-AV: E=Sophos;i="5.96,265,1665471600";
d="scan'208";a="318804633"
Received: from orsmga006.jf.intel.com ([10.7.209.51])
by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;
22 Dec 2022 03:48:06 -0800
X-IronPort-AV: E=McAfee;i="6500,9779,10568"; a="629504660"
X-IronPort-AV: E=Sophos;i="5.96,265,1665471600";
d="scan'208";a="629504660"
Received: from lab-ah.igk.intel.com ([10.91.215.196])
by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;
22 Dec 2022 03:48:00 -0800
From: Andrzej Hajda <andrzej.hajda@intel.com>
To: linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-snps-arc@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-hexagon@vger.kernel.org, linux-ia64@vger.kernel.org,
loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org,
linux-mips@vger.kernel.org, openrisc@lists.librecores.org,
linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org,
linux-sh@vger.kernel.org, sparclinux@vger.kernel.org,
linux-xtensa@linux-xtensa.org, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
Cc: Andrzej Hajda <andrzej.hajda@intel.com>,
Arnd Bergmann <arnd@arndb.de>,
Rodrigo Vivi <rodrigo.vivi@intel.com>,
Andrew Morton <akpm@linux-foundation.org>,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Boqun Feng <boqun.feng@gmail.com>,
Mark Rutland <mark.rutland@arm.com>
Subject: [PATCH 07/19] arch/loongarch: rename internal name __xchg to
__arch_xchg
Date: Thu, 22 Dec 2022 12:46:23 +0100
Message-Id: <20221222114635.1251934-8-andrzej.hajda@intel.com>
X-Mailer: git-send-email 2.34.1
In-Reply-To: <20221222114635.1251934-1-andrzej.hajda@intel.com>
References: <20221222114635.1251934-1-andrzej.hajda@intel.com>
MIME-Version: 1.0
Organization: Intel Technology Poland sp. z o.o. - ul. Slowackiego 173,
80-298 Gdansk - KRS 101882 - NIP 957-07-52-316
Content-Transfer-Encoding: 8bit
X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,
DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,
SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no
version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <sparclinux.vger.kernel.org>
X-Mailing-List: sparclinux@vger.kernel.org
|
| Series |
Introduce __xchg, non-atomic xchg
|
expand
|
diff --git a/arch/loongarch/include/asm/cmpxchg.h b/arch/loongarch/include/asm/cmpxchg.h index ecfa6cf79806e6..979fde61bba8a4 100644 --- a/arch/loongarch/include/asm/cmpxchg.h +++ b/arch/loongarch/include/asm/cmpxchg.h @@ -62,7 +62,7 @@ static inline unsigned int __xchg_small(volatile void *ptr, unsigned int val, } static __always_inline unsigned long -__xchg(volatile void *ptr, unsigned long x, int size) +__arch_xchg(volatile void *ptr, unsigned long x, int size) { switch (size) { case 1: @@ -87,7 +87,7 @@ __xchg(volatile void *ptr, unsigned long x, int size) __typeof__(*(ptr)) __res; \ \ __res = (__typeof__(*(ptr))) \ - __xchg((ptr), (unsigned long)(x), sizeof(*(ptr))); \ + __arch_xchg((ptr), (unsigned long)(x), sizeof(*(ptr))); \ \ __res; \ })
__xchg will be used for non-atomic xchg macro. Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> --- arch/loongarch/include/asm/cmpxchg.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)