From patchwork Tue Feb 24 03:07:37 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Ahern X-Patchwork-Id: 442762 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 60388140119 for ; Tue, 24 Feb 2015 14:07:59 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752538AbbBXDH7 (ORCPT ); Mon, 23 Feb 2015 22:07:59 -0500 Received: from aserp1040.oracle.com ([141.146.126.69]:49461 "EHLO aserp1040.oracle.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752392AbbBXDH6 (ORCPT ); Mon, 23 Feb 2015 22:07:58 -0500 Received: from acsinet21.oracle.com (acsinet21.oracle.com [141.146.126.237]) by aserp1040.oracle.com (Sentrion-MTA-4.3.2/Sentrion-MTA-4.3.2) with ESMTP id t1O37r6Q022234 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Tue, 24 Feb 2015 03:07:53 GMT Received: from userz7022.oracle.com (userz7022.oracle.com [156.151.31.86]) by acsinet21.oracle.com (8.14.4+Sun/8.14.4) with ESMTP id t1O37qh4000020 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 24 Feb 2015 03:07:53 GMT Received: from abhmp0010.oracle.com (abhmp0010.oracle.com [141.146.116.16]) by userz7022.oracle.com (8.14.5+Sun/8.14.4) with ESMTP id t1O37pu3020299; Tue, 24 Feb 2015 03:07:52 GMT Received: from ca-qasparc20.us.oracle.com (/10.147.24.73) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Mon, 23 Feb 2015 19:07:51 -0800 From: David Ahern To: sparclinux@vger.kernel.org, davem@davemloft.net Cc: David Ahern Subject: [PATCH 3/3] sparc: perf: Make counting mode actually work Date: Mon, 23 Feb 2015 22:07:37 -0500 Message-Id: <1424747257-141252-3-git-send-email-david.ahern@oracle.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1424747257-141252-1-git-send-email-david.ahern@oracle.com> References: <1424747257-141252-1-git-send-email-david.ahern@oracle.com> X-Source-IP: acsinet21.oracle.com [141.146.126.237] Sender: sparclinux-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: sparclinux@vger.kernel.org Currently perf-stat (aka, counting mode) does not work: perf stat ./1bi Performance counter stats for './1bi': 131.864070 task-clock (msec) # 0.993 CPUs utilized 0 context-switches # 0.000 K/sec 0 cpu-migrations # 0.000 K/sec 30 page-faults # 0.228 K/sec 0 cycles # 0.000 GHz stalled-cycles-frontend:HG stalled-cycles-backend:HG 0 instructions:HG 0 branches:HG # 0.000 K/sec 0 branch-misses:HG # 0.00% of all branches 0.132778349 seconds time elapsed The reason is that state is never reset (stays with PERF_HES_UPTODATE set). Add a call to sparc_pmu_enable_event during the added_event handling. Clean up the encoding since pmu_start calls sparc_pmu_enable_event which does the same. Passing PERF_EF_RELOAD to sparc_pmu_start means the call to sparc_perf_event_set_period can be removed as well. With this patch: perf stat ./1bi Performance counter stats for './1bi': 131.893485 task-clock (msec) # 0.992 CPUs utilized 0 context-switches # 0.000 K/sec 0 cpu-migrations # 0.000 K/sec 30 page-faults # 0.227 K/sec 546,781,981 cycles # 4.146 GHz stalled-cycles-frontend:HG stalled-cycles-backend:HG 1,090,528,128 instructions:HG # 1.99 insns per cycle 10,089,375 branches:HG # 76.496 M/sec 7,182 branch-misses:HG # 0.07% of all branches 0.132918320 seconds time elapsed Signed-off-by: David Ahern --- arch/sparc/kernel/perf_event.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c index 48b565fdb486..86eebfa3b158 100644 --- a/arch/sparc/kernel/perf_event.c +++ b/arch/sparc/kernel/perf_event.c @@ -996,6 +996,8 @@ static void calculate_single_pcr(struct cpu_hw_events *cpuc) cpuc->pcr[0] |= cpuc->event[0]->hw.config_base; } +static void sparc_pmu_start(struct perf_event *event, int flags); + /* On this PMU each PIC has it's own PCR control register. */ static void calculate_multiple_pcrs(struct cpu_hw_events *cpuc) { @@ -1008,20 +1010,13 @@ static void calculate_multiple_pcrs(struct cpu_hw_events *cpuc) struct perf_event *cp = cpuc->event[i]; struct hw_perf_event *hwc = &cp->hw; int idx = hwc->idx; - u64 enc; if (cpuc->current_idx[i] != PIC_NO_INDEX) continue; - sparc_perf_event_set_period(cp, hwc, idx); cpuc->current_idx[i] = idx; - enc = perf_event_get_enc(cpuc->events[i]); - cpuc->pcr[idx] &= ~mask_for_index(idx); - if (hwc->state & PERF_HES_STOPPED) - cpuc->pcr[idx] |= nop_for_index(idx); - else - cpuc->pcr[idx] |= event_encoding(enc, idx); + sparc_pmu_start(cp, PERF_EF_RELOAD); } out: for (i = 0; i < cpuc->n_events; i++) {