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bh=F+zww1XInGrZ7RpGgLW9fRGnMzTvE0IwSyy/5Fuox8I=; b=ghf6f08KF5c61rcJ+U8VUP/2UD96jFh6lFar+FWTmIomVBbZ2j/RMFTLiIR02GsFEh 4O2/HSKewfH/V2NKfptf3/xnHpLg6jXtJVX5UchqoIPRH0FI2IEAL9vfy0UUSc/R5dhO mWoaE9T/o7+JaKWSM1pLer5G5f9qZ/k4xUOJt8u+RWCb5fVnOt5gkzOQLXLxYXMno/Sc 46iUnrlUz8jo0h9k/fjPHRoiPsscHDNLgd7/oYWe3HGOjn49Nwtqgoz08LmfObV10iTx fkzf5lSW2gWDD4D9UiXPsEpYDnYse6D0WQMX+BoX1EMAhthqY4M8UzEybLdNCIC0dTr0 9h4w== X-Gm-Message-State: AC+VfDzyWLklwhaESzOPuK1cdfNmCm9LgIQg4N2qLVuEY7kNf9BlIquF U3GcP53zNkIHLrOxaDDR6+fjh84NTps= X-Google-Smtp-Source: ACHHUZ7kztFwDNxOxbmfH8qkQLS8H6pGBnkzHi0MjI3EiunCYlzhIaMMj3PgT6hQTIPaWWB9AEhz7A== X-Received: by 2002:a05:6358:714:b0:123:3203:9287 with SMTP id e20-20020a056358071400b0012332039287mr10032547rwj.4.1685680223209; Thu, 01 Jun 2023 21:30:23 -0700 (PDT) Received: from wheely.local0.net ([203.221.142.9]) by smtp.gmail.com with ESMTPSA id e23-20020a17090ab39700b002532eef4fc5sm291198pjr.34.2023.06.01.21.30.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jun 2023 21:30:22 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Fri, 2 Jun 2023 14:30:16 +1000 Message-Id: <20230602043016.46343-1-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 Subject: [Skiboot] [PATCH] hw/chiptod: allow qemu to use the chiptod X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" There is a QEMU model for ChipTOD (not yet upstream) that provides enough to get through skiboot's sync sequence. So run the chiptod init when running under QEMU, if it is being provided in the device tree. If not, don't crash because the QEMU patch has not been merged yet... Signed-off-by: Nicholas Piggin --- core/chip.c | 3 +-- hw/chiptod.c | 8 ++++++-- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/core/chip.c b/core/chip.c index 6fc5d423..cee65822 100644 --- a/core/chip.c +++ b/core/chip.c @@ -187,8 +187,7 @@ void init_chips(void) dt_node_is_compatible(dt_root, "qemu,powernv9") || dt_node_is_compatible(dt_root, "qemu,powernv10") || dt_find_by_path(dt_root, "/qemu")) { - proc_chip_quirks |= QUIRK_QEMU | QUIRK_NO_CHIPTOD - | QUIRK_NO_DIRECT_CTL | QUIRK_NO_RNG; + proc_chip_quirks |= QUIRK_QEMU | QUIRK_NO_DIRECT_CTL | QUIRK_NO_RNG; prlog(PR_NOTICE, "CHIP: Detected QEMU simulator\n"); } diff --git a/hw/chiptod.c b/hw/chiptod.c index 736bd03f..e3941e29 100644 --- a/hw/chiptod.c +++ b/hw/chiptod.c @@ -1681,7 +1681,6 @@ error_out: static int64_t opal_resync_timebase(void) { - /* Mambo and qemu doesn't simulate the chiptod */ if (chip_quirk(QUIRK_NO_CHIPTOD)) return OPAL_SUCCESS; @@ -1829,13 +1828,16 @@ void chiptod_init(void) bool sres; int i; - /* Mambo and qemu doesn't simulate the chiptod */ if (chip_quirk(QUIRK_NO_CHIPTOD)) return; op_display(OP_LOG, OP_MOD_CHIPTOD, 0); if (!chiptod_probe()) { + /* Not all QEMU models provide chiptod */ + if (chip_quirk(QUIRK_QEMU)) + return; + prerror("Failed ChipTOD detection !\n"); op_display(OP_FATAL, OP_MOD_CHIPTOD, 0); abort(); @@ -1903,6 +1905,8 @@ void chiptod_init(void) chiptod_init_topology_info(); op_display(OP_LOG, OP_MOD_CHIPTOD, 4); + + prlog(PR_NOTICE, "Synchronized all processors to common timebase.\n"); } /* CAPP timebase sync */