diff mbox series

[v4,6/9] npu: move npu_set_fence_state() to phb_ops

Message ID 20211217023647.715283-7-npiggin@gmail.com
State Superseded
Headers show
Series hwprobe patches | expand

Commit Message

Nicholas Piggin Dec. 17, 2021, 2:36 a.m. UTC 
From: Stewart Smith <stewart@flamingspork.com>

This lets us consider not building in npu.o

Reviewed-by: Dan Horák <dan@danny.cz>
Signed-off-by: Stewart Smith <stewart@flamingspork.com>
---
 core/hmi.c    | 2 +-
 hw/npu.c      | 7 +++++--
 include/npu.h | 1 -
 include/pci.h | 3 +++
 4 files changed, 9 insertions(+), 4 deletions(-)

Comments

Cédric Le Goater Dec. 17, 2021, 3:26 p.m. UTC | #1 
On 12/17/21 03:36, Nicholas Piggin wrote:
> From: Stewart Smith <stewart@flamingspork.com>
> 
> This lets us consider not building in npu.o

I would instead introduce an empty stub for npu_set_fence_state()
in npu.h.

Thanks,

C.

> Reviewed-by: Dan Horák <dan@danny.cz>
> Signed-off-by: Stewart Smith <stewart@flamingspork.com>
> ---
>   core/hmi.c    | 2 +-
>   hw/npu.c      | 7 +++++--
>   include/npu.h | 1 -
>   include/pci.h | 3 +++
>   4 files changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/core/hmi.c b/core/hmi.c
> index ce5abd7d6..fe3d82529 100644
> --- a/core/hmi.c
> +++ b/core/hmi.c
> @@ -908,7 +908,7 @@ static void find_npu_checkstop_reason(int flat_chip_id,
>   
>   		if (phb->phb_type == phb_type_pcie_v3) {
>   			/* Set the NPU to fenced since it can't recover. */
> -			npu_set_fence_state(phb_to_npu(phb), true);
> +			phb->ops->set_fence_state(phb, true);
>   		}
>   
>   		/* Set up the HMI event */
> diff --git a/hw/npu.c b/hw/npu.c
> index 35e6372d2..542f37397 100644
> --- a/hw/npu.c
> +++ b/hw/npu.c
> @@ -925,7 +925,9 @@ static int64_t npu_eeh_next_error(struct phb *phb,
>   }
>   
>   /* For use in error injection and handling. */
> -void npu_set_fence_state(struct npu *p, bool fence) {
> +static void npu_set_fence_state(struct phb *phb, bool fence) {
> +	struct npu *p = phb_to_npu(phb);
> +
>   	p->fenced = fence;
>   
>   	if (fence)
> @@ -968,7 +970,7 @@ static int64_t npu_err_inject(struct phb *phb, uint64_t pe_number,
>   		return OPAL_PARAMETER;
>   	} else if (type == 1) {
>   		/* Emulate fence mode. */
> -		npu_set_fence_state(p, true);
> +		npu_set_fence_state(phb, true);
>   	} else {
>   		/* Cause a freeze with an invalid MMIO read.  If the BAR is not
>   		 * enabled, this will checkstop the machine.
> @@ -1012,6 +1014,7 @@ static const struct phb_ops npu_ops = {
>   	.get_diag_data2		= NULL,
>   	.set_capi_mode		= NULL,
>   	.set_capp_recovery	= NULL,
> +	.set_fence_state	= npu_set_fence_state,
>   };
>   
>   static void assign_mmio_bars(uint32_t gcid, uint32_t xscom,
> diff --git a/include/npu.h b/include/npu.h
> index 50cc9c9fc..45818a28f 100644
> --- a/include/npu.h
> +++ b/include/npu.h
> @@ -153,7 +153,6 @@ int64_t npu_dev_procedure(void *dev, struct pci_cfg_reg_filter *pcrf,
>   			  uint32_t offset, uint32_t len, uint32_t *data,
>   			  bool write);
>   
> -void npu_set_fence_state(struct npu *p, bool fence);
>   void npu_dev_procedure_reset(struct npu_dev *dev);
>   
>   #define NPUDBG(p, fmt, a...)	prlog(PR_DEBUG, "NPU%d: " fmt, \
> diff --git a/include/pci.h b/include/pci.h
> index caae74431..101442490 100644
> --- a/include/pci.h
> +++ b/include/pci.h
> @@ -340,6 +340,9 @@ struct phb_ops {
>   	/* Get/set PBCQ Tunnel BAR register */
>   	void (*get_tunnel_bar)(struct phb *phb, uint64_t *addr);
>   	int64_t (*set_tunnel_bar)(struct phb *phb, uint64_t addr);
> +
> +	/* Currently only used by NPU HMI code */
> +	void (*set_fence_state)(struct phb *phb, bool fence);
>   };
>   
>   enum phb_type {
>
Nicholas Piggin Dec. 20, 2021, 6:11 a.m. UTC | #2 
Excerpts from Cédric Le Goater's message of December 18, 2021 1:26 am:
> On 12/17/21 03:36, Nicholas Piggin wrote:
>> From: Stewart Smith <stewart@flamingspork.com>
>> 
>> This lets us consider not building in npu.o
> 
> I would instead introduce an empty stub for npu_set_fence_state()
> in npu.h.

hmi.c has explicit npu code already, so ok I'll do that.

Would be best to move all the npu and capp checkstop / fir handling into 
relevant files and then maybe a new phb checkstop handling ops function
would be justified. But that can be later.

Thanks,
Nick

> 
> Thanks,
> 
> C.
> 
>> Reviewed-by: Dan Horák <dan@danny.cz>
>> Signed-off-by: Stewart Smith <stewart@flamingspork.com>
>> ---
>>   core/hmi.c    | 2 +-
>>   hw/npu.c      | 7 +++++--
>>   include/npu.h | 1 -
>>   include/pci.h | 3 +++
>>   4 files changed, 9 insertions(+), 4 deletions(-)
>> 
>> diff --git a/core/hmi.c b/core/hmi.c
>> index ce5abd7d6..fe3d82529 100644
>> --- a/core/hmi.c
>> +++ b/core/hmi.c
>> @@ -908,7 +908,7 @@ static void find_npu_checkstop_reason(int flat_chip_id,
>>   
>>   		if (phb->phb_type == phb_type_pcie_v3) {
>>   			/* Set the NPU to fenced since it can't recover. */
>> -			npu_set_fence_state(phb_to_npu(phb), true);
>> +			phb->ops->set_fence_state(phb, true);
>>   		}
>>   
>>   		/* Set up the HMI event */
>> diff --git a/hw/npu.c b/hw/npu.c
>> index 35e6372d2..542f37397 100644
>> --- a/hw/npu.c
>> +++ b/hw/npu.c
>> @@ -925,7 +925,9 @@ static int64_t npu_eeh_next_error(struct phb *phb,
>>   }
>>   
>>   /* For use in error injection and handling. */
>> -void npu_set_fence_state(struct npu *p, bool fence) {
>> +static void npu_set_fence_state(struct phb *phb, bool fence) {
>> +	struct npu *p = phb_to_npu(phb);
>> +
>>   	p->fenced = fence;
>>   
>>   	if (fence)
>> @@ -968,7 +970,7 @@ static int64_t npu_err_inject(struct phb *phb, uint64_t pe_number,
>>   		return OPAL_PARAMETER;
>>   	} else if (type == 1) {
>>   		/* Emulate fence mode. */
>> -		npu_set_fence_state(p, true);
>> +		npu_set_fence_state(phb, true);
>>   	} else {
>>   		/* Cause a freeze with an invalid MMIO read.  If the BAR is not
>>   		 * enabled, this will checkstop the machine.
>> @@ -1012,6 +1014,7 @@ static const struct phb_ops npu_ops = {
>>   	.get_diag_data2		= NULL,
>>   	.set_capi_mode		= NULL,
>>   	.set_capp_recovery	= NULL,
>> +	.set_fence_state	= npu_set_fence_state,
>>   };
>>   
>>   static void assign_mmio_bars(uint32_t gcid, uint32_t xscom,
>> diff --git a/include/npu.h b/include/npu.h
>> index 50cc9c9fc..45818a28f 100644
>> --- a/include/npu.h
>> +++ b/include/npu.h
>> @@ -153,7 +153,6 @@ int64_t npu_dev_procedure(void *dev, struct pci_cfg_reg_filter *pcrf,
>>   			  uint32_t offset, uint32_t len, uint32_t *data,
>>   			  bool write);
>>   
>> -void npu_set_fence_state(struct npu *p, bool fence);
>>   void npu_dev_procedure_reset(struct npu_dev *dev);
>>   
>>   #define NPUDBG(p, fmt, a...)	prlog(PR_DEBUG, "NPU%d: " fmt, \
>> diff --git a/include/pci.h b/include/pci.h
>> index caae74431..101442490 100644
>> --- a/include/pci.h
>> +++ b/include/pci.h
>> @@ -340,6 +340,9 @@ struct phb_ops {
>>   	/* Get/set PBCQ Tunnel BAR register */
>>   	void (*get_tunnel_bar)(struct phb *phb, uint64_t *addr);
>>   	int64_t (*set_tunnel_bar)(struct phb *phb, uint64_t addr);
>> +
>> +	/* Currently only used by NPU HMI code */
>> +	void (*set_fence_state)(struct phb *phb, bool fence);
>>   };
>>   
>>   enum phb_type {
>> 
> 
>
diff mbox series

Patch

diff --git a/core/hmi.c b/core/hmi.c
index ce5abd7d6..fe3d82529 100644
--- a/core/hmi.c
+++ b/core/hmi.c
@@ -908,7 +908,7 @@  static void find_npu_checkstop_reason(int flat_chip_id,
 
 		if (phb->phb_type == phb_type_pcie_v3) {
 			/* Set the NPU to fenced since it can't recover. */
-			npu_set_fence_state(phb_to_npu(phb), true);
+			phb->ops->set_fence_state(phb, true);
 		}
 
 		/* Set up the HMI event */
diff --git a/hw/npu.c b/hw/npu.c
index 35e6372d2..542f37397 100644
--- a/hw/npu.c
+++ b/hw/npu.c
@@ -925,7 +925,9 @@  static int64_t npu_eeh_next_error(struct phb *phb,
 }
 
 /* For use in error injection and handling. */
-void npu_set_fence_state(struct npu *p, bool fence) {
+static void npu_set_fence_state(struct phb *phb, bool fence) {
+	struct npu *p = phb_to_npu(phb);
+
 	p->fenced = fence;
 
 	if (fence)
@@ -968,7 +970,7 @@  static int64_t npu_err_inject(struct phb *phb, uint64_t pe_number,
 		return OPAL_PARAMETER;
 	} else if (type == 1) {
 		/* Emulate fence mode. */
-		npu_set_fence_state(p, true);
+		npu_set_fence_state(phb, true);
 	} else {
 		/* Cause a freeze with an invalid MMIO read.  If the BAR is not
 		 * enabled, this will checkstop the machine.
@@ -1012,6 +1014,7 @@  static const struct phb_ops npu_ops = {
 	.get_diag_data2		= NULL,
 	.set_capi_mode		= NULL,
 	.set_capp_recovery	= NULL,
+	.set_fence_state	= npu_set_fence_state,
 };
 
 static void assign_mmio_bars(uint32_t gcid, uint32_t xscom,
diff --git a/include/npu.h b/include/npu.h
index 50cc9c9fc..45818a28f 100644
--- a/include/npu.h
+++ b/include/npu.h
@@ -153,7 +153,6 @@  int64_t npu_dev_procedure(void *dev, struct pci_cfg_reg_filter *pcrf,
 			  uint32_t offset, uint32_t len, uint32_t *data,
 			  bool write);
 
-void npu_set_fence_state(struct npu *p, bool fence);
 void npu_dev_procedure_reset(struct npu_dev *dev);
 
 #define NPUDBG(p, fmt, a...)	prlog(PR_DEBUG, "NPU%d: " fmt, \
diff --git a/include/pci.h b/include/pci.h
index caae74431..101442490 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -340,6 +340,9 @@  struct phb_ops {
 	/* Get/set PBCQ Tunnel BAR register */
 	void (*get_tunnel_bar)(struct phb *phb, uint64_t *addr);
 	int64_t (*set_tunnel_bar)(struct phb *phb, uint64_t addr);
+
+	/* Currently only used by NPU HMI code */
+	void (*set_fence_state)(struct phb *phb, bool fence);
 };
 
 enum phb_type {