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[115.64.153.41]) by smtp.gmail.com with ESMTPSA id z3sm11158058pfe.78.2021.10.02.18.22.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Oct 2021 18:22:21 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sun, 3 Oct 2021 11:22:05 +1000 Message-Id: <20211003012210.1165606-4-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211003012210.1165606-1-npiggin@gmail.com> References: <20211003012210.1165606-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 3/8] cpu: add debug check in cpu_relax X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" If cpu_relax() is called when not at medium SMT priority, it will lose the prior priority and return at medium. Add a debug check to catch this, which would have flagged the previous bug. Signed-off-by: Nicholas Piggin --- core/cpu.c | 6 ++++++ include/processor.h | 1 + 2 files changed, 7 insertions(+) diff --git a/core/cpu.c b/core/cpu.c index 5c10fc6e8..0f2da1524 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -80,6 +80,12 @@ unsigned long __attrconst cpu_emergency_stack_top(unsigned int pir) void __nomcount cpu_relax(void) { + if ((mfspr(SPR_PPR32) >> 18) != 0x4) { + printf("cpu_relax called when not at medium SMT priority: " + "PPR[PRI]=0x%lx\n", mfspr(SPR_PPR32) >> 18); + backtrace(); + } + /* Relax a bit to give sibling threads some breathing space */ smt_lowest(); asm volatile("nop; nop; nop; nop;\n" diff --git a/include/processor.h b/include/processor.h index 973d7e77b..7a9c49994 100644 --- a/include/processor.h +++ b/include/processor.h @@ -71,6 +71,7 @@ #define SPR_USRR1 0x1fb /* RW: Ultravisor Save/Restore Register 1 */ #define SPR_SMFCTRL 0x1ff /* RW: Secure Memory Facility Control */ #define SPR_PSSCR 0x357 /* RW: Stop status and control (ISA 3) */ +#define SPR_PPR32 0x382 #define SPR_TSCR 0x399 #define SPR_HID0 0x3f0 #define SPR_HID1 0x3f1