diff mbox series

[01/16,01/16] opencapi5: move opal api

Message ID 20210820094557.29743-2-clombard@linux.vnet.ibm.com
State Superseded
Headers show
Series OpenCAPI 5.0 Support for P10 | expand

Commit Message

Christophe Lombard Aug. 20, 2021, 9:45 a.m. UTC 
Move the OPAL entry points for npu2 opencapi to the common opal NPU
file. This prepares us to add same entries for PAU opencapi in this common
file.

No functional change.

Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
---
 hw/npu-opal.c      | 67 ++++++++++++++++++++++++++++++++++++++++++++++
 hw/npu2-opencapi.c | 35 ++++--------------------
 include/npu2.h     |  7 +++++
 3 files changed, 79 insertions(+), 30 deletions(-)

Comments

Frederic Barrat Sept. 8, 2021, 12:16 p.m. UTC | #1 
On 20/08/2021 11:45, Christophe Lombard wrote:
> Move the OPAL entry points for npu2 opencapi to the common opal NPU
> file. This prepares us to add same entries for PAU opencapi in this common
> file.
> 
> No functional change.
> 
> Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
> ---
>   hw/npu-opal.c      | 67 ++++++++++++++++++++++++++++++++++++++++++++++
>   hw/npu2-opencapi.c | 35 ++++--------------------
>   include/npu2.h     |  7 +++++
>   3 files changed, 79 insertions(+), 30 deletions(-)
> 
> diff --git a/hw/npu-opal.c b/hw/npu-opal.c
> index 412ea460..64e36852 100644
> --- a/hw/npu-opal.c
> +++ b/hw/npu-opal.c
> @@ -174,3 +174,70 @@ static int64_t opal_npu_get_relaxed_order(uint64_t phb_id,
>   	return phb4->ro_state;
>   }
>   opal_call(OPAL_NPU_GET_RELAXED_ORDER, opal_npu_get_relaxed_order, 2);
> +
> +#define MAX_PE_HANDLE	((1 << 15) - 1)
> +
> +static int64_t opal_npu_spa_setup(uint64_t phb_id, uint32_t bdfn,
> +				  uint64_t addr, uint64_t PE_mask)
> +{
> +	struct phb *phb = pci_get_phb(phb_id);
> +	int64_t rc = OPAL_SUCCESS;
> +
> +	if (!phb)
> +		return OPAL_PARAMETER;
> +
> +	/* 4k aligned */
> +	if (addr & 0xFFF)
> +		return OPAL_PARAMETER;
> +
> +	if (PE_mask > 15)
> +		return OPAL_PARAMETER;
> +
> +	if (phb->phb_type == phb_type_npu_v2_opencapi)
> +		rc = npu2_opencapi_spa_setup(phb, bdfn, addr, PE_mask);
> +	else
> +		return OPAL_PARAMETER;
> +
> +	return rc;


That seems a bit convoluted, that last line is useless.  That pattern 
will be repeated, with a few twists, in later patches. We should just 
use the same pattern on all the opal calls. See more on patch "Add 
support for OpenCAPI Persistent Memory devices."




> diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c
> index 035c6cdc..686f2e22 100644
> --- a/hw/npu2-opencapi.c
> +++ b/hw/npu2-opencapi.c

> -static int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t __unused bdfn,
> -			long capabilities, uint64_t rate_phys, int rate_sz)
> +int64_t npu2_opencapi_tl_set(struct phb *phb, uint32_t __unused bdfn,
> +		    long capabilities, uint64_t rate_phys, int rate_sz)
>   {
> -	struct phb *phb = pci_get_phb(phb_id);
>   	struct npu2_dev *dev;
>   	uint64_t stack, block, reg, templ_rate;
>   	int i, rate_pos;
>   	char *rate = (char *) rate_phys;
> 
> -	if (!phb || phb->phb_type != phb_type_npu_v2_opencapi)
> -		return OPAL_PARAMETER;
>   	if (!opal_addr_valid(rate) || rate_sz != TL_RATE_BUF_SIZE)
>   		return OPAL_PARAMETER;

For all the other opal calls, the argument verification is done in the 
front-end (npu-opal.c), except here for rate and rate_sz. No big deal, 
but it looks a bit odd.

   Fred


> 
> @@ -2157,7 +2133,6 @@ static int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t __unused bdfn,
>   	OCAPIDBG(dev, "OTL configuration 1 register set to %llx\n", reg);
>   	return OPAL_SUCCESS;
>   }
> -opal_call(OPAL_NPU_TL_SET, opal_npu_tl_set, 5);
> 
>   static void set_mem_bar(struct npu2_dev *dev, uint64_t base, uint64_t size)
>   {
> diff --git a/include/npu2.h b/include/npu2.h
> index eb7c4558..f48a68b6 100644
> --- a/include/npu2.h
> +++ b/include/npu2.h
> @@ -271,4 +271,11 @@ static inline int npu2_get_phb_index(unsigned int brick_index)
>   	return NPU2_PHB_INDEX_BASE + brick_index;
>   }
> 
> +int64_t npu2_opencapi_spa_setup(struct phb *phb, uint32_t __unused bdfn,
> +				uint64_t addr, uint64_t PE_mask);
> +int64_t npu2_opencapi_spa_clear_cache(struct phb *phb, uint32_t __unused bdfn,
> +				      uint64_t PE_handle);
> +int64_t npu2_opencapi_tl_set(struct phb *phb, uint32_t __unused bdfn,
> +		    long capabilities, uint64_t rate_phys, int rate_sz);
> +
>   #endif /* __NPU2_H */
>
diff mbox series

Patch

diff --git a/hw/npu-opal.c b/hw/npu-opal.c
index 412ea460..64e36852 100644
--- a/hw/npu-opal.c
+++ b/hw/npu-opal.c
@@ -174,3 +174,70 @@  static int64_t opal_npu_get_relaxed_order(uint64_t phb_id,
 	return phb4->ro_state;
 }
 opal_call(OPAL_NPU_GET_RELAXED_ORDER, opal_npu_get_relaxed_order, 2);
+
+#define MAX_PE_HANDLE	((1 << 15) - 1)
+
+static int64_t opal_npu_spa_setup(uint64_t phb_id, uint32_t bdfn,
+				  uint64_t addr, uint64_t PE_mask)
+{
+	struct phb *phb = pci_get_phb(phb_id);
+	int64_t rc = OPAL_SUCCESS;
+
+	if (!phb)
+		return OPAL_PARAMETER;
+
+	/* 4k aligned */
+	if (addr & 0xFFF)
+		return OPAL_PARAMETER;
+
+	if (PE_mask > 15)
+		return OPAL_PARAMETER;
+
+	if (phb->phb_type == phb_type_npu_v2_opencapi)
+		rc = npu2_opencapi_spa_setup(phb, bdfn, addr, PE_mask);
+	else
+		return OPAL_PARAMETER;
+
+	return rc;
+}
+opal_call(OPAL_NPU_SPA_SETUP, opal_npu_spa_setup, 4);
+
+static int64_t opal_npu_spa_clear_cache(uint64_t phb_id, uint32_t bdfn,
+					uint64_t PE_handle)
+{
+	struct phb *phb = pci_get_phb(phb_id);
+	int64_t rc = OPAL_SUCCESS;
+
+	if (!phb)
+		return OPAL_PARAMETER;
+
+	if (PE_handle > MAX_PE_HANDLE)
+		return OPAL_PARAMETER;
+
+	if (phb->phb_type == phb_type_npu_v2_opencapi)
+		rc = npu2_opencapi_spa_clear_cache(phb, bdfn, PE_handle);
+	else
+		return OPAL_PARAMETER;
+
+	return rc;
+}
+opal_call(OPAL_NPU_SPA_CLEAR_CACHE, opal_npu_spa_clear_cache, 3);
+
+static int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t bdfn,
+		    long capabilities, uint64_t rate_phys, int rate_sz)
+{
+	struct phb *phb = pci_get_phb(phb_id);
+	int64_t rc = OPAL_SUCCESS;
+
+	if (!phb)
+		return OPAL_PARAMETER;
+
+	if (phb->phb_type == phb_type_npu_v2_opencapi)
+		rc = npu2_opencapi_tl_set(phb, bdfn, capabilities,
+					  rate_phys, rate_sz);
+	else
+		return OPAL_PARAMETER;
+
+	return rc;
+}
+opal_call(OPAL_NPU_TL_SET, opal_npu_tl_set, 5);
diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c
index 035c6cdc..686f2e22 100644
--- a/hw/npu2-opencapi.c
+++ b/hw/npu2-opencapi.c
@@ -1957,24 +1957,13 @@  void npu2_opencapi_set_broken(struct npu2 *npu, int brick)
 	}
 }
 
-static int64_t opal_npu_spa_setup(uint64_t phb_id, uint32_t __unused bdfn,
+int64_t npu2_opencapi_spa_setup(struct phb *phb, uint32_t __unused bdfn,
 				uint64_t addr, uint64_t PE_mask)
 {
 	uint64_t stack, block, offset, reg;
-	struct phb *phb = pci_get_phb(phb_id);
 	struct npu2_dev *dev;
 	int rc;
 
-	if (!phb || phb->phb_type != phb_type_npu_v2_opencapi)
-		return OPAL_PARAMETER;
-
-	/* 4k aligned */
-	if (addr & 0xFFF)
-		return OPAL_PARAMETER;
-
-	if (PE_mask > 15)
-		return OPAL_PARAMETER;
-
 	dev = phb_to_npu2_dev_ocapi(phb);
 	if (!dev)
 		return OPAL_PARAMETER;
@@ -1986,7 +1975,6 @@  static int64_t opal_npu_spa_setup(uint64_t phb_id, uint32_t __unused bdfn,
 	else
 		offset = NPU2_XSL_PSL_SPAP_A0;
 
-
 	lock(&dev->npu->lock);
 	/*
 	 * set the SPAP used by the device
@@ -2024,22 +2012,14 @@  out:
 	unlock(&dev->npu->lock);
 	return rc;
 }
-opal_call(OPAL_NPU_SPA_SETUP, opal_npu_spa_setup, 4);
 
-static int64_t opal_npu_spa_clear_cache(uint64_t phb_id, uint32_t __unused bdfn,
-					uint64_t PE_handle)
+int64_t npu2_opencapi_spa_clear_cache(struct phb *phb, uint32_t __unused bdfn,
+				      uint64_t PE_handle)
 {
 	uint64_t cc_inv, stack, block, reg, rc;
 	uint32_t retries = 5;
-	struct phb *phb = pci_get_phb(phb_id);
 	struct npu2_dev *dev;
 
-	if (!phb || phb->phb_type != phb_type_npu_v2_opencapi)
-		return OPAL_PARAMETER;
-
-	if (PE_handle > MAX_PE_HANDLE)
-		return OPAL_PARAMETER;
-
 	dev = phb_to_npu2_dev_ocapi(phb);
 	if (!dev)
 		return OPAL_PARAMETER;
@@ -2077,7 +2057,6 @@  out:
 	unlock(&dev->npu->lock);
 	return rc;
 }
-opal_call(OPAL_NPU_SPA_CLEAR_CACHE, opal_npu_spa_clear_cache, 3);
 
 static int get_template_rate(unsigned int templ, char *rate_buf)
 {
@@ -2101,17 +2080,14 @@  static bool is_template_supported(unsigned int templ, long capabilities)
 	return !!(capabilities & (1ull << templ));
 }
 
-static int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t __unused bdfn,
-			long capabilities, uint64_t rate_phys, int rate_sz)
+int64_t npu2_opencapi_tl_set(struct phb *phb, uint32_t __unused bdfn,
+		    long capabilities, uint64_t rate_phys, int rate_sz)
 {
-	struct phb *phb = pci_get_phb(phb_id);
 	struct npu2_dev *dev;
 	uint64_t stack, block, reg, templ_rate;
 	int i, rate_pos;
 	char *rate = (char *) rate_phys;
 
-	if (!phb || phb->phb_type != phb_type_npu_v2_opencapi)
-		return OPAL_PARAMETER;
 	if (!opal_addr_valid(rate) || rate_sz != TL_RATE_BUF_SIZE)
 		return OPAL_PARAMETER;
 
@@ -2157,7 +2133,6 @@  static int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t __unused bdfn,
 	OCAPIDBG(dev, "OTL configuration 1 register set to %llx\n", reg);
 	return OPAL_SUCCESS;
 }
-opal_call(OPAL_NPU_TL_SET, opal_npu_tl_set, 5);
 
 static void set_mem_bar(struct npu2_dev *dev, uint64_t base, uint64_t size)
 {
diff --git a/include/npu2.h b/include/npu2.h
index eb7c4558..f48a68b6 100644
--- a/include/npu2.h
+++ b/include/npu2.h
@@ -271,4 +271,11 @@  static inline int npu2_get_phb_index(unsigned int brick_index)
 	return NPU2_PHB_INDEX_BASE + brick_index;
 }
 
+int64_t npu2_opencapi_spa_setup(struct phb *phb, uint32_t __unused bdfn,
+				uint64_t addr, uint64_t PE_mask);
+int64_t npu2_opencapi_spa_clear_cache(struct phb *phb, uint32_t __unused bdfn,
+				      uint64_t PE_handle);
+int64_t npu2_opencapi_tl_set(struct phb *phb, uint32_t __unused bdfn,
+		    long capabilities, uint64_t rate_phys, int rate_sz);
+
 #endif /* __NPU2_H */