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Wed, 4 Aug 2021 07:23:29 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:29 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:29 +0530 Message-Id: <20210804072137.1147875-52-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: Vp9jnA4vs2hIG_IH95e62M4DJBOZOJ_3 X-Proofpoint-GUID: Vp9jnA4vs2hIG_IH95e62M4DJBOZOJ_3 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 phishscore=0 mlxscore=0 spamscore=0 suspectscore=0 impostorscore=0 mlxlogscore=877 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 51/59] phb5: Enable Gen5 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Neuling Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Michael Neuling Registers for Gen5 have been initialized in a previous patch. So let's activate it! Signed-off-by: Michael Neuling Signed-off-by: Vasant Hegde --- hw/phb4.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index 0e98042ce..9bc8d47ee 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -3008,12 +3008,16 @@ static int64_t phb4_poll_link(struct pci_slot *slot) static unsigned int phb4_get_max_link_speed(struct phb4 *p, struct dt_node *np) { - unsigned int max_link_speed; + unsigned int max_link_speed, hw_max_link_speed; struct proc_chip *chip; chip = get_chip(p->chip_id); + hw_max_link_speed = 4; + if (is_phb5()) + hw_max_link_speed = 5; + /* Priority order: NVRAM -> dt -> GEN3 dd2.00 -> GEN4 */ - max_link_speed = 4; + max_link_speed = hw_max_link_speed; if (p->rev == PHB4_REV_NIMBUS_DD20 && ((0xf & chip->ec_level) == 0) && chip->ec_rev == 0) max_link_speed = 3; @@ -3033,8 +3037,8 @@ static unsigned int phb4_get_max_link_speed(struct phb4 *p, struct dt_node *np) } if (pcie_max_link_speed) max_link_speed = pcie_max_link_speed; - if (max_link_speed > 4) /* clamp to 4 */ - max_link_speed = 4; + if (max_link_speed > hw_max_link_speed) + max_link_speed = hw_max_link_speed; return max_link_speed; }