diff mbox series

[v2,50/59] phb5: Add register inits specific to Gen5

Message ID 20210804072137.1147875-51-hegdevasant@linux.vnet.ibm.com
State Accepted
Headers show
Series P10 Enablement | expand

Commit Message

Vasant Hegde Aug. 4, 2021, 7:21 a.m. UTC 
From: Frederic Barrat <fbarrat@linux.ibm.com>

Update init sequence to take into account Gen5.
Define default equlization settings if HDAT is not used.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
---
 hw/phb4.c           | 18 +++++++++++++-----
 include/phb4-regs.h |  6 ++++--
 2 files changed, 17 insertions(+), 7 deletions(-)
diff mbox series

Patch

diff --git a/hw/phb4.c b/hw/phb4.c
index 6700c7fbb..0e98042ce 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -5387,8 +5387,12 @@  static void phb4_init_hw(struct phb4 *p)
 		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL1, be64_to_cpu(p->lane_eq[1]));
 		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL2, be64_to_cpu(p->lane_eq[2]));
 		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL3, be64_to_cpu(p->lane_eq[3]));
-		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL20, be64_to_cpu(p->lane_eq[4]));
-		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL21, be64_to_cpu(p->lane_eq[5]));
+		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL40, be64_to_cpu(p->lane_eq[4]));
+		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL41, be64_to_cpu(p->lane_eq[5]));
+		if (is_phb5()) {
+			out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL50, be64_to_cpu(p->lane_eq[6]));
+			out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL51, be64_to_cpu(p->lane_eq[7]));
+		}
 	}
 	if (!p->lane_eq_en) {
 		/* Read modify write and set to 2 bits */
@@ -5830,7 +5834,7 @@  static __be64 lane_eq_phb5_default[8] = {
 	CPU_TO_BE64(0x4444444444444444UL), CPU_TO_BE64(0x4444444444444444UL),
 	CPU_TO_BE64(0x4444444444444444UL), CPU_TO_BE64(0x4444444444444444UL),
 	CPU_TO_BE64(0x4444444444444444UL), CPU_TO_BE64(0x4444444444444444UL),
-	CPU_TO_BE64(0x4444444444444444UL), CPU_TO_BE64(0x4444444444444444UL),
+	CPU_TO_BE64(0x9999999999999999UL), CPU_TO_BE64(0x9999999999999999UL),
 };
 
 static void phb4_create(struct dt_node *np)
@@ -5842,7 +5846,7 @@  static void phb4_create(struct dt_node *np)
 	struct dt_node *iplp;
 	char *path;
 	uint32_t irq_base, irq_flags;
-	int i;
+	int i, eq_reg_count;
 	int chip_id;
 
 	chip_id = dt_prop_get_u32(np, "ibm,chip-id");
@@ -5942,7 +5946,11 @@  static void phb4_create(struct dt_node *np)
 	/* Check for lane equalization values from HB or HDAT */
 	p->lane_eq_en = true;
 	p->lane_eq = dt_prop_get_def_size(np, "ibm,lane-eq", NULL, &lane_eq_len);
-	lane_eq_len_req = 6 * 8;
+	if (is_phb5())
+		eq_reg_count = 8;
+	else
+		eq_reg_count = 6;
+	lane_eq_len_req = eq_reg_count * 8;
 	if (p->lane_eq) {
 		if (lane_eq_len < lane_eq_len_req) {
 			PHBERR(p, "Device-tree has ibm,lane-eq too short: %ld"
diff --git a/include/phb4-regs.h b/include/phb4-regs.h
index 99633e103..8ab78c377 100644
--- a/include/phb4-regs.h
+++ b/include/phb4-regs.h
@@ -295,8 +295,10 @@ 
 #define PHB_PCIE_LANE_EQ_CNTL1		0x1AD8
 #define PHB_PCIE_LANE_EQ_CNTL2		0x1AE0
 #define PHB_PCIE_LANE_EQ_CNTL3		0x1AE8
-#define PHB_PCIE_LANE_EQ_CNTL20		0x1AF0
-#define PHB_PCIE_LANE_EQ_CNTL21		0x1AF8
+#define PHB_PCIE_LANE_EQ_CNTL40		0x1AF0
+#define PHB_PCIE_LANE_EQ_CNTL41		0x1AF8
+#define PHB_PCIE_LANE_EQ_CNTL50		0x1B00
+#define PHB_PCIE_LANE_EQ_CNTL51		0x1B08
 #define PHB_PCIE_TRACE_CTRL		0x1B20
 #define PHB_PCIE_MISC_STRAP		0x1B30
 #define PHB_PCIE_PDL_PHY_EQ_CNTL	0x1B38