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Wed, 4 Aug 2021 07:23:05 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:04 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:15 +0530 Message-Id: <20210804072137.1147875-38-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: guwxLAQZ_1DBiB--nSPpA5Oz_jX6JFFd X-Proofpoint-ORIG-GUID: guwxLAQZ_1DBiB--nSPpA5Oz_jX6JFFd X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 mlxscore=0 clxscore=1015 impostorscore=0 spamscore=0 mlxlogscore=999 malwarescore=0 bulkscore=0 priorityscore=1501 adultscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 37/59] psi/p10: Introduce xive2_source_mask() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Cédric Le Goater Commit fa161cd89fbf ("hw/psi-p9: Mask OPAL-owned LSIs without handlers") introduced xive_source_mask(). Do the same for P10. Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- hw/psi.c | 11 ++++++++++- hw/xive2.c | 7 +++++++ include/xive.h | 2 ++ 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/hw/psi.c b/hw/psi.c index 291422539..e9b8e2ea7 100644 --- a/hw/psi.c +++ b/hw/psi.c @@ -564,7 +564,16 @@ static void psi_p9_mask_unhandled_irq(struct irq_source *is, uint32_t isn) * have a handler for the interrupt then it needs to be masked to * prevent the IRQ from locking up the thread which handles it. */ - xive_source_mask(is, isn); + switch (proc_gen) { + case proc_gen_p9: + xive_source_mask(is, isn); + break; + case proc_gen_p10: + xive2_source_mask(is, isn); + return; + default: + assert(false); + } } diff --git a/hw/xive2.c b/hw/xive2.c index cba050fa1..f565be1fd 100644 --- a/hw/xive2.c +++ b/hw/xive2.c @@ -2532,6 +2532,13 @@ static char *xive_source_name(struct irq_source *is, uint32_t isn) return s->orig_ops->name(is, isn); } +void xive2_source_mask(struct irq_source *is, uint32_t isn) +{ + struct xive_src *s = container_of(is, struct xive_src, is); + + xive_update_irq_mask(s, isn - s->esb_base, true); +} + static const struct irq_source_ops xive_irq_source_ops = { .interrupt = xive_source_interrupt, .attributes = xive_source_attributes, diff --git a/include/xive.h b/include/xive.h index faaef2aeb..8d5fbeddb 100644 --- a/include/xive.h +++ b/include/xive.h @@ -91,6 +91,8 @@ uint64_t xive2_get_esb_base(uint32_t girq); void xive2_cpu_callin(struct cpu_thread *cpu); void *xive2_get_trigger_port(uint32_t girq); +void xive2_source_mask(struct irq_source *is, uint32_t isn); + void xive2_cpu_reset(void); void xive2_late_init(void);