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Mon, 19 Jul 2021 13:22:00 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.86.230]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 19 Jul 2021 13:22:00 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Mon, 19 Jul 2021 18:49:57 +0530 Message-Id: <20210719132012.150948-47-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210719132012.150948-1-hegdevasant@linux.vnet.ibm.com> References: <20210719132012.150948-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: Zh7DPMdtW2zeq1Kb__k-SWBVoSAvBf-e X-Proofpoint-ORIG-GUID: Zh7DPMdtW2zeq1Kb__k-SWBVoSAvBf-e X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-19_05:2021-07-19, 2021-07-19 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 malwarescore=0 impostorscore=0 mlxscore=0 phishscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=710 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2107190076 Subject: [Skiboot] [PATCH 46/61] xive/p10: Activate has_array when PQ_disable is available X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Cédric Le Goater hash_array is an Internal cache hashing optimization. It tracks for ESBs where the original trigger came from so that we avoid getting the EAS into the cache twice. Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- hw/xive2.c | 11 ++++++++--- include/xive2-regs.h | 2 ++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/hw/xive2.c b/hw/xive2.c index 23b3cdc2f..d9894a071 100644 --- a/hw/xive2.c +++ b/hw/xive2.c @@ -1615,15 +1615,20 @@ static bool xive_cfg_save_restore(struct xive *x) * 1/3rd of the cache is reserved for PHB ESBs and the rest to * IPIs. This is sufficient to keep all the PHB ESBs in cache and * avoid ESB cache misses during IO interrupt processing. + * + * hash_array_enable : + * Internal cache hashing optimization. The hash_array tracks for + * ESBs where the original trigger came from so that we avoid + * getting the EAS into the cache twice. */ static void xive_config_esb_cache(struct xive *x) { uint64_t val = xive_regr(x, VC_ESBC_CFG); if (xive_has_cap(x, CQ_XIVE_CAP_PHB_PQ_DISABLE)) { - val |= VC_ESBC_CFG_SPLIT_MODE; - xive_dbg(x, "ESB cache configured with split mode. " - "VC_ESBC_CFG=%016llx\n", val); + val |= VC_ESBC_CFG_SPLIT_MODE | VC_ESBC_CFG_HASH_ARRAY_ENABLE; + xive_dbg(x, "ESB cache configured with split mode " + "and hash array. VC_ESBC_CFG=%016llx\n", val); } else val &= ~VC_ESBC_CFG_SPLIT_MODE; diff --git a/include/xive2-regs.h b/include/xive2-regs.h index 4638c3d89..c2ed265f6 100644 --- a/include/xive2-regs.h +++ b/include/xive2-regs.h @@ -230,6 +230,8 @@ /* ESBC configuration */ #define X_VC_ESBC_CFG 0x148 #define VC_ESBC_CFG 0x240 +#define VC_ESBC_CFG_HASH_ARRAY_ENABLE PPC_BIT(40) +#define VC_ESBC_CFG_HASH_STORE_MODE PPC_BITMASK(41,42) #define VC_ESBC_CFG_SPLIT_MODE PPC_BIT(56) /* EASC flush control register */