Message ID | 20210719132012.150948-46-hegdevasant@linux.vnet.ibm.com |
---|---|
State | Superseded |
Headers | show
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Mon, 19 Jul 2021 13:21:58 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.86.230]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 19 Jul 2021 13:21:58 +0000 (GMT) From: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> To: skiboot@lists.ozlabs.org Date: Mon, 19 Jul 2021 18:49:56 +0530 Message-Id: <20210719132012.150948-46-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210719132012.150948-1-hegdevasant@linux.vnet.ibm.com> References: <20210719132012.150948-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: jmgZBkb_-FJNebEVKpO8E-hpPBmqzd3o X-Proofpoint-ORIG-GUID: jmgZBkb_-FJNebEVKpO8E-hpPBmqzd3o X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-19_05:2021-07-19, 2021-07-19 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 malwarescore=0 bulkscore=0 phishscore=0 clxscore=1015 adultscore=0 mlxscore=0 spamscore=0 impostorscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2107190076 Subject: [Skiboot] [PATCH 45/61] xive/p10: Activate split mode for PHB ESBs when PQ_disable is available X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development <skiboot.lists.ozlabs.org> List-Unsubscribe: <https://lists.ozlabs.org/options/skiboot>, <mailto:skiboot-request@lists.ozlabs.org?subject=unsubscribe> List-Archive: <http://lists.ozlabs.org/pipermail/skiboot/> List-Post: <mailto:skiboot@lists.ozlabs.org> List-Help: <mailto:skiboot-request@lists.ozlabs.org?subject=help> List-Subscribe: <https://lists.ozlabs.org/listinfo/skiboot>, <mailto:skiboot-request@lists.ozlabs.org?subject=subscribe> Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" <skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org> |
Series |
P10 Enablement
|
expand
|
diff --git a/hw/xive2.c b/hw/xive2.c index cd6a4efe6..23b3cdc2f 100644 --- a/hw/xive2.c +++ b/hw/xive2.c @@ -1607,6 +1607,29 @@ static bool xive_cfg_save_restore(struct xive *x) return !!(x->config & CQ_XIVE_CFG_EN_VP_SAVE_RESTORE); } +/* + * When PQ_disable is available, configure the ESB cache to improve + * performance for PHB ESBs. + * + * split_mode : + * 1/3rd of the cache is reserved for PHB ESBs and the rest to + * IPIs. This is sufficient to keep all the PHB ESBs in cache and + * avoid ESB cache misses during IO interrupt processing. + */ +static void xive_config_esb_cache(struct xive *x) +{ + uint64_t val = xive_regr(x, VC_ESBC_CFG); + + if (xive_has_cap(x, CQ_XIVE_CAP_PHB_PQ_DISABLE)) { + val |= VC_ESBC_CFG_SPLIT_MODE; + xive_dbg(x, "ESB cache configured with split mode. " + "VC_ESBC_CFG=%016llx\n", val); + } else + val &= ~VC_ESBC_CFG_SPLIT_MODE; + + xive_regw(x, VC_ESBC_CFG, val); +} + static void xive_config_fused_core(struct xive *x) { uint64_t val = xive_regr(x, TCTXT_CFG); @@ -1722,6 +1745,8 @@ static bool xive_config_init(struct xive *x) xive_config_fused_core(x); + xive_config_esb_cache(x); + xive_config_reduced_priorities_fixup(x); return true; diff --git a/include/xive2-regs.h b/include/xive2-regs.h index ad1a9b79f..4638c3d89 100644 --- a/include/xive2-regs.h +++ b/include/xive2-regs.h @@ -227,6 +227,11 @@ #define VC_ESBC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(32,35) #define VC_ESBC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(36,63) /* 28-bit */ +/* ESBC configuration */ +#define X_VC_ESBC_CFG 0x148 +#define VC_ESBC_CFG 0x240 +#define VC_ESBC_CFG_SPLIT_MODE PPC_BIT(56) + /* EASC flush control register */ #define X_VC_EASC_FLUSH_CTRL 0x160 #define VC_EASC_FLUSH_CTRL 0x300