diff mbox series

[3/4] xive/p9: Introduce XIVE_ESB_PAGE_SIZE

Message ID 20201104222057.590816-4-clg@kaod.org
State Accepted
Headers show
Series xive/p9: small cleanups | expand

Checks

Context Check Description
snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot-dco success Signed-off-by present
snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot success Test snowpatch/job/snowpatch-skiboot on branch master
snowpatch_ozlabs/apply_patch success Successfully applied on branch master (89a32b4930be829f37e6967354a759e38048d01f)

Commit Message

Cédric Le Goater Nov. 4, 2020, 10:20 p.m. UTC
Rename XIVE_ESB_SIZE to XIVE_ESB_PAGE_SIZE in the xive/p9 driver to
be consistent with the xive2/p10 driver.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/xive.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)
diff mbox series

Patch

diff --git a/hw/xive.c b/hw/xive.c
index 34e211c3bf1a..af502fbfe79e 100644
--- a/hw/xive.c
+++ b/hw/xive.c
@@ -157,7 +157,7 @@ 
 
 /* Use 64K for everything by default */
 #define XIVE_ESB_SHIFT		(16 + 1) /* trigger + mgmt pages */
-#define XIVE_ESB_SIZE		(1ul << XIVE_ESB_SHIFT) /* 2 pages */
+#define XIVE_ESB_PAGE_SIZE	(1ul << XIVE_ESB_SHIFT) /* 2 pages */
 
 /* Max number of EQs. We allocate an indirect table big enough so
  * that when fully populated we can have that many EQs.
@@ -1102,7 +1102,7 @@  static void xive_scrub_workaround_eq(struct xive *x, uint32_t block __unused, ui
 	/* EQ variant of the workaround described in __xive_cache_scrub(),
 	 * a simple non-side effect load from ESn will do
 	 */
-	mmio = x->eq_mmio + idx * XIVE_ESB_SIZE;
+	mmio = x->eq_mmio + idx * XIVE_ESB_PAGE_SIZE;
 
 	/* Ensure the above has returned before we do anything else
 	 * the XIVE store queue is completely empty
@@ -1944,7 +1944,7 @@  void *xive_get_trigger_port(uint32_t girq)
 		    girq >= x->int_ipi_top)
 			return NULL;
 
-		return x->esb_mmio + idx * XIVE_ESB_SIZE;
+		return x->esb_mmio + idx * XIVE_ESB_PAGE_SIZE;
 	}
 }
 
@@ -2719,7 +2719,7 @@  static void xive_ipi_init(struct xive *x, struct cpu_thread *cpu)
 
 static void xive_ipi_eoi(struct xive *x, uint32_t idx)
 {
-	uint8_t *mm = x->esb_mmio + idx * XIVE_ESB_SIZE;
+	uint8_t *mm = x->esb_mmio + idx * XIVE_ESB_PAGE_SIZE;
 	uint8_t eoi_val;
 
 	/* For EOI, we use the special MMIO that does a clear of both
@@ -2736,7 +2736,7 @@  static void xive_ipi_eoi(struct xive *x, uint32_t idx)
 
 static void xive_ipi_trigger(struct xive *x, uint32_t idx)
 {
-	uint8_t *mm = x->esb_mmio + idx * XIVE_ESB_SIZE;
+	uint8_t *mm = x->esb_mmio + idx * XIVE_ESB_PAGE_SIZE;
 
 	xive_vdbg(x, "Trigger IPI 0x%x\n", idx);
 
@@ -2965,7 +2965,7 @@  static void xive_init_cpu_emulation(struct xive_cpu_state *xs,
 	xs->eqgen = 0;
 	x = xive_from_vc_blk(xs->eq_blk);
 	assert(x);
-	xs->eqmmio = x->eq_mmio + (xs->eq_idx + XIVE_EMULATION_PRIO) * XIVE_ESB_SIZE;
+	xs->eqmmio = x->eq_mmio + (xs->eq_idx + XIVE_EMULATION_PRIO) * XIVE_ESB_PAGE_SIZE;
 }
 
 static void xive_init_cpu_exploitation(struct xive_cpu_state *xs)
@@ -3837,7 +3837,7 @@  static int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio,
 	}
 	if (out_qeoi_page) {
 		*out_qeoi_page =
-			cpu_to_be64((uint64_t)x->eq_mmio + idx * XIVE_ESB_SIZE);
+			cpu_to_be64((uint64_t)x->eq_mmio + idx * XIVE_ESB_PAGE_SIZE);
 	}
 	if (out_qflags) {
 		*out_qflags = 0;
@@ -5028,7 +5028,7 @@  static int64_t __opal_xive_dump_emu(struct xive_cpu_state *xs, uint32_t pir)
 	      xs->eqbuf[(xs->eqptr + 2) & xs->eqmsk],
 	      xs->eqbuf[(xs->eqptr + 3) & xs->eqmsk]);
 
-	mm = xs->xive->esb_mmio + GIRQ_TO_IDX(xs->ipi_irq) * XIVE_ESB_SIZE;
+	mm = xs->xive->esb_mmio + GIRQ_TO_IDX(xs->ipi_irq) * XIVE_ESB_PAGE_SIZE;
 	pq = in_8(mm + 0x10800);
 	if (xive_get_irq_targetting(xs->ipi_irq, &ipi_target, NULL, NULL))
 		prlog(PR_INFO, "CPU[%04x]: IPI #%08x PQ=%x target=%08x\n",