diff mbox series

[RFC,3/6] xive/p9: Add debugfs entries for performance

Message ID 20200917163544.142593-4-clg@kaod.org
State RFC
Headers show
Series OPAL debugfs calls | expand

Checks

Context Check Description
snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot-dco success Signed-off-by present
snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot success Test snowpatch/job/snowpatch-skiboot on branch master
snowpatch_ozlabs/apply_patch success Successfully applied on branch master (d362ae4f4c521a7faffb1befe2fbba467f2c4d18)

Commit Message

Cédric Le Goater Sept. 17, 2020, 4:35 p.m. UTC
XIVE interrupt controller has some registers collecting internal
performance mesures. Expose them through a debug handler.

Unfortunately, these can not be reset without a reboot.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/xive-p9-regs.h | 14 ++++++++++++++
 hw/xive.c              | 25 +++++++++++++++++++++++++
 2 files changed, 39 insertions(+)
diff mbox series

Patch

diff --git a/include/xive-p9-regs.h b/include/xive-p9-regs.h
index fff341cca150..c1dcc7d205c2 100644
--- a/include/xive-p9-regs.h
+++ b/include/xive-p9-regs.h
@@ -163,6 +163,11 @@ 
 #define X_PC_VPC_CWATCH_DAT7	0x16f
 #define PC_VPC_CWATCH_DAT7	0x778
 
+#define X_PC_VPC_ADDITIONAL_PERF_1 0x174
+#define PC_VPC_ADDITIONAL_PERF_1   0x7A0
+#define X_PC_VPC_ADDITIONAL_PERF_2 0x175
+#define PC_VPC_ADDITIONAL_PERF_2   0x7A8
+
 /* VC0 register offsets */
 #define X_VC_GLOBAL_CONFIG	0x200
 #define VC_GLOBAL_CONFIG	0x800
@@ -262,6 +267,15 @@ 
 #define  VC_SBC_CONF_CIST_BOTH	PPC_BIT(45)
 #define  VC_SBC_CONF_NO_UPD_PRF	PPC_BIT(59)
 
+#define X_VC_EQC_ADDITIONAL_PERF_1 0x253
+#define VC_EQC_ADDITIONAL_PERF_1   0x970
+#define X_VC_EQC_ADDITIONAL_PERF_2 0x254
+#define VC_EQC_ADDITIONAL_PERF_2   0x978
+#define X_VC_IVC_ADDITIONAL_PERF   0x25B
+#define VC_IVC_ADDITIONAL_PERF	   0x9F0
+#define X_VC_SBC_ADDITIONAL_PERF   0x263
+#define VC_SBC_ADDITIONAL_PERF     0xA70
+
 /* VC1 register offsets */
 
 /* VSD Table address register definitions (shared) */
diff --git a/hw/xive.c b/hw/xive.c
index ccebb1e1d17d..b13beb575ba1 100644
--- a/hw/xive.c
+++ b/hw/xive.c
@@ -5359,6 +5359,27 @@  static int xive_vpt_read(struct opal_debug *d, void *buf, uint64_t size)
 	return n;
 }
 
+static int xive_perf_read(struct opal_debug *d, void *buf, uint64_t size)
+{
+	struct xive *x = d->private;
+	int n = 0;
+
+	n += snprintf(buf + n, size - n, "Performance counters [%d]\n", x->block_id);
+
+#define perf_read(reg)	\
+	n += snprintf(buf + n, size - n, "%30s = %016llx\n", #reg, \
+	      in_be64(x->ic_base + reg))
+
+	perf_read(PC_VPC_ADDITIONAL_PERF_1);
+	perf_read(PC_VPC_ADDITIONAL_PERF_2);
+	perf_read(VC_EQC_ADDITIONAL_PERF_1);
+	perf_read(VC_EQC_ADDITIONAL_PERF_2);
+	perf_read(VC_IVC_ADDITIONAL_PERF);
+	perf_read(VC_SBC_ADDITIONAL_PERF);
+
+	return n;
+}
+
 static const struct opal_debug_ops xive_ivt_ops = {
 	.read = xive_ivt_read,
 };
@@ -5371,6 +5392,9 @@  static const struct opal_debug_ops xive_esc_ops = {
 static const struct opal_debug_ops xive_vpt_ops = {
 	.read = xive_vpt_read,
 };
+static const struct opal_debug_ops xive_perf_ops = {
+	.read = xive_perf_read,
+};
 
 static const struct {
 	const char *name;
@@ -5380,6 +5404,7 @@  static const struct {
 	{ "xive-eqt",	&xive_eqt_ops,  },
 	{ "xive-esc",	&xive_esc_ops,  },
 	{ "xive-vpt",	&xive_vpt_ops,  },
+	{ "xive-perf",	&xive_perf_ops, },
 };
 
 static void xive_init_debug(struct xive *x)