From patchwork Mon Jul 20 04:39:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1332026 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B98D01MY8z9sRN for ; Mon, 20 Jul 2020 14:40:16 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=qDCHmoPq; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4B98Cz6zF3zDqQs for ; Mon, 20 Jul 2020 14:40:15 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::542; helo=mail-pg1-x542.google.com; envelope-from=oohall@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=qDCHmoPq; dkim-atps=neutral Received: from mail-pg1-x542.google.com (mail-pg1-x542.google.com [IPv6:2607:f8b0:4864:20::542]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4B98Cm6cBMzDqPK for ; Mon, 20 Jul 2020 14:40:02 +1000 (AEST) Received: by mail-pg1-x542.google.com with SMTP id m22so9690707pgv.9 for ; Sun, 19 Jul 2020 21:40:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=ZqOofFKC6191AhZXtBKe4wnyvhPYoARIZH0mkREUdAA=; b=qDCHmoPqc3/Ydk7yFWYXu2pIST7pB5pz6wO8ABKXRuiz6BGoL379wqiprbaQdOOGgI Os0TIBOhv6rPnqx5jM6gbUCC6f8RHWJ2IiO7BrFkwdtOrCOyPuToHWJyu1SARM1GouaF oAhpI5ynpUCWCleXGkZQpa4l85SxA5VYaBo3AuDSh8qXNMe3dSImf1/rjeqw67A3vHDN m9TRAesCvp7Pgi/IAqh4QRm6whLzGMiKiv8G1ObYMHHzhGwXpqx2H9du1SAgNum7hacH Ph/X/e8NhmwbU82SqgQLi2VinxOGaPpDuDqAgV4D+iIMtWmCo7zoIUaPn3utUCDw9khz keRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=ZqOofFKC6191AhZXtBKe4wnyvhPYoARIZH0mkREUdAA=; b=U7/tVLQMvDmarMkpHzr8g7gZ8mUgZ1U+xAuXX4gMIlNiWcrxsCrHVk7EVQ2sDx3m/+ Kp9oUg5oLYGbRN9e8sd5FNJryTNZ/inbw1qzFAxbXZnBhcDMKOgO6RNQI/UHCCtCRwE2 /rH4JQhADj538TmTQjPnXyfoLOe6dM0K0VDcUjtvpMkj8J6zMiG/Id33XjZia5Ki0BCQ MwpXMz67a0cyku0CrWF4tVHNPLoe2d/BXZwSBQ5RCCfHkag708Iwc2cPYETTVv4Gz0Qs JCwJVKg7QT614UM68i55LQvxeZOZytWSpmPSVxBrV+owqWWyJ9vwKkvfP9JoyVdr1rJO p3Hg== X-Gm-Message-State: AOAM531c4P+1Esbpim5qCqvonWou2dIK9nwTUku072FQSzN++70yRE3L xgQf3i5ASuKJUkI3nV+1++NXouW7dZI= X-Google-Smtp-Source: ABdhPJwOZ7KZoOc3NTUYKlfBQygceashmF9QtdlNbcuhcZh70Q8SOEQsTYQH2xKlnPpBOrcX2CiW/w== X-Received: by 2002:aa7:9422:: with SMTP id y2mr18417148pfo.211.1595220000105; Sun, 19 Jul 2020 21:40:00 -0700 (PDT) Received: from 192-168-1-18.tpgi.com.au ([203.220.204.169]) by smtp.gmail.com with ESMTPSA id t73sm15387883pfc.78.2020.07.19.21.39.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Jul 2020 21:39:59 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Mon, 20 Jul 2020 14:39:48 +1000 Message-Id: <20200720043948.1346998-1-oohall@gmail.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Subject: [Skiboot] [PATCH] hw/psi-p9: Configure IRQ offset before XIVE notify X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" When configuring the XIVE notification address any currently pending interrupts will be delivered once the the valid bit in the BAR is set. Currently we enable the notify BAR before we've configured the global interrupt number offset for the PSI interrupts. If any PSI interrupt is pending at this point we'll send an interrupt trigger notification for the wrong interrupt vector. This can potentially cause a checkstop since there may not be an EAS / IVT configure for that vector. Fix this by fixing the ordering so we setup the offset before the XIVE notification address. Cc: Cédric Le Goater Signed-off-by: Oliver O'Halloran Reviewed-by: Cédric Le Goater --- hw/psi.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/psi.c b/hw/psi.c index 339bc28c8c1a..8a0704729015 100644 --- a/hw/psi.c +++ b/hw/psi.c @@ -701,16 +701,6 @@ static void psi_init_p9_interrupts(struct psi *psi) prlog(PR_DEBUG, "PSI[0x%03x]: ESB MMIO at @%p\n", psi->chip_id, psi->esb_mmio); - /* Grab and configure the notification port */ - val = xive_get_notify_port(psi->chip_id, XIVE_HW_SRC_PSI); - val |= PSIHB_ESB_NOTIF_VALID; - out_be64(psi->regs + PSIHB_ESB_NOTIF_ADDR, val); - - /* Setup interrupt offset */ - val = xive_get_notify_base(psi->interrupt); - val <<= 32; - out_be64(psi->regs + PSIHB_IVT_OFFSET, val); - /* Register sources */ prlog(PR_DEBUG, "PSI[0x%03x]: Interrupts sources registered for P9 DD2.x\n", @@ -719,6 +709,16 @@ static void psi_init_p9_interrupts(struct psi *psi) 12, psi->esb_mmio, XIVE_SRC_LSI, psi, &psi_p9_irq_ops); + /* Setup interrupt offset */ + val = xive_get_notify_base(psi->interrupt); + val <<= 32; + out_be64(psi->regs + PSIHB_IVT_OFFSET, val); + + /* Grab and configure the notification port */ + val = xive_get_notify_port(psi->chip_id, XIVE_HW_SRC_PSI); + val |= PSIHB_ESB_NOTIF_VALID; + out_be64(psi->regs + PSIHB_ESB_NOTIF_ADDR, val); + /* Reset irq handling and switch to ESB mode */ out_be64(psi->regs + PSIHB_INTERRUPT_CONTROL, PSIHB_IRQ_RESET); out_be64(psi->regs + PSIHB_INTERRUPT_CONTROL, 0);