@@ -8,11 +8,21 @@
#include <processor.h>
#include <opal-api.h>
#include <cpu.h>
+#include <debug_descriptor.h>
+#include <console.h>
static struct dt_node *uv_fw_node;
static uint64_t uv_base_addr;
bool uv_present;
+struct memcons uv_memcons __section(".data.memcons") = {
+ .magic = MEMCONS_MAGIC,
+ .obuf_phys = INMEM_UV_CON_START,
+ .ibuf_phys = INMEM_UV_CON_START + INMEM_UV_CON_OUT_LEN,
+ .obuf_size = INMEM_UV_CON_OUT_LEN,
+ .ibuf_size = INMEM_UV_CON_IN_LEN,
+};
+
static void cpu_start_ultravisor(void *fdt)
{
uint64_t uv_entry = 0;
@@ -90,4 +100,7 @@ void init_uv()
uv_fw_sz, uv_base_addr, uv_dt_src);
memcpy((void *)uv_base_addr, (void *)uv_dt_src, uv_fw_sz);
+
+ dt_add_property_u64(uv_fw_node, "memcons", (u64)&uv_memcons);
+ debug_descriptor.uv_memcons_phys = (u64)&uv_memcons;
}
@@ -28,9 +28,12 @@ struct memcons {
};
extern struct memcons memcons;
+extern struct memcons uv_memcons;
#define INMEM_CON_IN_LEN 16
#define INMEM_CON_OUT_LEN (INMEM_CON_LEN - INMEM_CON_IN_LEN)
+#define INMEM_UV_CON_IN_LEN 16
+#define INMEM_UV_CON_OUT_LEN (INMEM_UV_CON_LEN - INMEM_UV_CON_IN_LEN)
/* Console driver */
struct con_ops {
@@ -20,6 +20,7 @@ struct debug_descriptor {
/* Memory console */
__be64 memcons_phys;
+ __be64 uv_memcons_phys;
__be32 memcons_tce;
__be32 memcons_obuf_tce;
__be32 memcons_ibuf_tce;
@@ -91,16 +91,20 @@
#define INMEM_CON_START (SKIBOOT_BASE + 0x01000000)
#define INMEM_CON_LEN 0x100000
-/* This is the location of HBRT console buffer at base + 17M */
-#define HBRT_CON_START (SKIBOOT_BASE + 0x01100000)
+/* This is the location of our ultravisor console buffer at base + 17M */
+#define INMEM_UV_CON_START (SKIBOOT_BASE + 0x01100000)
+#define INMEM_UV_CON_LEN 0x100000
+
+/* This is the location of HBRT console buffer at base + 18M */
+#define HBRT_CON_START (SKIBOOT_BASE + 0x01200000)
#define HBRT_CON_LEN 0x100000
-/* Tell FSP to put the init data at base + 20M, allocate 8M */
-#define SPIRA_HEAP_BASE (SKIBOOT_BASE + 0x01200000)
+/* Tell FSP to put the init data at base + 19M, allocate 8M */
+#define SPIRA_HEAP_BASE (SKIBOOT_BASE + 0x01300000)
#define SPIRA_HEAP_SIZE 0x00800000
/* This is our PSI TCE table. It's 256K entries on P8 */
-#define PSI_TCE_TABLE_BASE (SKIBOOT_BASE + 0x01a00000)
+#define PSI_TCE_TABLE_BASE (SKIBOOT_BASE + 0x01c00000)
#define PSI_TCE_TABLE_SIZE 0x00200000UL
/* This is our dump result table after MPIPL. Hostboot will write to this
@@ -119,7 +123,7 @@
*
* (Ensure this has at least a 64k alignment)
*/
-#define SKIBOOT_SIZE 0x01c10000
+#define SKIBOOT_SIZE 0x01e00000
/* We start laying out the CPU stacks from here, indexed by PIR
* each stack is STACK_SIZE in size (naturally aligned power of