From patchwork Fri Jun 12 11:37:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1308128 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49jzTV5n7Qz9sSy for ; Fri, 12 Jun 2020 21:46:38 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 49jzTV4ff1zDqx1 for ; Fri, 12 Jun 2020 21:46:38 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=kaod.org (client-ip=178.32.122.254; helo=4.mo7.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org X-Greylist: delayed 467 seconds by postgrey-1.36 at bilbo; Fri, 12 Jun 2020 21:46:08 AEST Received: from 4.mo7.mail-out.ovh.net (4.mo7.mail-out.ovh.net [178.32.122.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 49jzSw2HTwzDqwt for ; Fri, 12 Jun 2020 21:46:07 +1000 (AEST) Received: from player771.ha.ovh.net (unknown [10.110.103.118]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id 765BD16C8B6 for ; Fri, 12 Jun 2020 13:38:17 +0200 (CEST) Received: from kaod.org (82-64-250-170.subs.proxad.net [82.64.250.170]) (Authenticated sender: clg@kaod.org) by player771.ha.ovh.net (Postfix) with ESMTPSA id D52E91363DB61; Fri, 12 Jun 2020 11:38:11 +0000 (UTC) Authentication-Results: garm.ovh; auth=pass (GARM-97G002fd7b5261-340f-493c-a6e4-927c89149aff,EB3F143BCCF81B35F467F76D3EA0524591534A17) smtp.auth=clg@kaod.org From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Fri, 12 Jun 2020 13:37:29 +0200 Message-Id: <20200612113732.374240-9-clg@kaod.org> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20200612113732.374240-1-clg@kaod.org> References: <20200612113732.374240-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 7577587848753744857 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduhedrudeiuddggeehucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfesthekredtredtjeenucfhrhhomhepveorughrihgtucfnvgcuifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucggtffrrghtthgvrhhnpefgieetvdefudeghedvveejudeihfeiteffjeetjeeukefhgffgvedugedugedugfenucfkpheptddrtddrtddrtddpkedvrdeigedrvdehtddrudejtdenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehplhgrhigvrhejjedurdhhrgdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtohepshhkihgsohhotheslhhishhtshdrohiilhgrsghsrdhorhhg Subject: [Skiboot] [PATCH v2 08/11] xive/p9: Clarify indirect table allocation X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The XIVE interrupt controller uses a set of Virtualization Structure Tables (VST) which characteristics, type, address, size, are described by Virtual Structure Descriptors (VSD). A VSD is 64bit wide. The EQ and VP tables are indirect tables. The VSD points to a single page of VSDs each pointing to a page of virtual structures. Indirect tables are limited to a single top page which is enough to cover the whole range of EQs (24 bits) and VPs (19bits). Signed-off-by: Cédric Le Goater --- hw/xive.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 9bc78de9542c..8e7a51125f44 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -91,6 +91,7 @@ * local block of that chip */ +#define XIVE_VSD_SIZE sizeof(u64) /* BAR default values (should be initialized by HostBoot but for * now we do it). Based on the memory map document by Dave Larson @@ -180,7 +181,7 @@ #define XIVE_EQ_ORDER 20 /* 1M ENDs */ #define XIVE_EQ_COUNT (1ul << XIVE_EQ_ORDER) -#define IND_EQ_TABLE_SIZE ((XIVE_EQ_COUNT / EQ_PER_PAGE) * 8) +#define XIVE_EQ_TABLE_SIZE ((XIVE_EQ_COUNT / EQ_PER_PAGE) * XIVE_VSD_SIZE) #define XIVE_EQ_SHIFT (16 + 1) /* ESn + ESe pages */ @@ -217,7 +218,7 @@ #define MAX_VP_ORDER NVT_SHIFT /* 512k */ #define MAX_VP_COUNT (1ul << MAX_VP_ORDER) -#define IND_VP_TABLE_SIZE ((MAX_VP_COUNT / VP_PER_PAGE) * 8) +#define XIVE_VP_TABLE_SIZE ((MAX_VP_COUNT / VP_PER_PAGE) * XIVE_VSD_SIZE) /* Initial number of VPs (XXX Make it a variable ?). Round things * up to a max of 32 cores per chip @@ -1661,10 +1662,12 @@ static bool xive_prealloc_tables(struct xive *x) memset(x->ivt_base, 0, IVT_SIZE); xive_dbg(x, "IVT at %p size 0x%lx\n", x->ivt_base, IVT_SIZE); - /* Indirect EQ table. (XXX Align to 64K until I figure out the - * HW requirements) - */ - al = (IND_EQ_TABLE_SIZE + 0xffff) & ~0xffffull; + /* Indirect EQ table. Limited to one top page. */ + al = ALIGN_UP(XIVE_EQ_TABLE_SIZE, 0x10000); + if (al > 0x10000) { + xive_err(x, "EQ indirect table is too big !\n"); + return false; + } x->eq_ind_base = local_alloc(x->chip_id, al, al); if (!x->eq_ind_base) { xive_err(x, "Failed to allocate EQ indirect table\n"); @@ -1672,19 +1675,21 @@ static bool xive_prealloc_tables(struct xive *x) } memset(x->eq_ind_base, 0, al); xive_dbg(x, "EQi at %p size 0x%llx\n", x->eq_ind_base, al); - x->eq_ind_count = IND_EQ_TABLE_SIZE / 8; + x->eq_ind_count = XIVE_EQ_TABLE_SIZE / 8; - /* Indirect VP table. (XXX Align to 64K until I figure out the - * HW requirements) - */ - al = (IND_VP_TABLE_SIZE + 0xffff) & ~0xffffull; + /* Indirect VP table. Limited to one top page. */ + al = ALIGN_UP(XIVE_VP_TABLE_SIZE, 0x10000); + if (al > 0x10000) { + xive_err(x, "VP indirect table is too big !\n"); + return false; + } x->vp_ind_base = local_alloc(x->chip_id, al, al); if (!x->vp_ind_base) { xive_err(x, "Failed to allocate VP indirect table\n"); return false; } xive_dbg(x, "VPi at %p size 0x%llx\n", x->vp_ind_base, al); - x->vp_ind_count = IND_VP_TABLE_SIZE / 8; + x->vp_ind_count = XIVE_VP_TABLE_SIZE / 8; memset(x->vp_ind_base, 0, al); /* Populate/initialize VP/EQs indirect backing */