diff mbox series

[v2,06/11] xive/p9: Introduce XIVE_EQ_SHIFT

Message ID 20200612113732.374240-7-clg@kaod.org
State Accepted
Headers show
Series xive/p9: various small cleanups | expand

Checks

Context Check Description
snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot-dco success Signed-off-by present
snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot success Test snowpatch/job/snowpatch-skiboot on branch master
snowpatch_ozlabs/apply_patch success Successfully applied on branch master (fe70fbb78d33abea788a3221bc409a7c50c019c3)

Commit Message

Cédric Le Goater June 12, 2020, 11:37 a.m. UTC
Each EQ descriptor is associated with a pair of ESB pages. The even
page controls the ESn PQ bits and the odd page controls the ESe PQ
bits.

Reviewed-by: Gustavo Romero <gromero@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/xive.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/hw/xive.c b/hw/xive.c
index 3e7b87fdfd17..a106bd593052 100644
--- a/hw/xive.c
+++ b/hw/xive.c
@@ -100,7 +100,6 @@ 
 /* Use 64K for everything by default */
 #define IC_PAGE_SIZE	0x10000
 #define TM_PAGE_SIZE	0x10000
-#define EQ_ESB_SHIFT	(16 + 1)
 
 /* VC BAR contains set translations for the ESBs and the EQs.
  *
@@ -182,6 +181,8 @@ 
 #define EQ_PER_PAGE		(0x10000 / 32) // Use sizeof ?
 #define IND_EQ_TABLE_SIZE	((XIVE_EQ_COUNT / EQ_PER_PAGE) * 8)
 
+#define XIVE_EQ_SHIFT		(16 + 1) /* ESn + ESe pages */
+
 /* Number of priorities (and thus EQDs) we allocate for each VP */
 #define NUM_INT_PRIORITIES	8
 
@@ -2676,7 +2677,7 @@  static struct xive *init_one_xive(struct dt_node *np)
 	/* Register escalation sources */
 	__xive_register_source(x, &x->esc_irqs,
 			       MAKE_ESCALATION_GIRQ(x->block_id, 0),
-			       XIVE_EQ_COUNT, EQ_ESB_SHIFT,
+			       XIVE_EQ_COUNT, XIVE_EQ_SHIFT,
 			       x->eq_mmio, XIVE_SRC_EOI_PAGE1,
 			       false, NULL, NULL);