| Message ID | 20200506105716.21401-1-svaidy@linux.ibm.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | Detect fused core mode and bail out | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | Successfully applied on branch master (0f1937ef40fca0c3212a9dff1010b832a24fb063) |
| snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot | success | Test snowpatch/job/snowpatch-skiboot on branch master |
| snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot-dco | success | Signed-off-by present |
On Wed, 6 May 2020 at 10:57, Vaidyanathan Srinivasan <svaidy@linux.ibm.com> wrote: > > From: Joel Stanley <joel@jms.id.au> > > Fused code mode is currently not supported in OPAL. Continuing to > boot the system would result in errors at later stages of boot. > > Wait for console to be up and print message for developers to check > and fix the system modes. > > Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com> > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > Test on ZZ: > [ 160.055440456,7] CPU: Boot CPU PIR is 0x0840 PVR is 0x004e0203 > ... > ... > [ 171.356626043,3] NUVOTON: i2c device inaccessible > [ 171.356627241,5] TPM: tpm node 0x3052d768 disabled > [ 171.356628427,6] STB: no compatible tpm device found! > [ 171.356630080,5] Trying to load OPAL LID 80f00103... > [ 171.356631982,6] OPAL: Using FSP OPAL console > [ 171.356632943,3] CPU: Detected unsupported fused core mode > [ 171.356634425,3] *********************************************** > [ 171.356635414,3] < assert failed at core/init.c:1285 > > > Test in Fleetwood with additional PVR patches: > [ 438.337801715,7] CPU: Boot CPU PIR is 0x0110 PVR is 0x004e2102 > ... > ... > [ 441.222264932,3] CPU: Detected unsupported fused core mode > [ 441.222266127,3] *********************************************** > [ 441.222266980,3] < assert failed at core/init.c:1285 > > > This minimal patch can be included in skiboot stable streams to help > developers detect and fix unsupported modes. Cool. I tested it on this machine: [ 96.493391427,7] CPU: Boot CPU PIR is 0x0030 PVR is 0x004e0202 ... [ 96.498644199,5] CHIP: Chip ID 0000 type: P9N DD2.21 [ 96.498700280,5] CHIP: Chip ID 0008 type: P9N DD2.21 [ 96.499290145,5] PLAT: Using virtual UART [ 96.499595656,5] PLAT: Detected Witherspoon platform ... [ 98.179946233,3] CPU: Detected unsupported fused core mode [ 98.179976245,3] *********************************************** [ 98.180013135,3] < assert failed at core/init.c:1289 > So it does what I was after. Thanks! Tested-by: Joel Stanley <joel@jms.id.au> > > --Vaidy > --- > core/init.c | 4 ++++ > include/processor.h | 16 ++++++++++++++++ > 2 files changed, 20 insertions(+) > > diff --git a/core/init.c b/core/init.c > index 595d087f..89240f60 100644 > --- a/core/init.c > +++ b/core/init.c > @@ -1280,6 +1280,10 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) > /* Install the OPAL Console handlers */ > init_opal_console(); > > + if(is_fused_core(mfspr(SPR_PVR))) { > + prerror("CPU: Detected unsupported fused core mode\n"); > + abort(); > + } > /* > * Some platforms set a flag to wait for SBE validation to be > * performed by the BMC. If this occurs it leaves the SBE in a > diff --git a/include/processor.h b/include/processor.h > index 57c2ee13..42002fc0 100644 > --- a/include/processor.h > +++ b/include/processor.h > @@ -173,10 +173,12 @@ > > /* PVR bits */ > #define SPR_PVR_TYPE 0xffff0000 > +#define SPR_PVR_CHIP_TYPE 0x0000f000 > #define SPR_PVR_VERS_MAJ 0x00000f00 > #define SPR_PVR_VERS_MIN 0x000000ff > > #define PVR_TYPE(_pvr) GETFIELD(SPR_PVR_TYPE, _pvr) > +#define PVR_CHIP_TYPE(_pvr) GETFIELD(SPR_PVR_CHIP_TYPE, _pvr) > #define PVR_VERS_MAJ(_pvr) GETFIELD(SPR_PVR_VERS_MAJ, _pvr) > #define PVR_VERS_MIN(_pvr) GETFIELD(SPR_PVR_VERS_MIN, _pvr) > > @@ -228,6 +230,20 @@ static inline bool is_power9n(uint32_t version) > return true; > } > > +static inline bool is_fused_core(uint32_t version) > +{ > + if (PVR_TYPE(version) != PVR_TYPE_P9) > + return false; > + > + switch(PVR_CHIP_TYPE(version)) { > + case 0: > + case 2: > + return true; > + default: > + return false; > + } > +} > + > #ifndef __TEST__ > > /* > -- > 2.26.2 >
On Wed, May 6, 2020 at 8:57 PM Vaidyanathan Srinivasan <svaidy@linux.ibm.com> wrote: > > From: Joel Stanley <joel@jms.id.au> > > Fused code mode is currently not supported in OPAL. Continuing to > boot the system would result in errors at later stages of boot. > > Wait for console to be up and print message for developers to check > and fix the system modes. > > Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com> > Signed-off-by: Joel Stanley <joel@jms.id.au> Thanks, merged as 482f18adf21eeb5f6ce2a93334725509a8f6f0cd
diff --git a/core/init.c b/core/init.c index 595d087f..89240f60 100644 --- a/core/init.c +++ b/core/init.c @@ -1280,6 +1280,10 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) /* Install the OPAL Console handlers */ init_opal_console(); + if(is_fused_core(mfspr(SPR_PVR))) { + prerror("CPU: Detected unsupported fused core mode\n"); + abort(); + } /* * Some platforms set a flag to wait for SBE validation to be * performed by the BMC. If this occurs it leaves the SBE in a diff --git a/include/processor.h b/include/processor.h index 57c2ee13..42002fc0 100644 --- a/include/processor.h +++ b/include/processor.h @@ -173,10 +173,12 @@ /* PVR bits */ #define SPR_PVR_TYPE 0xffff0000 +#define SPR_PVR_CHIP_TYPE 0x0000f000 #define SPR_PVR_VERS_MAJ 0x00000f00 #define SPR_PVR_VERS_MIN 0x000000ff #define PVR_TYPE(_pvr) GETFIELD(SPR_PVR_TYPE, _pvr) +#define PVR_CHIP_TYPE(_pvr) GETFIELD(SPR_PVR_CHIP_TYPE, _pvr) #define PVR_VERS_MAJ(_pvr) GETFIELD(SPR_PVR_VERS_MAJ, _pvr) #define PVR_VERS_MIN(_pvr) GETFIELD(SPR_PVR_VERS_MIN, _pvr) @@ -228,6 +230,20 @@ static inline bool is_power9n(uint32_t version) return true; } +static inline bool is_fused_core(uint32_t version) +{ + if (PVR_TYPE(version) != PVR_TYPE_P9) + return false; + + switch(PVR_CHIP_TYPE(version)) { + case 0: + case 2: + return true; + default: + return false; + } +} + #ifndef __TEST__ /*